1 /*
2  * drivers/gpu/drm/omapdrm/omap_crtc.c
3  *
4  * Copyright (C) 2011 Texas Instruments
5  * Author: Rob Clark <rob@ti.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_crtc.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_mode.h>
25 #include <drm/drm_plane_helper.h>
26 
27 #include "omap_drv.h"
28 
29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
30 
31 struct omap_crtc {
32 	struct drm_crtc base;
33 
34 	const char *name;
35 	enum omap_channel channel;
36 
37 	/*
38 	 * Temporary: eventually this will go away, but it is needed
39 	 * for now to keep the output's happy.  (They only need
40 	 * mgr->id.)  Eventually this will be replaced w/ something
41 	 * more common-panel-framework-y
42 	 */
43 	struct omap_overlay_manager *mgr;
44 
45 	struct omap_video_timings timings;
46 
47 	struct omap_drm_irq vblank_irq;
48 	struct omap_drm_irq error_irq;
49 
50 	bool ignore_digit_sync_lost;
51 
52 	bool pending;
53 	wait_queue_head_t pending_wait;
54 };
55 
56 /* -----------------------------------------------------------------------------
57  * Helper Functions
58  */
59 
60 uint32_t pipe2vbl(struct drm_crtc *crtc)
61 {
62 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
63 
64 	return dispc_mgr_get_vsync_irq(omap_crtc->channel);
65 }
66 
67 struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
68 {
69 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
70 	return &omap_crtc->timings;
71 }
72 
73 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
74 {
75 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
76 	return omap_crtc->channel;
77 }
78 
79 int omap_crtc_wait_pending(struct drm_crtc *crtc)
80 {
81 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
82 
83 	return wait_event_timeout(omap_crtc->pending_wait,
84 				  !omap_crtc->pending,
85 				  msecs_to_jiffies(50));
86 }
87 
88 /* -----------------------------------------------------------------------------
89  * DSS Manager Functions
90  */
91 
92 /*
93  * Manager-ops, callbacks from output when they need to configure
94  * the upstream part of the video pipe.
95  *
96  * Most of these we can ignore until we add support for command-mode
97  * panels.. for video-mode the crtc-helpers already do an adequate
98  * job of sequencing the setup of the video pipe in the proper order
99  */
100 
101 /* ovl-mgr-id -> crtc */
102 static struct omap_crtc *omap_crtcs[8];
103 
104 /* we can probably ignore these until we support command-mode panels: */
105 static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
106 		struct omap_dss_device *dst)
107 {
108 	if (mgr->output)
109 		return -EINVAL;
110 
111 	if ((mgr->supported_outputs & dst->id) == 0)
112 		return -EINVAL;
113 
114 	dst->manager = mgr;
115 	mgr->output = dst;
116 
117 	return 0;
118 }
119 
120 static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
121 		struct omap_dss_device *dst)
122 {
123 	mgr->output->manager = NULL;
124 	mgr->output = NULL;
125 }
126 
127 static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
128 {
129 }
130 
131 /* Called only from the encoder enable/disable and suspend/resume handlers. */
132 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
133 {
134 	struct drm_device *dev = crtc->dev;
135 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
136 	enum omap_channel channel = omap_crtc->channel;
137 	struct omap_irq_wait *wait;
138 	u32 framedone_irq, vsync_irq;
139 	int ret;
140 
141 	if (dispc_mgr_is_enabled(channel) == enable)
142 		return;
143 
144 	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
145 		/*
146 		 * Digit output produces some sync lost interrupts during the
147 		 * first frame when enabling, so we need to ignore those.
148 		 */
149 		omap_crtc->ignore_digit_sync_lost = true;
150 	}
151 
152 	framedone_irq = dispc_mgr_get_framedone_irq(channel);
153 	vsync_irq = dispc_mgr_get_vsync_irq(channel);
154 
155 	if (enable) {
156 		wait = omap_irq_wait_init(dev, vsync_irq, 1);
157 	} else {
158 		/*
159 		 * When we disable the digit output, we need to wait for
160 		 * FRAMEDONE to know that DISPC has finished with the output.
161 		 *
162 		 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
163 		 * that case we need to use vsync interrupt, and wait for both
164 		 * even and odd frames.
165 		 */
166 
167 		if (framedone_irq)
168 			wait = omap_irq_wait_init(dev, framedone_irq, 1);
169 		else
170 			wait = omap_irq_wait_init(dev, vsync_irq, 2);
171 	}
172 
173 	dispc_mgr_enable(channel, enable);
174 
175 	ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
176 	if (ret) {
177 		dev_err(dev->dev, "%s: timeout waiting for %s\n",
178 				omap_crtc->name, enable ? "enable" : "disable");
179 	}
180 
181 	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
182 		omap_crtc->ignore_digit_sync_lost = false;
183 		/* make sure the irq handler sees the value above */
184 		mb();
185 	}
186 }
187 
188 
189 static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
190 {
191 	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
192 	struct omap_overlay_manager_info info;
193 
194 	memset(&info, 0, sizeof(info));
195 	info.default_color = 0x00000000;
196 	info.trans_key = 0x00000000;
197 	info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
198 	info.trans_enabled = false;
199 
200 	dispc_mgr_setup(omap_crtc->channel, &info);
201 	dispc_mgr_set_timings(omap_crtc->channel,
202 			&omap_crtc->timings);
203 	omap_crtc_set_enabled(&omap_crtc->base, true);
204 
205 	return 0;
206 }
207 
208 static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
209 {
210 	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
211 
212 	omap_crtc_set_enabled(&omap_crtc->base, false);
213 }
214 
215 static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
216 		const struct omap_video_timings *timings)
217 {
218 	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
219 	DBG("%s", omap_crtc->name);
220 	omap_crtc->timings = *timings;
221 }
222 
223 static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
224 		const struct dss_lcd_mgr_config *config)
225 {
226 	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
227 	DBG("%s", omap_crtc->name);
228 	dispc_mgr_set_lcd_config(omap_crtc->channel, config);
229 }
230 
231 static int omap_crtc_dss_register_framedone(
232 		struct omap_overlay_manager *mgr,
233 		void (*handler)(void *), void *data)
234 {
235 	return 0;
236 }
237 
238 static void omap_crtc_dss_unregister_framedone(
239 		struct omap_overlay_manager *mgr,
240 		void (*handler)(void *), void *data)
241 {
242 }
243 
244 static const struct dss_mgr_ops mgr_ops = {
245 	.connect = omap_crtc_dss_connect,
246 	.disconnect = omap_crtc_dss_disconnect,
247 	.start_update = omap_crtc_dss_start_update,
248 	.enable = omap_crtc_dss_enable,
249 	.disable = omap_crtc_dss_disable,
250 	.set_timings = omap_crtc_dss_set_timings,
251 	.set_lcd_config = omap_crtc_dss_set_lcd_config,
252 	.register_framedone_handler = omap_crtc_dss_register_framedone,
253 	.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
254 };
255 
256 /* -----------------------------------------------------------------------------
257  * Setup, Flush and Page Flip
258  */
259 
260 static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
261 {
262 	struct drm_pending_vblank_event *event;
263 	struct drm_device *dev = crtc->dev;
264 	unsigned long flags;
265 
266 	event = crtc->state->event;
267 
268 	if (!event)
269 		return;
270 
271 	spin_lock_irqsave(&dev->event_lock, flags);
272 
273 	list_del(&event->base.link);
274 
275 	/*
276 	 * Queue the event for delivery if it's still linked to a file
277 	 * handle, otherwise just destroy it.
278 	 */
279 	if (event->base.file_priv)
280 		drm_crtc_send_vblank_event(crtc, event);
281 	else
282 		event->base.destroy(&event->base);
283 
284 	spin_unlock_irqrestore(&dev->event_lock, flags);
285 }
286 
287 static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
288 {
289 	struct omap_crtc *omap_crtc =
290 			container_of(irq, struct omap_crtc, error_irq);
291 
292 	if (omap_crtc->ignore_digit_sync_lost) {
293 		irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
294 		if (!irqstatus)
295 			return;
296 	}
297 
298 	DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
299 }
300 
301 static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
302 {
303 	struct omap_crtc *omap_crtc =
304 			container_of(irq, struct omap_crtc, vblank_irq);
305 	struct drm_device *dev = omap_crtc->base.dev;
306 
307 	if (dispc_mgr_go_busy(omap_crtc->channel))
308 		return;
309 
310 	DBG("%s: apply done", omap_crtc->name);
311 
312 	__omap_irq_unregister(dev, &omap_crtc->vblank_irq);
313 
314 	rmb();
315 	WARN_ON(!omap_crtc->pending);
316 	omap_crtc->pending = false;
317 	wmb();
318 
319 	/* wake up userspace */
320 	omap_crtc_complete_page_flip(&omap_crtc->base);
321 
322 	/* wake up omap_atomic_complete */
323 	wake_up(&omap_crtc->pending_wait);
324 }
325 
326 /* -----------------------------------------------------------------------------
327  * CRTC Functions
328  */
329 
330 static void omap_crtc_destroy(struct drm_crtc *crtc)
331 {
332 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
333 
334 	DBG("%s", omap_crtc->name);
335 
336 	WARN_ON(omap_crtc->vblank_irq.registered);
337 	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
338 
339 	drm_crtc_cleanup(crtc);
340 
341 	kfree(omap_crtc);
342 }
343 
344 static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
345 		const struct drm_display_mode *mode,
346 		struct drm_display_mode *adjusted_mode)
347 {
348 	return true;
349 }
350 
351 static void omap_crtc_enable(struct drm_crtc *crtc)
352 {
353 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
354 
355 	DBG("%s", omap_crtc->name);
356 
357 	rmb();
358 	WARN_ON(omap_crtc->pending);
359 	omap_crtc->pending = true;
360 	wmb();
361 
362 	omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
363 
364 	drm_crtc_vblank_on(crtc);
365 }
366 
367 static void omap_crtc_disable(struct drm_crtc *crtc)
368 {
369 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
370 
371 	DBG("%s", omap_crtc->name);
372 
373 	drm_crtc_vblank_off(crtc);
374 }
375 
376 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
377 {
378 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
379 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
380 
381 	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
382 	    omap_crtc->name, mode->base.id, mode->name,
383 	    mode->vrefresh, mode->clock,
384 	    mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
385 	    mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
386 	    mode->type, mode->flags);
387 
388 	copy_timings_drm_to_omap(&omap_crtc->timings, mode);
389 }
390 
391 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
392                                   struct drm_crtc_state *old_crtc_state)
393 {
394 }
395 
396 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
397                                   struct drm_crtc_state *old_crtc_state)
398 {
399 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
400 
401 	WARN_ON(omap_crtc->vblank_irq.registered);
402 
403 	if (dispc_mgr_is_enabled(omap_crtc->channel)) {
404 
405 		DBG("%s: GO", omap_crtc->name);
406 
407 		rmb();
408 		WARN_ON(omap_crtc->pending);
409 		omap_crtc->pending = true;
410 		wmb();
411 
412 		dispc_mgr_go(omap_crtc->channel);
413 		omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
414 	}
415 }
416 
417 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
418 					 struct drm_crtc_state *state,
419 					 struct drm_property *property,
420 					 uint64_t val)
421 {
422 	struct drm_plane_state *plane_state;
423 	struct drm_plane *plane = crtc->primary;
424 
425 	/*
426 	 * Delegate property set to the primary plane. Get the plane state and
427 	 * set the property directly.
428 	 */
429 
430 	plane_state = drm_atomic_get_plane_state(state->state, plane);
431 	if (!plane_state)
432 		return -EINVAL;
433 
434 	return drm_atomic_plane_set_property(plane, plane_state, property, val);
435 }
436 
437 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
438 					 const struct drm_crtc_state *state,
439 					 struct drm_property *property,
440 					 uint64_t *val)
441 {
442 	/*
443 	 * Delegate property get to the primary plane. The
444 	 * drm_atomic_plane_get_property() function isn't exported, but can be
445 	 * called through drm_object_property_get_value() as that will call
446 	 * drm_atomic_get_property() for atomic drivers.
447 	 */
448 	return drm_object_property_get_value(&crtc->primary->base, property,
449 					     val);
450 }
451 
452 static const struct drm_crtc_funcs omap_crtc_funcs = {
453 	.reset = drm_atomic_helper_crtc_reset,
454 	.set_config = drm_atomic_helper_set_config,
455 	.destroy = omap_crtc_destroy,
456 	.page_flip = drm_atomic_helper_page_flip,
457 	.set_property = drm_atomic_helper_crtc_set_property,
458 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
459 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
460 	.atomic_set_property = omap_crtc_atomic_set_property,
461 	.atomic_get_property = omap_crtc_atomic_get_property,
462 };
463 
464 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
465 	.mode_fixup = omap_crtc_mode_fixup,
466 	.mode_set_nofb = omap_crtc_mode_set_nofb,
467 	.disable = omap_crtc_disable,
468 	.enable = omap_crtc_enable,
469 	.atomic_begin = omap_crtc_atomic_begin,
470 	.atomic_flush = omap_crtc_atomic_flush,
471 };
472 
473 /* -----------------------------------------------------------------------------
474  * Init and Cleanup
475  */
476 
477 static const char *channel_names[] = {
478 	[OMAP_DSS_CHANNEL_LCD] = "lcd",
479 	[OMAP_DSS_CHANNEL_DIGIT] = "tv",
480 	[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
481 	[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
482 };
483 
484 void omap_crtc_pre_init(void)
485 {
486 	dss_install_mgr_ops(&mgr_ops);
487 }
488 
489 void omap_crtc_pre_uninit(void)
490 {
491 	dss_uninstall_mgr_ops();
492 }
493 
494 /* initialize crtc */
495 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
496 		struct drm_plane *plane, enum omap_channel channel, int id)
497 {
498 	struct drm_crtc *crtc = NULL;
499 	struct omap_crtc *omap_crtc;
500 	int ret;
501 
502 	DBG("%s", channel_names[channel]);
503 
504 	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
505 	if (!omap_crtc)
506 		return NULL;
507 
508 	crtc = &omap_crtc->base;
509 
510 	init_waitqueue_head(&omap_crtc->pending_wait);
511 
512 	omap_crtc->channel = channel;
513 	omap_crtc->name = channel_names[channel];
514 
515 	omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
516 	omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
517 
518 	omap_crtc->error_irq.irqmask =
519 			dispc_mgr_get_sync_lost_irq(channel);
520 	omap_crtc->error_irq.irq = omap_crtc_error_irq;
521 	omap_irq_register(dev, &omap_crtc->error_irq);
522 
523 	/* temporary: */
524 	omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
525 
526 	ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
527 					&omap_crtc_funcs);
528 	if (ret < 0) {
529 		kfree(omap_crtc);
530 		return NULL;
531 	}
532 
533 	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
534 
535 	omap_plane_install_properties(crtc->primary, &crtc->base);
536 
537 	omap_crtcs[channel] = omap_crtc;
538 
539 	return crtc;
540 }
541