1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Rob Clark <rob@ti.com> 5 */ 6 7 #include <linux/math64.h> 8 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_crtc.h> 12 #include <drm/drm_mode.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/drm_vblank.h> 15 16 #include "omap_drv.h" 17 18 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) 19 20 struct omap_crtc_state { 21 /* Must be first. */ 22 struct drm_crtc_state base; 23 /* Shadow values for legacy userspace support. */ 24 unsigned int rotation; 25 unsigned int zpos; 26 bool manually_updated; 27 }; 28 29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) 30 31 struct omap_crtc { 32 struct drm_crtc base; 33 34 const char *name; 35 struct omap_drm_pipeline *pipe; 36 enum omap_channel channel; 37 38 struct videomode vm; 39 40 bool ignore_digit_sync_lost; 41 42 bool enabled; 43 bool pending; 44 wait_queue_head_t pending_wait; 45 struct drm_pending_vblank_event *event; 46 struct delayed_work update_work; 47 48 void (*framedone_handler)(void *); 49 void *framedone_handler_data; 50 }; 51 52 /* ----------------------------------------------------------------------------- 53 * Helper Functions 54 */ 55 56 struct videomode *omap_crtc_timings(struct drm_crtc *crtc) 57 { 58 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 59 return &omap_crtc->vm; 60 } 61 62 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) 63 { 64 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 65 return omap_crtc->channel; 66 } 67 68 static bool omap_crtc_is_pending(struct drm_crtc *crtc) 69 { 70 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 71 unsigned long flags; 72 bool pending; 73 74 spin_lock_irqsave(&crtc->dev->event_lock, flags); 75 pending = omap_crtc->pending; 76 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 77 78 return pending; 79 } 80 81 int omap_crtc_wait_pending(struct drm_crtc *crtc) 82 { 83 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 84 85 /* 86 * Timeout is set to a "sufficiently" high value, which should cover 87 * a single frame refresh even on slower displays. 88 */ 89 return wait_event_timeout(omap_crtc->pending_wait, 90 !omap_crtc_is_pending(crtc), 91 msecs_to_jiffies(250)); 92 } 93 94 /* ----------------------------------------------------------------------------- 95 * DSS Manager Functions 96 */ 97 98 /* 99 * Manager-ops, callbacks from output when they need to configure 100 * the upstream part of the video pipe. 101 */ 102 103 void omap_crtc_dss_start_update(struct omap_drm_private *priv, 104 enum omap_channel channel) 105 { 106 dispc_mgr_enable(priv->dispc, channel, true); 107 } 108 109 /* Called only from the encoder enable/disable and suspend/resume handlers. */ 110 void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) 111 { 112 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); 113 struct drm_device *dev = crtc->dev; 114 struct omap_drm_private *priv = dev->dev_private; 115 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 116 enum omap_channel channel = omap_crtc->channel; 117 struct omap_irq_wait *wait; 118 u32 framedone_irq, vsync_irq; 119 int ret; 120 121 if (WARN_ON(omap_crtc->enabled == enable)) 122 return; 123 124 if (omap_state->manually_updated) { 125 omap_irq_enable_framedone(crtc, enable); 126 omap_crtc->enabled = enable; 127 return; 128 } 129 130 if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) { 131 dispc_mgr_enable(priv->dispc, channel, enable); 132 omap_crtc->enabled = enable; 133 return; 134 } 135 136 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { 137 /* 138 * Digit output produces some sync lost interrupts during the 139 * first frame when enabling, so we need to ignore those. 140 */ 141 omap_crtc->ignore_digit_sync_lost = true; 142 } 143 144 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, 145 channel); 146 vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel); 147 148 if (enable) { 149 wait = omap_irq_wait_init(dev, vsync_irq, 1); 150 } else { 151 /* 152 * When we disable the digit output, we need to wait for 153 * FRAMEDONE to know that DISPC has finished with the output. 154 * 155 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in 156 * that case we need to use vsync interrupt, and wait for both 157 * even and odd frames. 158 */ 159 160 if (framedone_irq) 161 wait = omap_irq_wait_init(dev, framedone_irq, 1); 162 else 163 wait = omap_irq_wait_init(dev, vsync_irq, 2); 164 } 165 166 dispc_mgr_enable(priv->dispc, channel, enable); 167 omap_crtc->enabled = enable; 168 169 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); 170 if (ret) { 171 dev_err(dev->dev, "%s: timeout waiting for %s\n", 172 omap_crtc->name, enable ? "enable" : "disable"); 173 } 174 175 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { 176 omap_crtc->ignore_digit_sync_lost = false; 177 /* make sure the irq handler sees the value above */ 178 mb(); 179 } 180 } 181 182 183 int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel) 184 { 185 struct drm_crtc *crtc = priv->channels[channel]->crtc; 186 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 187 188 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, 189 &omap_crtc->vm); 190 omap_crtc_set_enabled(&omap_crtc->base, true); 191 192 return 0; 193 } 194 195 void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel) 196 { 197 struct drm_crtc *crtc = priv->channels[channel]->crtc; 198 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 199 200 omap_crtc_set_enabled(&omap_crtc->base, false); 201 } 202 203 void omap_crtc_dss_set_timings(struct omap_drm_private *priv, 204 enum omap_channel channel, 205 const struct videomode *vm) 206 { 207 struct drm_crtc *crtc = priv->channels[channel]->crtc; 208 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 209 210 DBG("%s", omap_crtc->name); 211 omap_crtc->vm = *vm; 212 } 213 214 void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv, 215 enum omap_channel channel, 216 const struct dss_lcd_mgr_config *config) 217 { 218 struct drm_crtc *crtc = priv->channels[channel]->crtc; 219 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 220 221 DBG("%s", omap_crtc->name); 222 dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel, 223 config); 224 } 225 226 int omap_crtc_dss_register_framedone( 227 struct omap_drm_private *priv, enum omap_channel channel, 228 void (*handler)(void *), void *data) 229 { 230 struct drm_crtc *crtc = priv->channels[channel]->crtc; 231 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 232 struct drm_device *dev = omap_crtc->base.dev; 233 234 if (omap_crtc->framedone_handler) 235 return -EBUSY; 236 237 dev_dbg(dev->dev, "register framedone %s", omap_crtc->name); 238 239 omap_crtc->framedone_handler = handler; 240 omap_crtc->framedone_handler_data = data; 241 242 return 0; 243 } 244 245 void omap_crtc_dss_unregister_framedone( 246 struct omap_drm_private *priv, enum omap_channel channel, 247 void (*handler)(void *), void *data) 248 { 249 struct drm_crtc *crtc = priv->channels[channel]->crtc; 250 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 251 struct drm_device *dev = omap_crtc->base.dev; 252 253 dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name); 254 255 WARN_ON(omap_crtc->framedone_handler != handler); 256 WARN_ON(omap_crtc->framedone_handler_data != data); 257 258 omap_crtc->framedone_handler = NULL; 259 omap_crtc->framedone_handler_data = NULL; 260 } 261 262 /* ----------------------------------------------------------------------------- 263 * Setup, Flush and Page Flip 264 */ 265 266 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus) 267 { 268 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 269 270 if (omap_crtc->ignore_digit_sync_lost) { 271 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; 272 if (!irqstatus) 273 return; 274 } 275 276 DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); 277 } 278 279 void omap_crtc_vblank_irq(struct drm_crtc *crtc) 280 { 281 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 282 struct drm_device *dev = omap_crtc->base.dev; 283 struct omap_drm_private *priv = dev->dev_private; 284 bool pending; 285 286 spin_lock(&crtc->dev->event_lock); 287 /* 288 * If the dispc is busy we're racing the flush operation. Try again on 289 * the next vblank interrupt. 290 */ 291 if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) { 292 spin_unlock(&crtc->dev->event_lock); 293 return; 294 } 295 296 /* Send the vblank event if one has been requested. */ 297 if (omap_crtc->event) { 298 drm_crtc_send_vblank_event(crtc, omap_crtc->event); 299 omap_crtc->event = NULL; 300 } 301 302 pending = omap_crtc->pending; 303 omap_crtc->pending = false; 304 spin_unlock(&crtc->dev->event_lock); 305 306 if (pending) 307 drm_crtc_vblank_put(crtc); 308 309 /* Wake up omap_atomic_complete. */ 310 wake_up(&omap_crtc->pending_wait); 311 312 DBG("%s: apply done", omap_crtc->name); 313 } 314 315 void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus) 316 { 317 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 318 319 if (!omap_crtc->framedone_handler) 320 return; 321 322 omap_crtc->framedone_handler(omap_crtc->framedone_handler_data); 323 324 spin_lock(&crtc->dev->event_lock); 325 /* Send the vblank event if one has been requested. */ 326 if (omap_crtc->event) { 327 drm_crtc_send_vblank_event(crtc, omap_crtc->event); 328 omap_crtc->event = NULL; 329 } 330 omap_crtc->pending = false; 331 spin_unlock(&crtc->dev->event_lock); 332 333 /* Wake up omap_atomic_complete. */ 334 wake_up(&omap_crtc->pending_wait); 335 } 336 337 void omap_crtc_flush(struct drm_crtc *crtc) 338 { 339 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 340 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); 341 342 if (!omap_state->manually_updated) 343 return; 344 345 if (!delayed_work_pending(&omap_crtc->update_work)) 346 schedule_delayed_work(&omap_crtc->update_work, 0); 347 } 348 349 static void omap_crtc_manual_display_update(struct work_struct *data) 350 { 351 struct omap_crtc *omap_crtc = 352 container_of(data, struct omap_crtc, update_work.work); 353 struct omap_dss_device *dssdev = omap_crtc->pipe->output; 354 struct drm_device *dev = omap_crtc->base.dev; 355 int ret; 356 357 if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->update) 358 return; 359 360 ret = dssdev->dsi_ops->update(dssdev); 361 if (ret < 0) { 362 spin_lock_irq(&dev->event_lock); 363 omap_crtc->pending = false; 364 spin_unlock_irq(&dev->event_lock); 365 wake_up(&omap_crtc->pending_wait); 366 } 367 } 368 369 static s16 omap_crtc_s31_32_to_s2_8(s64 coef) 370 { 371 u64 sign_bit = 1ULL << 63; 372 u64 cbits = (u64)coef; 373 374 s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1ff); 375 376 if (cbits & sign_bit) 377 ret = -ret; 378 379 return ret; 380 } 381 382 static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm, 383 struct omap_dss_cpr_coefs *cpr) 384 { 385 cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]); 386 cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]); 387 cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]); 388 cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]); 389 cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]); 390 cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]); 391 cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]); 392 cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]); 393 cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]); 394 } 395 396 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) 397 { 398 struct omap_drm_private *priv = crtc->dev->dev_private; 399 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 400 struct omap_overlay_manager_info info; 401 402 memset(&info, 0, sizeof(info)); 403 404 info.default_color = 0x000000; 405 info.trans_enabled = false; 406 info.partial_alpha_enabled = false; 407 408 if (crtc->state->ctm) { 409 struct drm_color_ctm *ctm = crtc->state->ctm->data; 410 411 info.cpr_enable = true; 412 omap_crtc_cpr_coefs_from_ctm(ctm, &info.cpr_coefs); 413 } else { 414 info.cpr_enable = false; 415 } 416 417 dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info); 418 } 419 420 /* ----------------------------------------------------------------------------- 421 * CRTC Functions 422 */ 423 424 static void omap_crtc_destroy(struct drm_crtc *crtc) 425 { 426 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 427 428 DBG("%s", omap_crtc->name); 429 430 drm_crtc_cleanup(crtc); 431 432 kfree(omap_crtc); 433 } 434 435 static void omap_crtc_arm_event(struct drm_crtc *crtc) 436 { 437 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 438 439 WARN_ON(omap_crtc->pending); 440 omap_crtc->pending = true; 441 442 if (crtc->state->event) { 443 omap_crtc->event = crtc->state->event; 444 crtc->state->event = NULL; 445 } 446 } 447 448 static void omap_crtc_atomic_enable(struct drm_crtc *crtc, 449 struct drm_atomic_state *state) 450 { 451 struct omap_drm_private *priv = crtc->dev->dev_private; 452 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 453 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); 454 int ret; 455 456 DBG("%s", omap_crtc->name); 457 458 dispc_runtime_get(priv->dispc); 459 460 /* manual updated display will not trigger vsync irq */ 461 if (omap_state->manually_updated) 462 return; 463 464 drm_crtc_vblank_on(crtc); 465 466 ret = drm_crtc_vblank_get(crtc); 467 WARN_ON(ret != 0); 468 469 spin_lock_irq(&crtc->dev->event_lock); 470 omap_crtc_arm_event(crtc); 471 spin_unlock_irq(&crtc->dev->event_lock); 472 } 473 474 static void omap_crtc_atomic_disable(struct drm_crtc *crtc, 475 struct drm_atomic_state *state) 476 { 477 struct omap_drm_private *priv = crtc->dev->dev_private; 478 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 479 struct drm_device *dev = crtc->dev; 480 481 DBG("%s", omap_crtc->name); 482 483 spin_lock_irq(&crtc->dev->event_lock); 484 if (crtc->state->event) { 485 drm_crtc_send_vblank_event(crtc, crtc->state->event); 486 crtc->state->event = NULL; 487 } 488 spin_unlock_irq(&crtc->dev->event_lock); 489 490 cancel_delayed_work(&omap_crtc->update_work); 491 492 if (!omap_crtc_wait_pending(crtc)) 493 dev_warn(dev->dev, "manual display update did not finish!"); 494 495 drm_crtc_vblank_off(crtc); 496 497 dispc_runtime_put(priv->dispc); 498 } 499 500 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, 501 const struct drm_display_mode *mode) 502 { 503 struct omap_drm_private *priv = crtc->dev->dev_private; 504 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 505 struct videomode vm = {0}; 506 int r; 507 508 drm_display_mode_to_videomode(mode, &vm); 509 510 /* 511 * DSI might not call this, since the supplied mode is not a 512 * valid DISPC mode. DSI will calculate and configure the 513 * proper DISPC mode later. 514 */ 515 if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) { 516 r = dispc_mgr_check_timings(priv->dispc, 517 omap_crtc->channel, 518 &vm); 519 if (r) 520 return r; 521 } 522 523 /* Check for bandwidth limit */ 524 if (priv->max_bandwidth) { 525 /* 526 * Estimation for the bandwidth need of a given mode with one 527 * full screen plane: 528 * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) 529 * ^^ Refresh rate ^^ 530 * 531 * The interlaced mode is taken into account by using the 532 * pixelclock in the calculation. 533 * 534 * The equation is rearranged for 64bit arithmetic. 535 */ 536 uint64_t bandwidth = mode->clock * 1000; 537 unsigned int bpp = 4; 538 539 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; 540 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); 541 542 /* 543 * Reject modes which would need more bandwidth if used with one 544 * full resolution plane (most common use case). 545 */ 546 if (priv->max_bandwidth < bandwidth) 547 return MODE_BAD; 548 } 549 550 return MODE_OK; 551 } 552 553 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) 554 { 555 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 556 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 557 558 DBG("%s: set mode: " DRM_MODE_FMT, 559 omap_crtc->name, DRM_MODE_ARG(mode)); 560 561 drm_display_mode_to_videomode(mode, &omap_crtc->vm); 562 } 563 564 static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc) 565 { 566 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 567 struct omap_dss_device *dssdev = omap_crtc->pipe->output; 568 569 if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->is_video_mode) 570 return false; 571 572 if (dssdev->dsi_ops->is_video_mode(dssdev)) 573 return false; 574 575 DBG("detected manually updated display!"); 576 return true; 577 } 578 579 static int omap_crtc_atomic_check(struct drm_crtc *crtc, 580 struct drm_atomic_state *state) 581 { 582 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 583 crtc); 584 struct drm_plane_state *pri_state; 585 586 if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) { 587 unsigned int length = crtc_state->degamma_lut->length / 588 sizeof(struct drm_color_lut); 589 590 if (length < 2) 591 return -EINVAL; 592 } 593 594 pri_state = drm_atomic_get_new_plane_state(state, 595 crtc->primary); 596 if (pri_state) { 597 struct omap_crtc_state *omap_crtc_state = 598 to_omap_crtc_state(crtc_state); 599 600 /* Mirror new values for zpos and rotation in omap_crtc_state */ 601 omap_crtc_state->zpos = pri_state->zpos; 602 omap_crtc_state->rotation = pri_state->rotation; 603 604 /* Check if this CRTC is for a manually updated display */ 605 omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc); 606 } 607 608 return 0; 609 } 610 611 static void omap_crtc_atomic_begin(struct drm_crtc *crtc, 612 struct drm_atomic_state *state) 613 { 614 } 615 616 static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 617 struct drm_atomic_state *state) 618 { 619 struct omap_drm_private *priv = crtc->dev->dev_private; 620 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 621 struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state); 622 int ret; 623 624 if (crtc->state->color_mgmt_changed) { 625 struct drm_color_lut *lut = NULL; 626 unsigned int length = 0; 627 628 if (crtc->state->degamma_lut) { 629 lut = (struct drm_color_lut *) 630 crtc->state->degamma_lut->data; 631 length = crtc->state->degamma_lut->length / 632 sizeof(*lut); 633 } 634 dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel, 635 lut, length); 636 } 637 638 omap_crtc_write_crtc_properties(crtc); 639 640 /* Only flush the CRTC if it is currently enabled. */ 641 if (!omap_crtc->enabled) 642 return; 643 644 DBG("%s: GO", omap_crtc->name); 645 646 if (omap_crtc_state->manually_updated) { 647 /* send new image for page flips and modeset changes */ 648 spin_lock_irq(&crtc->dev->event_lock); 649 omap_crtc_flush(crtc); 650 omap_crtc_arm_event(crtc); 651 spin_unlock_irq(&crtc->dev->event_lock); 652 return; 653 } 654 655 ret = drm_crtc_vblank_get(crtc); 656 WARN_ON(ret != 0); 657 658 spin_lock_irq(&crtc->dev->event_lock); 659 dispc_mgr_go(priv->dispc, omap_crtc->channel); 660 omap_crtc_arm_event(crtc); 661 spin_unlock_irq(&crtc->dev->event_lock); 662 } 663 664 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, 665 struct drm_crtc_state *state, 666 struct drm_property *property, 667 u64 val) 668 { 669 struct omap_drm_private *priv = crtc->dev->dev_private; 670 struct drm_plane_state *plane_state; 671 672 /* 673 * Delegate property set to the primary plane. Get the plane state and 674 * set the property directly, the shadow copy will be assigned in the 675 * omap_crtc_atomic_check callback. This way updates to plane state will 676 * always be mirrored in the crtc state correctly. 677 */ 678 plane_state = drm_atomic_get_plane_state(state->state, crtc->primary); 679 if (IS_ERR(plane_state)) 680 return PTR_ERR(plane_state); 681 682 if (property == crtc->primary->rotation_property) 683 plane_state->rotation = val; 684 else if (property == priv->zorder_prop) 685 plane_state->zpos = val; 686 else 687 return -EINVAL; 688 689 return 0; 690 } 691 692 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, 693 const struct drm_crtc_state *state, 694 struct drm_property *property, 695 u64 *val) 696 { 697 struct omap_drm_private *priv = crtc->dev->dev_private; 698 struct omap_crtc_state *omap_state = to_omap_crtc_state(state); 699 700 if (property == crtc->primary->rotation_property) 701 *val = omap_state->rotation; 702 else if (property == priv->zorder_prop) 703 *val = omap_state->zpos; 704 else 705 return -EINVAL; 706 707 return 0; 708 } 709 710 static void omap_crtc_reset(struct drm_crtc *crtc) 711 { 712 struct omap_crtc_state *state; 713 714 if (crtc->state) 715 __drm_atomic_helper_crtc_destroy_state(crtc->state); 716 717 kfree(crtc->state); 718 719 state = kzalloc(sizeof(*state), GFP_KERNEL); 720 if (state) 721 __drm_atomic_helper_crtc_reset(crtc, &state->base); 722 } 723 724 static struct drm_crtc_state * 725 omap_crtc_duplicate_state(struct drm_crtc *crtc) 726 { 727 struct omap_crtc_state *state, *current_state; 728 729 if (WARN_ON(!crtc->state)) 730 return NULL; 731 732 current_state = to_omap_crtc_state(crtc->state); 733 734 state = kmalloc(sizeof(*state), GFP_KERNEL); 735 if (!state) 736 return NULL; 737 738 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 739 740 state->zpos = current_state->zpos; 741 state->rotation = current_state->rotation; 742 state->manually_updated = current_state->manually_updated; 743 744 return &state->base; 745 } 746 747 static const struct drm_crtc_funcs omap_crtc_funcs = { 748 .reset = omap_crtc_reset, 749 .set_config = drm_atomic_helper_set_config, 750 .destroy = omap_crtc_destroy, 751 .page_flip = drm_atomic_helper_page_flip, 752 .atomic_duplicate_state = omap_crtc_duplicate_state, 753 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 754 .atomic_set_property = omap_crtc_atomic_set_property, 755 .atomic_get_property = omap_crtc_atomic_get_property, 756 .enable_vblank = omap_irq_enable_vblank, 757 .disable_vblank = omap_irq_disable_vblank, 758 }; 759 760 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { 761 .mode_set_nofb = omap_crtc_mode_set_nofb, 762 .atomic_check = omap_crtc_atomic_check, 763 .atomic_begin = omap_crtc_atomic_begin, 764 .atomic_flush = omap_crtc_atomic_flush, 765 .atomic_enable = omap_crtc_atomic_enable, 766 .atomic_disable = omap_crtc_atomic_disable, 767 .mode_valid = omap_crtc_mode_valid, 768 }; 769 770 /* ----------------------------------------------------------------------------- 771 * Init and Cleanup 772 */ 773 774 static const char *channel_names[] = { 775 [OMAP_DSS_CHANNEL_LCD] = "lcd", 776 [OMAP_DSS_CHANNEL_DIGIT] = "tv", 777 [OMAP_DSS_CHANNEL_LCD2] = "lcd2", 778 [OMAP_DSS_CHANNEL_LCD3] = "lcd3", 779 }; 780 781 /* initialize crtc */ 782 struct drm_crtc *omap_crtc_init(struct drm_device *dev, 783 struct omap_drm_pipeline *pipe, 784 struct drm_plane *plane) 785 { 786 struct omap_drm_private *priv = dev->dev_private; 787 struct drm_crtc *crtc = NULL; 788 struct omap_crtc *omap_crtc; 789 enum omap_channel channel; 790 int ret; 791 792 channel = pipe->output->dispc_channel; 793 794 DBG("%s", channel_names[channel]); 795 796 omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); 797 if (!omap_crtc) 798 return ERR_PTR(-ENOMEM); 799 800 crtc = &omap_crtc->base; 801 802 init_waitqueue_head(&omap_crtc->pending_wait); 803 804 omap_crtc->pipe = pipe; 805 omap_crtc->channel = channel; 806 omap_crtc->name = channel_names[channel]; 807 808 /* 809 * We want to refresh manually updated displays from dirty callback, 810 * which is called quite often (e.g. for each drawn line). This will 811 * be used to do the display update asynchronously to avoid blocking 812 * the rendering process and merges multiple dirty calls into one 813 * update if they arrive very fast. We also call this function for 814 * atomic display updates (e.g. for page flips), which means we do 815 * not need extra locking. Atomic updates should be synchronous, but 816 * need to wait for the framedone interrupt anyways. 817 */ 818 INIT_DELAYED_WORK(&omap_crtc->update_work, 819 omap_crtc_manual_display_update); 820 821 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, 822 &omap_crtc_funcs, NULL); 823 if (ret < 0) { 824 dev_err(dev->dev, "%s(): could not init crtc for: %s\n", 825 __func__, pipe->output->name); 826 kfree(omap_crtc); 827 return ERR_PTR(ret); 828 } 829 830 drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); 831 832 /* The dispc API adapts to what ever size, but the HW supports 833 * 256 element gamma table for LCDs and 1024 element table for 834 * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma 835 * tables so lets use that. Size of HW gamma table can be 836 * extracted with dispc_mgr_gamma_size(). If it returns 0 837 * gamma table is not supported. 838 */ 839 if (dispc_mgr_gamma_size(priv->dispc, channel)) { 840 unsigned int gamma_lut_size = 256; 841 842 drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0); 843 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); 844 } 845 846 omap_plane_install_properties(crtc->primary, &crtc->base); 847 848 return crtc; 849 } 850