1 /* 2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 * Author: Rob Clark <rob@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_crtc_helper.h> 22 #include <drm/drm_mode.h> 23 #include <drm/drm_plane_helper.h> 24 #include <linux/math64.h> 25 26 #include "omap_drv.h" 27 28 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) 29 30 struct omap_crtc_state { 31 /* Must be first. */ 32 struct drm_crtc_state base; 33 /* Shadow values for legacy userspace support. */ 34 unsigned int rotation; 35 unsigned int zpos; 36 }; 37 38 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) 39 40 struct omap_crtc { 41 struct drm_crtc base; 42 43 const char *name; 44 struct omap_drm_pipeline *pipe; 45 enum omap_channel channel; 46 47 struct videomode vm; 48 49 bool ignore_digit_sync_lost; 50 51 bool enabled; 52 bool pending; 53 wait_queue_head_t pending_wait; 54 struct drm_pending_vblank_event *event; 55 }; 56 57 /* ----------------------------------------------------------------------------- 58 * Helper Functions 59 */ 60 61 struct videomode *omap_crtc_timings(struct drm_crtc *crtc) 62 { 63 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 64 return &omap_crtc->vm; 65 } 66 67 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) 68 { 69 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 70 return omap_crtc->channel; 71 } 72 73 static bool omap_crtc_is_pending(struct drm_crtc *crtc) 74 { 75 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 76 unsigned long flags; 77 bool pending; 78 79 spin_lock_irqsave(&crtc->dev->event_lock, flags); 80 pending = omap_crtc->pending; 81 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 82 83 return pending; 84 } 85 86 int omap_crtc_wait_pending(struct drm_crtc *crtc) 87 { 88 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 89 90 /* 91 * Timeout is set to a "sufficiently" high value, which should cover 92 * a single frame refresh even on slower displays. 93 */ 94 return wait_event_timeout(omap_crtc->pending_wait, 95 !omap_crtc_is_pending(crtc), 96 msecs_to_jiffies(250)); 97 } 98 99 /* ----------------------------------------------------------------------------- 100 * DSS Manager Functions 101 */ 102 103 /* 104 * Manager-ops, callbacks from output when they need to configure 105 * the upstream part of the video pipe. 106 * 107 * Most of these we can ignore until we add support for command-mode 108 * panels.. for video-mode the crtc-helpers already do an adequate 109 * job of sequencing the setup of the video pipe in the proper order 110 */ 111 112 /* we can probably ignore these until we support command-mode panels: */ 113 static void omap_crtc_dss_start_update(struct omap_drm_private *priv, 114 enum omap_channel channel) 115 { 116 } 117 118 /* Called only from the encoder enable/disable and suspend/resume handlers. */ 119 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) 120 { 121 struct drm_device *dev = crtc->dev; 122 struct omap_drm_private *priv = dev->dev_private; 123 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 124 enum omap_channel channel = omap_crtc->channel; 125 struct omap_irq_wait *wait; 126 u32 framedone_irq, vsync_irq; 127 int ret; 128 129 if (WARN_ON(omap_crtc->enabled == enable)) 130 return; 131 132 if (omap_crtc->pipe->output->output_type == OMAP_DISPLAY_TYPE_HDMI) { 133 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); 134 omap_crtc->enabled = enable; 135 return; 136 } 137 138 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { 139 /* 140 * Digit output produces some sync lost interrupts during the 141 * first frame when enabling, so we need to ignore those. 142 */ 143 omap_crtc->ignore_digit_sync_lost = true; 144 } 145 146 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, 147 channel); 148 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); 149 150 if (enable) { 151 wait = omap_irq_wait_init(dev, vsync_irq, 1); 152 } else { 153 /* 154 * When we disable the digit output, we need to wait for 155 * FRAMEDONE to know that DISPC has finished with the output. 156 * 157 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in 158 * that case we need to use vsync interrupt, and wait for both 159 * even and odd frames. 160 */ 161 162 if (framedone_irq) 163 wait = omap_irq_wait_init(dev, framedone_irq, 1); 164 else 165 wait = omap_irq_wait_init(dev, vsync_irq, 2); 166 } 167 168 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); 169 omap_crtc->enabled = enable; 170 171 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); 172 if (ret) { 173 dev_err(dev->dev, "%s: timeout waiting for %s\n", 174 omap_crtc->name, enable ? "enable" : "disable"); 175 } 176 177 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { 178 omap_crtc->ignore_digit_sync_lost = false; 179 /* make sure the irq handler sees the value above */ 180 mb(); 181 } 182 } 183 184 185 static int omap_crtc_dss_enable(struct omap_drm_private *priv, 186 enum omap_channel channel) 187 { 188 struct drm_crtc *crtc = priv->channels[channel]->crtc; 189 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 190 191 priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, 192 &omap_crtc->vm); 193 omap_crtc_set_enabled(&omap_crtc->base, true); 194 195 return 0; 196 } 197 198 static void omap_crtc_dss_disable(struct omap_drm_private *priv, 199 enum omap_channel channel) 200 { 201 struct drm_crtc *crtc = priv->channels[channel]->crtc; 202 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 203 204 omap_crtc_set_enabled(&omap_crtc->base, false); 205 } 206 207 static void omap_crtc_dss_set_timings(struct omap_drm_private *priv, 208 enum omap_channel channel, 209 const struct videomode *vm) 210 { 211 struct drm_crtc *crtc = priv->channels[channel]->crtc; 212 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 213 214 DBG("%s", omap_crtc->name); 215 omap_crtc->vm = *vm; 216 } 217 218 static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv, 219 enum omap_channel channel, 220 const struct dss_lcd_mgr_config *config) 221 { 222 struct drm_crtc *crtc = priv->channels[channel]->crtc; 223 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 224 225 DBG("%s", omap_crtc->name); 226 priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, 227 config); 228 } 229 230 static int omap_crtc_dss_register_framedone( 231 struct omap_drm_private *priv, enum omap_channel channel, 232 void (*handler)(void *), void *data) 233 { 234 return 0; 235 } 236 237 static void omap_crtc_dss_unregister_framedone( 238 struct omap_drm_private *priv, enum omap_channel channel, 239 void (*handler)(void *), void *data) 240 { 241 } 242 243 static const struct dss_mgr_ops mgr_ops = { 244 .start_update = omap_crtc_dss_start_update, 245 .enable = omap_crtc_dss_enable, 246 .disable = omap_crtc_dss_disable, 247 .set_timings = omap_crtc_dss_set_timings, 248 .set_lcd_config = omap_crtc_dss_set_lcd_config, 249 .register_framedone_handler = omap_crtc_dss_register_framedone, 250 .unregister_framedone_handler = omap_crtc_dss_unregister_framedone, 251 }; 252 253 /* ----------------------------------------------------------------------------- 254 * Setup, Flush and Page Flip 255 */ 256 257 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus) 258 { 259 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 260 261 if (omap_crtc->ignore_digit_sync_lost) { 262 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; 263 if (!irqstatus) 264 return; 265 } 266 267 DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); 268 } 269 270 void omap_crtc_vblank_irq(struct drm_crtc *crtc) 271 { 272 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 273 struct drm_device *dev = omap_crtc->base.dev; 274 struct omap_drm_private *priv = dev->dev_private; 275 bool pending; 276 277 spin_lock(&crtc->dev->event_lock); 278 /* 279 * If the dispc is busy we're racing the flush operation. Try again on 280 * the next vblank interrupt. 281 */ 282 if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) { 283 spin_unlock(&crtc->dev->event_lock); 284 return; 285 } 286 287 /* Send the vblank event if one has been requested. */ 288 if (omap_crtc->event) { 289 drm_crtc_send_vblank_event(crtc, omap_crtc->event); 290 omap_crtc->event = NULL; 291 } 292 293 pending = omap_crtc->pending; 294 omap_crtc->pending = false; 295 spin_unlock(&crtc->dev->event_lock); 296 297 if (pending) 298 drm_crtc_vblank_put(crtc); 299 300 /* Wake up omap_atomic_complete. */ 301 wake_up(&omap_crtc->pending_wait); 302 303 DBG("%s: apply done", omap_crtc->name); 304 } 305 306 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) 307 { 308 struct omap_drm_private *priv = crtc->dev->dev_private; 309 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 310 struct omap_overlay_manager_info info; 311 312 memset(&info, 0, sizeof(info)); 313 314 info.default_color = 0x000000; 315 info.trans_enabled = false; 316 info.partial_alpha_enabled = false; 317 info.cpr_enable = false; 318 319 priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info); 320 } 321 322 /* ----------------------------------------------------------------------------- 323 * CRTC Functions 324 */ 325 326 static void omap_crtc_destroy(struct drm_crtc *crtc) 327 { 328 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 329 330 DBG("%s", omap_crtc->name); 331 332 drm_crtc_cleanup(crtc); 333 334 kfree(omap_crtc); 335 } 336 337 static void omap_crtc_arm_event(struct drm_crtc *crtc) 338 { 339 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 340 341 WARN_ON(omap_crtc->pending); 342 omap_crtc->pending = true; 343 344 if (crtc->state->event) { 345 omap_crtc->event = crtc->state->event; 346 crtc->state->event = NULL; 347 } 348 } 349 350 static void omap_crtc_atomic_enable(struct drm_crtc *crtc, 351 struct drm_crtc_state *old_state) 352 { 353 struct omap_drm_private *priv = crtc->dev->dev_private; 354 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 355 int ret; 356 357 DBG("%s", omap_crtc->name); 358 359 priv->dispc_ops->runtime_get(priv->dispc); 360 361 spin_lock_irq(&crtc->dev->event_lock); 362 drm_crtc_vblank_on(crtc); 363 ret = drm_crtc_vblank_get(crtc); 364 WARN_ON(ret != 0); 365 366 omap_crtc_arm_event(crtc); 367 spin_unlock_irq(&crtc->dev->event_lock); 368 } 369 370 static void omap_crtc_atomic_disable(struct drm_crtc *crtc, 371 struct drm_crtc_state *old_state) 372 { 373 struct omap_drm_private *priv = crtc->dev->dev_private; 374 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 375 376 DBG("%s", omap_crtc->name); 377 378 spin_lock_irq(&crtc->dev->event_lock); 379 if (crtc->state->event) { 380 drm_crtc_send_vblank_event(crtc, crtc->state->event); 381 crtc->state->event = NULL; 382 } 383 spin_unlock_irq(&crtc->dev->event_lock); 384 385 drm_crtc_vblank_off(crtc); 386 387 priv->dispc_ops->runtime_put(priv->dispc); 388 } 389 390 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, 391 const struct drm_display_mode *mode) 392 { 393 struct omap_drm_private *priv = crtc->dev->dev_private; 394 395 /* Check for bandwidth limit */ 396 if (priv->max_bandwidth) { 397 /* 398 * Estimation for the bandwidth need of a given mode with one 399 * full screen plane: 400 * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) 401 * ^^ Refresh rate ^^ 402 * 403 * The interlaced mode is taken into account by using the 404 * pixelclock in the calculation. 405 * 406 * The equation is rearranged for 64bit arithmetic. 407 */ 408 uint64_t bandwidth = mode->clock * 1000; 409 unsigned int bpp = 4; 410 411 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; 412 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); 413 414 /* 415 * Reject modes which would need more bandwidth if used with one 416 * full resolution plane (most common use case). 417 */ 418 if (priv->max_bandwidth < bandwidth) 419 return MODE_BAD; 420 } 421 422 return MODE_OK; 423 } 424 425 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) 426 { 427 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 428 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 429 430 DBG("%s: set mode: " DRM_MODE_FMT, 431 omap_crtc->name, DRM_MODE_ARG(mode)); 432 433 drm_display_mode_to_videomode(mode, &omap_crtc->vm); 434 } 435 436 static int omap_crtc_atomic_check(struct drm_crtc *crtc, 437 struct drm_crtc_state *state) 438 { 439 struct drm_plane_state *pri_state; 440 441 if (state->color_mgmt_changed && state->gamma_lut) { 442 unsigned int length = state->gamma_lut->length / 443 sizeof(struct drm_color_lut); 444 445 if (length < 2) 446 return -EINVAL; 447 } 448 449 pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary); 450 if (pri_state) { 451 struct omap_crtc_state *omap_crtc_state = 452 to_omap_crtc_state(state); 453 454 /* Mirror new values for zpos and rotation in omap_crtc_state */ 455 omap_crtc_state->zpos = pri_state->zpos; 456 omap_crtc_state->rotation = pri_state->rotation; 457 } 458 459 return 0; 460 } 461 462 static void omap_crtc_atomic_begin(struct drm_crtc *crtc, 463 struct drm_crtc_state *old_crtc_state) 464 { 465 } 466 467 static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 468 struct drm_crtc_state *old_crtc_state) 469 { 470 struct omap_drm_private *priv = crtc->dev->dev_private; 471 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 472 int ret; 473 474 if (crtc->state->color_mgmt_changed) { 475 struct drm_color_lut *lut = NULL; 476 unsigned int length = 0; 477 478 if (crtc->state->gamma_lut) { 479 lut = (struct drm_color_lut *) 480 crtc->state->gamma_lut->data; 481 length = crtc->state->gamma_lut->length / 482 sizeof(*lut); 483 } 484 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel, 485 lut, length); 486 } 487 488 omap_crtc_write_crtc_properties(crtc); 489 490 /* Only flush the CRTC if it is currently enabled. */ 491 if (!omap_crtc->enabled) 492 return; 493 494 DBG("%s: GO", omap_crtc->name); 495 496 ret = drm_crtc_vblank_get(crtc); 497 WARN_ON(ret != 0); 498 499 spin_lock_irq(&crtc->dev->event_lock); 500 priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel); 501 omap_crtc_arm_event(crtc); 502 spin_unlock_irq(&crtc->dev->event_lock); 503 } 504 505 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, 506 struct drm_crtc_state *state, 507 struct drm_property *property, 508 u64 val) 509 { 510 struct omap_drm_private *priv = crtc->dev->dev_private; 511 struct drm_plane_state *plane_state; 512 513 /* 514 * Delegate property set to the primary plane. Get the plane state and 515 * set the property directly, the shadow copy will be assigned in the 516 * omap_crtc_atomic_check callback. This way updates to plane state will 517 * always be mirrored in the crtc state correctly. 518 */ 519 plane_state = drm_atomic_get_plane_state(state->state, crtc->primary); 520 if (IS_ERR(plane_state)) 521 return PTR_ERR(plane_state); 522 523 if (property == crtc->primary->rotation_property) 524 plane_state->rotation = val; 525 else if (property == priv->zorder_prop) 526 plane_state->zpos = val; 527 else 528 return -EINVAL; 529 530 return 0; 531 } 532 533 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, 534 const struct drm_crtc_state *state, 535 struct drm_property *property, 536 u64 *val) 537 { 538 struct omap_drm_private *priv = crtc->dev->dev_private; 539 struct omap_crtc_state *omap_state = to_omap_crtc_state(state); 540 541 if (property == crtc->primary->rotation_property) 542 *val = omap_state->rotation; 543 else if (property == priv->zorder_prop) 544 *val = omap_state->zpos; 545 else 546 return -EINVAL; 547 548 return 0; 549 } 550 551 static void omap_crtc_reset(struct drm_crtc *crtc) 552 { 553 if (crtc->state) 554 __drm_atomic_helper_crtc_destroy_state(crtc->state); 555 556 kfree(crtc->state); 557 crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL); 558 559 if (crtc->state) 560 crtc->state->crtc = crtc; 561 } 562 563 static struct drm_crtc_state * 564 omap_crtc_duplicate_state(struct drm_crtc *crtc) 565 { 566 struct omap_crtc_state *state, *current_state; 567 568 if (WARN_ON(!crtc->state)) 569 return NULL; 570 571 current_state = to_omap_crtc_state(crtc->state); 572 573 state = kmalloc(sizeof(*state), GFP_KERNEL); 574 if (!state) 575 return NULL; 576 577 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 578 579 state->zpos = current_state->zpos; 580 state->rotation = current_state->rotation; 581 582 return &state->base; 583 } 584 585 static const struct drm_crtc_funcs omap_crtc_funcs = { 586 .reset = omap_crtc_reset, 587 .set_config = drm_atomic_helper_set_config, 588 .destroy = omap_crtc_destroy, 589 .page_flip = drm_atomic_helper_page_flip, 590 .gamma_set = drm_atomic_helper_legacy_gamma_set, 591 .atomic_duplicate_state = omap_crtc_duplicate_state, 592 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 593 .atomic_set_property = omap_crtc_atomic_set_property, 594 .atomic_get_property = omap_crtc_atomic_get_property, 595 .enable_vblank = omap_irq_enable_vblank, 596 .disable_vblank = omap_irq_disable_vblank, 597 }; 598 599 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { 600 .mode_set_nofb = omap_crtc_mode_set_nofb, 601 .atomic_check = omap_crtc_atomic_check, 602 .atomic_begin = omap_crtc_atomic_begin, 603 .atomic_flush = omap_crtc_atomic_flush, 604 .atomic_enable = omap_crtc_atomic_enable, 605 .atomic_disable = omap_crtc_atomic_disable, 606 .mode_valid = omap_crtc_mode_valid, 607 }; 608 609 /* ----------------------------------------------------------------------------- 610 * Init and Cleanup 611 */ 612 613 static const char *channel_names[] = { 614 [OMAP_DSS_CHANNEL_LCD] = "lcd", 615 [OMAP_DSS_CHANNEL_DIGIT] = "tv", 616 [OMAP_DSS_CHANNEL_LCD2] = "lcd2", 617 [OMAP_DSS_CHANNEL_LCD3] = "lcd3", 618 }; 619 620 void omap_crtc_pre_init(struct omap_drm_private *priv) 621 { 622 dss_install_mgr_ops(priv->dss, &mgr_ops, priv); 623 } 624 625 void omap_crtc_pre_uninit(struct omap_drm_private *priv) 626 { 627 dss_uninstall_mgr_ops(priv->dss); 628 } 629 630 /* initialize crtc */ 631 struct drm_crtc *omap_crtc_init(struct drm_device *dev, 632 struct omap_drm_pipeline *pipe, 633 struct drm_plane *plane) 634 { 635 struct omap_drm_private *priv = dev->dev_private; 636 struct drm_crtc *crtc = NULL; 637 struct omap_crtc *omap_crtc; 638 enum omap_channel channel; 639 int ret; 640 641 channel = pipe->output->dispc_channel; 642 643 DBG("%s", channel_names[channel]); 644 645 omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); 646 if (!omap_crtc) 647 return ERR_PTR(-ENOMEM); 648 649 crtc = &omap_crtc->base; 650 651 init_waitqueue_head(&omap_crtc->pending_wait); 652 653 omap_crtc->pipe = pipe; 654 omap_crtc->channel = channel; 655 omap_crtc->name = channel_names[channel]; 656 657 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, 658 &omap_crtc_funcs, NULL); 659 if (ret < 0) { 660 dev_err(dev->dev, "%s(): could not init crtc for: %s\n", 661 __func__, pipe->display->name); 662 kfree(omap_crtc); 663 return ERR_PTR(ret); 664 } 665 666 drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); 667 668 /* The dispc API adapts to what ever size, but the HW supports 669 * 256 element gamma table for LCDs and 1024 element table for 670 * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma 671 * tables so lets use that. Size of HW gamma table can be 672 * extracted with dispc_mgr_gamma_size(). If it returns 0 673 * gamma table is not supprted. 674 */ 675 if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) { 676 unsigned int gamma_lut_size = 256; 677 678 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size); 679 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); 680 } 681 682 omap_plane_install_properties(crtc->primary, &crtc->base); 683 684 return crtc; 685 } 686