1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/platform_device.h> 20 #include <linux/sched.h> 21 22 #include "omapdss.h" 23 #include "dss.h" 24 25 struct dss_video_pll { 26 struct dss_pll pll; 27 28 struct device *dev; 29 30 void __iomem *clkctrl_base; 31 }; 32 33 #define REG_MOD(reg, val, start, end) \ 34 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) 35 36 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) 37 { 38 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ 39 } 40 41 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) 42 { 43 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ 44 } 45 46 static void dss_dpll_power_enable(struct dss_video_pll *vpll) 47 { 48 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ 49 50 /* 51 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, 52 * so we have to use fixed delay here. 53 */ 54 msleep(1); 55 } 56 57 static void dss_dpll_power_disable(struct dss_video_pll *vpll) 58 { 59 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ 60 } 61 62 static int dss_video_pll_enable(struct dss_pll *pll) 63 { 64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); 65 int r; 66 67 r = dss_runtime_get(pll->dss); 68 if (r) 69 return r; 70 71 dss_ctrl_pll_enable(pll, true); 72 73 dss_dpll_enable_scp_clk(vpll); 74 75 r = dss_pll_wait_reset_done(pll); 76 if (r) 77 goto err_reset; 78 79 dss_dpll_power_enable(vpll); 80 81 return 0; 82 83 err_reset: 84 dss_dpll_disable_scp_clk(vpll); 85 dss_ctrl_pll_enable(pll, false); 86 dss_runtime_put(pll->dss); 87 88 return r; 89 } 90 91 static void dss_video_pll_disable(struct dss_pll *pll) 92 { 93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); 94 95 dss_dpll_power_disable(vpll); 96 97 dss_dpll_disable_scp_clk(vpll); 98 99 dss_ctrl_pll_enable(pll, false); 100 101 dss_runtime_put(pll->dss); 102 } 103 104 static const struct dss_pll_ops dss_pll_ops = { 105 .enable = dss_video_pll_enable, 106 .disable = dss_video_pll_disable, 107 .set_config = dss_pll_write_config_type_a, 108 }; 109 110 static const struct dss_pll_hw dss_dra7_video_pll_hw = { 111 .type = DSS_PLL_TYPE_A, 112 113 .n_max = (1 << 8) - 1, 114 .m_max = (1 << 12) - 1, 115 .mX_max = (1 << 5) - 1, 116 .fint_min = 500000, 117 .fint_max = 2500000, 118 .clkdco_max = 1800000000, 119 120 .n_msb = 8, 121 .n_lsb = 1, 122 .m_msb = 20, 123 .m_lsb = 9, 124 125 .mX_msb[0] = 25, 126 .mX_lsb[0] = 21, 127 .mX_msb[1] = 30, 128 .mX_lsb[1] = 26, 129 .mX_msb[2] = 4, 130 .mX_lsb[2] = 0, 131 .mX_msb[3] = 9, 132 .mX_lsb[3] = 5, 133 134 .has_refsel = true, 135 136 .errata_i886 = true, 137 }; 138 139 struct dss_pll *dss_video_pll_init(struct dss_device *dss, 140 struct platform_device *pdev, int id, 141 struct regulator *regulator) 142 { 143 const char * const reg_name[] = { "pll1", "pll2" }; 144 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" }; 145 const char * const clkin_name[] = { "video1_clk", "video2_clk" }; 146 147 struct resource *res; 148 struct dss_video_pll *vpll; 149 void __iomem *pll_base, *clkctrl_base; 150 struct clk *clk; 151 struct dss_pll *pll; 152 int r; 153 154 /* PLL CONTROL */ 155 156 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]); 157 pll_base = devm_ioremap_resource(&pdev->dev, res); 158 if (IS_ERR(pll_base)) 159 return ERR_CAST(pll_base); 160 161 /* CLOCK CONTROL */ 162 163 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 164 clkctrl_name[id]); 165 clkctrl_base = devm_ioremap_resource(&pdev->dev, res); 166 if (IS_ERR(clkctrl_base)) 167 return ERR_CAST(clkctrl_base); 168 169 /* CLKIN */ 170 171 clk = devm_clk_get(&pdev->dev, clkin_name[id]); 172 if (IS_ERR(clk)) { 173 DSSERR("can't get video pll clkin\n"); 174 return ERR_CAST(clk); 175 } 176 177 vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL); 178 if (!vpll) 179 return ERR_PTR(-ENOMEM); 180 181 vpll->dev = &pdev->dev; 182 vpll->clkctrl_base = clkctrl_base; 183 184 pll = &vpll->pll; 185 186 pll->name = id == 0 ? "video0" : "video1"; 187 pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2; 188 pll->clkin = clk; 189 pll->regulator = regulator; 190 pll->base = pll_base; 191 pll->hw = &dss_dra7_video_pll_hw; 192 pll->ops = &dss_pll_ops; 193 194 r = dss_pll_register(dss, pll); 195 if (r) 196 return ERR_PTR(r); 197 198 return pll; 199 } 200 201 void dss_video_pll_uninit(struct dss_pll *pll) 202 { 203 dss_pll_unregister(pll); 204 } 205