1 /* 2 * linux/drivers/video/omap2/dss/venc.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * VENC settings from TI's DSS driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #define DSS_SUBSYS_NAME "VENC" 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/io.h> 29 #include <linux/mutex.h> 30 #include <linux/completion.h> 31 #include <linux/delay.h> 32 #include <linux/string.h> 33 #include <linux/seq_file.h> 34 #include <linux/platform_device.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/of.h> 38 #include <linux/of_graph.h> 39 #include <linux/component.h> 40 #include <linux/sys_soc.h> 41 42 #include "omapdss.h" 43 #include "dss.h" 44 45 /* Venc registers */ 46 #define VENC_REV_ID 0x00 47 #define VENC_STATUS 0x04 48 #define VENC_F_CONTROL 0x08 49 #define VENC_VIDOUT_CTRL 0x10 50 #define VENC_SYNC_CTRL 0x14 51 #define VENC_LLEN 0x1C 52 #define VENC_FLENS 0x20 53 #define VENC_HFLTR_CTRL 0x24 54 #define VENC_CC_CARR_WSS_CARR 0x28 55 #define VENC_C_PHASE 0x2C 56 #define VENC_GAIN_U 0x30 57 #define VENC_GAIN_V 0x34 58 #define VENC_GAIN_Y 0x38 59 #define VENC_BLACK_LEVEL 0x3C 60 #define VENC_BLANK_LEVEL 0x40 61 #define VENC_X_COLOR 0x44 62 #define VENC_M_CONTROL 0x48 63 #define VENC_BSTAMP_WSS_DATA 0x4C 64 #define VENC_S_CARR 0x50 65 #define VENC_LINE21 0x54 66 #define VENC_LN_SEL 0x58 67 #define VENC_L21__WC_CTL 0x5C 68 #define VENC_HTRIGGER_VTRIGGER 0x60 69 #define VENC_SAVID__EAVID 0x64 70 #define VENC_FLEN__FAL 0x68 71 #define VENC_LAL__PHASE_RESET 0x6C 72 #define VENC_HS_INT_START_STOP_X 0x70 73 #define VENC_HS_EXT_START_STOP_X 0x74 74 #define VENC_VS_INT_START_X 0x78 75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 78 #define VENC_VS_EXT_STOP_Y 0x88 79 #define VENC_AVID_START_STOP_X 0x90 80 #define VENC_AVID_START_STOP_Y 0x94 81 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 84 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 85 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 86 #define VENC_GEN_CTRL 0xB8 87 #define VENC_OUTPUT_CONTROL 0xC4 88 #define VENC_OUTPUT_TEST 0xC8 89 #define VENC_DAC_B__DAC_C 0xC8 90 91 struct venc_config { 92 u32 f_control; 93 u32 vidout_ctrl; 94 u32 sync_ctrl; 95 u32 llen; 96 u32 flens; 97 u32 hfltr_ctrl; 98 u32 cc_carr_wss_carr; 99 u32 c_phase; 100 u32 gain_u; 101 u32 gain_v; 102 u32 gain_y; 103 u32 black_level; 104 u32 blank_level; 105 u32 x_color; 106 u32 m_control; 107 u32 bstamp_wss_data; 108 u32 s_carr; 109 u32 line21; 110 u32 ln_sel; 111 u32 l21__wc_ctl; 112 u32 htrigger_vtrigger; 113 u32 savid__eavid; 114 u32 flen__fal; 115 u32 lal__phase_reset; 116 u32 hs_int_start_stop_x; 117 u32 hs_ext_start_stop_x; 118 u32 vs_int_start_x; 119 u32 vs_int_stop_x__vs_int_start_y; 120 u32 vs_int_stop_y__vs_ext_start_x; 121 u32 vs_ext_stop_x__vs_ext_start_y; 122 u32 vs_ext_stop_y; 123 u32 avid_start_stop_x; 124 u32 avid_start_stop_y; 125 u32 fid_int_start_x__fid_int_start_y; 126 u32 fid_int_offset_y__fid_ext_start_x; 127 u32 fid_ext_start_y__fid_ext_offset_y; 128 u32 tvdetgp_int_start_stop_x; 129 u32 tvdetgp_int_start_stop_y; 130 u32 gen_ctrl; 131 }; 132 133 /* from TRM */ 134 static const struct venc_config venc_config_pal_trm = { 135 .f_control = 0, 136 .vidout_ctrl = 1, 137 .sync_ctrl = 0x40, 138 .llen = 0x35F, /* 863 */ 139 .flens = 0x270, /* 624 */ 140 .hfltr_ctrl = 0, 141 .cc_carr_wss_carr = 0x2F7225ED, 142 .c_phase = 0, 143 .gain_u = 0x111, 144 .gain_v = 0x181, 145 .gain_y = 0x140, 146 .black_level = 0x3B, 147 .blank_level = 0x3B, 148 .x_color = 0x7, 149 .m_control = 0x2, 150 .bstamp_wss_data = 0x3F, 151 .s_carr = 0x2A098ACB, 152 .line21 = 0, 153 .ln_sel = 0x01290015, 154 .l21__wc_ctl = 0x0000F603, 155 .htrigger_vtrigger = 0, 156 157 .savid__eavid = 0x06A70108, 158 .flen__fal = 0x00180270, 159 .lal__phase_reset = 0x00040135, 160 .hs_int_start_stop_x = 0x00880358, 161 .hs_ext_start_stop_x = 0x000F035F, 162 .vs_int_start_x = 0x01A70000, 163 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 166 .vs_ext_stop_y = 0x00000025, 167 .avid_start_stop_x = 0x03530083, 168 .avid_start_stop_y = 0x026C002E, 169 .fid_int_start_x__fid_int_start_y = 0x0001008A, 170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 172 173 .tvdetgp_int_start_stop_x = 0x00140001, 174 .tvdetgp_int_start_stop_y = 0x00010001, 175 .gen_ctrl = 0x00FF0000, 176 }; 177 178 /* from TRM */ 179 static const struct venc_config venc_config_ntsc_trm = { 180 .f_control = 0, 181 .vidout_ctrl = 1, 182 .sync_ctrl = 0x8040, 183 .llen = 0x359, 184 .flens = 0x20C, 185 .hfltr_ctrl = 0, 186 .cc_carr_wss_carr = 0x043F2631, 187 .c_phase = 0, 188 .gain_u = 0x102, 189 .gain_v = 0x16C, 190 .gain_y = 0x12F, 191 .black_level = 0x43, 192 .blank_level = 0x38, 193 .x_color = 0x7, 194 .m_control = 0x1, 195 .bstamp_wss_data = 0x38, 196 .s_carr = 0x21F07C1F, 197 .line21 = 0, 198 .ln_sel = 0x01310011, 199 .l21__wc_ctl = 0x0000F003, 200 .htrigger_vtrigger = 0, 201 202 .savid__eavid = 0x069300F4, 203 .flen__fal = 0x0016020C, 204 .lal__phase_reset = 0x00060107, 205 .hs_int_start_stop_x = 0x008E0350, 206 .hs_ext_start_stop_x = 0x000F0359, 207 .vs_int_start_x = 0x01A00000, 208 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 211 .vs_ext_stop_y = 0x00000006, 212 .avid_start_stop_x = 0x03480078, 213 .avid_start_stop_y = 0x02060024, 214 .fid_int_start_x__fid_int_start_y = 0x0001008A, 215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 217 218 .tvdetgp_int_start_stop_x = 0x00140001, 219 .tvdetgp_int_start_stop_y = 0x00010001, 220 .gen_ctrl = 0x00F90000, 221 }; 222 223 static const struct venc_config venc_config_pal_bdghi = { 224 .f_control = 0, 225 .vidout_ctrl = 0, 226 .sync_ctrl = 0, 227 .hfltr_ctrl = 0, 228 .x_color = 0, 229 .line21 = 0, 230 .ln_sel = 21, 231 .htrigger_vtrigger = 0, 232 .tvdetgp_int_start_stop_x = 0x00140001, 233 .tvdetgp_int_start_stop_y = 0x00010001, 234 .gen_ctrl = 0x00FB0000, 235 236 .llen = 864-1, 237 .flens = 625-1, 238 .cc_carr_wss_carr = 0x2F7625ED, 239 .c_phase = 0xDF, 240 .gain_u = 0x111, 241 .gain_v = 0x181, 242 .gain_y = 0x140, 243 .black_level = 0x3e, 244 .blank_level = 0x3e, 245 .m_control = 0<<2 | 1<<1, 246 .bstamp_wss_data = 0x42, 247 .s_carr = 0x2a098acb, 248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, 249 .savid__eavid = 0x06A70108, 250 .flen__fal = 23<<16 | 624<<0, 251 .lal__phase_reset = 2<<17 | 310<<0, 252 .hs_int_start_stop_x = 0x00920358, 253 .hs_ext_start_stop_x = 0x000F035F, 254 .vs_int_start_x = 0x1a7<<16, 255 .vs_int_stop_x__vs_int_start_y = 0x000601A7, 256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, 257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af, 258 .vs_ext_stop_y = 0x05, 259 .avid_start_stop_x = 0x03530082, 260 .avid_start_stop_y = 0x0270002E, 261 .fid_int_start_x__fid_int_start_y = 0x0005008A, 262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 264 }; 265 266 enum venc_videomode { 267 VENC_MODE_UNKNOWN, 268 VENC_MODE_PAL, 269 VENC_MODE_NTSC, 270 }; 271 272 static const struct videomode omap_dss_pal_vm = { 273 .hactive = 720, 274 .vactive = 574, 275 .pixelclock = 13500000, 276 .hsync_len = 64, 277 .hfront_porch = 12, 278 .hback_porch = 68, 279 .vsync_len = 5, 280 .vfront_porch = 5, 281 .vback_porch = 41, 282 283 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 284 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 285 DISPLAY_FLAGS_PIXDATA_POSEDGE | 286 DISPLAY_FLAGS_SYNC_NEGEDGE, 287 }; 288 289 static const struct videomode omap_dss_ntsc_vm = { 290 .hactive = 720, 291 .vactive = 482, 292 .pixelclock = 13500000, 293 .hsync_len = 64, 294 .hfront_porch = 16, 295 .hback_porch = 58, 296 .vsync_len = 6, 297 .vfront_porch = 6, 298 .vback_porch = 31, 299 300 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 301 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 302 DISPLAY_FLAGS_PIXDATA_POSEDGE | 303 DISPLAY_FLAGS_SYNC_NEGEDGE, 304 }; 305 306 static enum venc_videomode venc_get_videomode(const struct videomode *vm) 307 { 308 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) 309 return VENC_MODE_UNKNOWN; 310 311 if (vm->pixelclock == omap_dss_pal_vm.pixelclock && 312 vm->hactive == omap_dss_pal_vm.hactive && 313 vm->vactive == omap_dss_pal_vm.vactive) 314 return VENC_MODE_PAL; 315 316 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && 317 vm->hactive == omap_dss_ntsc_vm.hactive && 318 vm->vactive == omap_dss_ntsc_vm.vactive) 319 return VENC_MODE_NTSC; 320 321 return VENC_MODE_UNKNOWN; 322 } 323 324 static struct { 325 struct platform_device *pdev; 326 void __iomem *base; 327 struct mutex venc_lock; 328 u32 wss_data; 329 struct regulator *vdda_dac_reg; 330 331 struct clk *tv_dac_clk; 332 333 struct videomode vm; 334 enum omap_dss_venc_type type; 335 bool invert_polarity; 336 bool requires_tv_dac_clk; 337 338 struct omap_dss_device output; 339 } venc; 340 341 static inline void venc_write_reg(int idx, u32 val) 342 { 343 __raw_writel(val, venc.base + idx); 344 } 345 346 static inline u32 venc_read_reg(int idx) 347 { 348 u32 l = __raw_readl(venc.base + idx); 349 return l; 350 } 351 352 static void venc_write_config(const struct venc_config *config) 353 { 354 DSSDBG("write venc conf\n"); 355 356 venc_write_reg(VENC_LLEN, config->llen); 357 venc_write_reg(VENC_FLENS, config->flens); 358 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 359 venc_write_reg(VENC_C_PHASE, config->c_phase); 360 venc_write_reg(VENC_GAIN_U, config->gain_u); 361 venc_write_reg(VENC_GAIN_V, config->gain_v); 362 venc_write_reg(VENC_GAIN_Y, config->gain_y); 363 venc_write_reg(VENC_BLACK_LEVEL, config->black_level); 364 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); 365 venc_write_reg(VENC_M_CONTROL, config->m_control); 366 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 367 venc.wss_data); 368 venc_write_reg(VENC_S_CARR, config->s_carr); 369 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); 370 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); 371 venc_write_reg(VENC_FLEN__FAL, config->flen__fal); 372 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); 373 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); 374 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); 375 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); 376 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, 377 config->vs_int_stop_x__vs_int_start_y); 378 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, 379 config->vs_int_stop_y__vs_ext_start_x); 380 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 381 config->vs_ext_stop_x__vs_ext_start_y); 382 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 383 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); 384 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 385 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, 386 config->fid_int_start_x__fid_int_start_y); 387 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 388 config->fid_int_offset_y__fid_ext_start_x); 389 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 390 config->fid_ext_start_y__fid_ext_offset_y); 391 392 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); 393 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); 394 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); 395 venc_write_reg(VENC_X_COLOR, config->x_color); 396 venc_write_reg(VENC_LINE21, config->line21); 397 venc_write_reg(VENC_LN_SEL, config->ln_sel); 398 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 399 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, 400 config->tvdetgp_int_start_stop_x); 401 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, 402 config->tvdetgp_int_start_stop_y); 403 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); 404 venc_write_reg(VENC_F_CONTROL, config->f_control); 405 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); 406 } 407 408 static void venc_reset(void) 409 { 410 int t = 1000; 411 412 venc_write_reg(VENC_F_CONTROL, 1<<8); 413 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { 414 if (--t == 0) { 415 DSSERR("Failed to reset venc\n"); 416 return; 417 } 418 } 419 420 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 421 /* the magical sleep that makes things work */ 422 /* XXX more info? What bug this circumvents? */ 423 msleep(20); 424 #endif 425 } 426 427 static int venc_runtime_get(void) 428 { 429 int r; 430 431 DSSDBG("venc_runtime_get\n"); 432 433 r = pm_runtime_get_sync(&venc.pdev->dev); 434 WARN_ON(r < 0); 435 return r < 0 ? r : 0; 436 } 437 438 static void venc_runtime_put(void) 439 { 440 int r; 441 442 DSSDBG("venc_runtime_put\n"); 443 444 r = pm_runtime_put_sync(&venc.pdev->dev); 445 WARN_ON(r < 0 && r != -ENOSYS); 446 } 447 448 static const struct venc_config *venc_timings_to_config(struct videomode *vm) 449 { 450 switch (venc_get_videomode(vm)) { 451 default: 452 WARN_ON_ONCE(1); 453 case VENC_MODE_PAL: 454 return &venc_config_pal_trm; 455 case VENC_MODE_NTSC: 456 return &venc_config_ntsc_trm; 457 } 458 } 459 460 static int venc_power_on(struct omap_dss_device *dssdev) 461 { 462 enum omap_channel channel = dssdev->dispc_channel; 463 u32 l; 464 int r; 465 466 r = venc_runtime_get(); 467 if (r) 468 goto err0; 469 470 venc_reset(); 471 venc_write_config(venc_timings_to_config(&venc.vm)); 472 473 dss_set_venc_output(venc.type); 474 dss_set_dac_pwrdn_bgz(1); 475 476 l = 0; 477 478 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) 479 l |= 1 << 1; 480 else /* S-Video */ 481 l |= (1 << 0) | (1 << 2); 482 483 if (venc.invert_polarity == false) 484 l |= 1 << 3; 485 486 venc_write_reg(VENC_OUTPUT_CONTROL, l); 487 488 dss_mgr_set_timings(channel, &venc.vm); 489 490 r = regulator_enable(venc.vdda_dac_reg); 491 if (r) 492 goto err1; 493 494 r = dss_mgr_enable(channel); 495 if (r) 496 goto err2; 497 498 return 0; 499 500 err2: 501 regulator_disable(venc.vdda_dac_reg); 502 err1: 503 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 504 dss_set_dac_pwrdn_bgz(0); 505 506 venc_runtime_put(); 507 err0: 508 return r; 509 } 510 511 static void venc_power_off(struct omap_dss_device *dssdev) 512 { 513 enum omap_channel channel = dssdev->dispc_channel; 514 515 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 516 dss_set_dac_pwrdn_bgz(0); 517 518 dss_mgr_disable(channel); 519 520 regulator_disable(venc.vdda_dac_reg); 521 522 venc_runtime_put(); 523 } 524 525 static int venc_display_enable(struct omap_dss_device *dssdev) 526 { 527 struct omap_dss_device *out = &venc.output; 528 int r; 529 530 DSSDBG("venc_display_enable\n"); 531 532 mutex_lock(&venc.venc_lock); 533 534 if (!out->dispc_channel_connected) { 535 DSSERR("Failed to enable display: no output/manager\n"); 536 r = -ENODEV; 537 goto err0; 538 } 539 540 r = venc_power_on(dssdev); 541 if (r) 542 goto err0; 543 544 venc.wss_data = 0; 545 546 mutex_unlock(&venc.venc_lock); 547 548 return 0; 549 err0: 550 mutex_unlock(&venc.venc_lock); 551 return r; 552 } 553 554 static void venc_display_disable(struct omap_dss_device *dssdev) 555 { 556 DSSDBG("venc_display_disable\n"); 557 558 mutex_lock(&venc.venc_lock); 559 560 venc_power_off(dssdev); 561 562 mutex_unlock(&venc.venc_lock); 563 } 564 565 static void venc_set_timings(struct omap_dss_device *dssdev, 566 struct videomode *vm) 567 { 568 struct videomode actual_vm; 569 570 DSSDBG("venc_set_timings\n"); 571 572 mutex_lock(&venc.venc_lock); 573 574 switch (venc_get_videomode(vm)) { 575 default: 576 WARN_ON_ONCE(1); 577 case VENC_MODE_PAL: 578 actual_vm = omap_dss_pal_vm; 579 break; 580 case VENC_MODE_NTSC: 581 actual_vm = omap_dss_ntsc_vm; 582 break; 583 } 584 585 /* Reset WSS data when the TV standard changes. */ 586 if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm))) 587 venc.wss_data = 0; 588 589 venc.vm = actual_vm; 590 591 dispc_set_tv_pclk(13500000); 592 593 mutex_unlock(&venc.venc_lock); 594 } 595 596 static int venc_check_timings(struct omap_dss_device *dssdev, 597 struct videomode *vm) 598 { 599 DSSDBG("venc_check_timings\n"); 600 601 switch (venc_get_videomode(vm)) { 602 case VENC_MODE_PAL: 603 case VENC_MODE_NTSC: 604 return 0; 605 default: 606 return -EINVAL; 607 } 608 } 609 610 static void venc_get_timings(struct omap_dss_device *dssdev, 611 struct videomode *vm) 612 { 613 mutex_lock(&venc.venc_lock); 614 615 *vm = venc.vm; 616 617 mutex_unlock(&venc.venc_lock); 618 } 619 620 static u32 venc_get_wss(struct omap_dss_device *dssdev) 621 { 622 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 623 return (venc.wss_data >> 8) ^ 0xfffff; 624 } 625 626 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) 627 { 628 const struct venc_config *config; 629 int r; 630 631 DSSDBG("venc_set_wss\n"); 632 633 mutex_lock(&venc.venc_lock); 634 635 config = venc_timings_to_config(&venc.vm); 636 637 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 638 venc.wss_data = (wss ^ 0xfffff) << 8; 639 640 r = venc_runtime_get(); 641 if (r) 642 goto err; 643 644 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 645 venc.wss_data); 646 647 venc_runtime_put(); 648 649 err: 650 mutex_unlock(&venc.venc_lock); 651 652 return r; 653 } 654 655 static int venc_init_regulator(void) 656 { 657 struct regulator *vdda_dac; 658 659 if (venc.vdda_dac_reg != NULL) 660 return 0; 661 662 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); 663 if (IS_ERR(vdda_dac)) { 664 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) 665 DSSERR("can't get VDDA_DAC regulator\n"); 666 return PTR_ERR(vdda_dac); 667 } 668 669 venc.vdda_dac_reg = vdda_dac; 670 671 return 0; 672 } 673 674 static void venc_dump_regs(struct seq_file *s) 675 { 676 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) 677 678 if (venc_runtime_get()) 679 return; 680 681 DUMPREG(VENC_F_CONTROL); 682 DUMPREG(VENC_VIDOUT_CTRL); 683 DUMPREG(VENC_SYNC_CTRL); 684 DUMPREG(VENC_LLEN); 685 DUMPREG(VENC_FLENS); 686 DUMPREG(VENC_HFLTR_CTRL); 687 DUMPREG(VENC_CC_CARR_WSS_CARR); 688 DUMPREG(VENC_C_PHASE); 689 DUMPREG(VENC_GAIN_U); 690 DUMPREG(VENC_GAIN_V); 691 DUMPREG(VENC_GAIN_Y); 692 DUMPREG(VENC_BLACK_LEVEL); 693 DUMPREG(VENC_BLANK_LEVEL); 694 DUMPREG(VENC_X_COLOR); 695 DUMPREG(VENC_M_CONTROL); 696 DUMPREG(VENC_BSTAMP_WSS_DATA); 697 DUMPREG(VENC_S_CARR); 698 DUMPREG(VENC_LINE21); 699 DUMPREG(VENC_LN_SEL); 700 DUMPREG(VENC_L21__WC_CTL); 701 DUMPREG(VENC_HTRIGGER_VTRIGGER); 702 DUMPREG(VENC_SAVID__EAVID); 703 DUMPREG(VENC_FLEN__FAL); 704 DUMPREG(VENC_LAL__PHASE_RESET); 705 DUMPREG(VENC_HS_INT_START_STOP_X); 706 DUMPREG(VENC_HS_EXT_START_STOP_X); 707 DUMPREG(VENC_VS_INT_START_X); 708 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); 709 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); 710 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 711 DUMPREG(VENC_VS_EXT_STOP_Y); 712 DUMPREG(VENC_AVID_START_STOP_X); 713 DUMPREG(VENC_AVID_START_STOP_Y); 714 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); 715 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 716 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 717 DUMPREG(VENC_TVDETGP_INT_START_STOP_X); 718 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); 719 DUMPREG(VENC_GEN_CTRL); 720 DUMPREG(VENC_OUTPUT_CONTROL); 721 DUMPREG(VENC_OUTPUT_TEST); 722 723 venc_runtime_put(); 724 725 #undef DUMPREG 726 } 727 728 static int venc_get_clocks(struct platform_device *pdev) 729 { 730 struct clk *clk; 731 732 if (venc.requires_tv_dac_clk) { 733 clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); 734 if (IS_ERR(clk)) { 735 DSSERR("can't get tv_dac_clk\n"); 736 return PTR_ERR(clk); 737 } 738 } else { 739 clk = NULL; 740 } 741 742 venc.tv_dac_clk = clk; 743 744 return 0; 745 } 746 747 static int venc_connect(struct omap_dss_device *dssdev, 748 struct omap_dss_device *dst) 749 { 750 enum omap_channel channel = dssdev->dispc_channel; 751 int r; 752 753 r = venc_init_regulator(); 754 if (r) 755 return r; 756 757 r = dss_mgr_connect(channel, dssdev); 758 if (r) 759 return r; 760 761 r = omapdss_output_set_device(dssdev, dst); 762 if (r) { 763 DSSERR("failed to connect output to new device: %s\n", 764 dst->name); 765 dss_mgr_disconnect(channel, dssdev); 766 return r; 767 } 768 769 return 0; 770 } 771 772 static void venc_disconnect(struct omap_dss_device *dssdev, 773 struct omap_dss_device *dst) 774 { 775 enum omap_channel channel = dssdev->dispc_channel; 776 777 WARN_ON(dst != dssdev->dst); 778 779 if (dst != dssdev->dst) 780 return; 781 782 omapdss_output_unset_device(dssdev); 783 784 dss_mgr_disconnect(channel, dssdev); 785 } 786 787 static const struct omapdss_atv_ops venc_ops = { 788 .connect = venc_connect, 789 .disconnect = venc_disconnect, 790 791 .enable = venc_display_enable, 792 .disable = venc_display_disable, 793 794 .check_timings = venc_check_timings, 795 .set_timings = venc_set_timings, 796 .get_timings = venc_get_timings, 797 798 .set_wss = venc_set_wss, 799 .get_wss = venc_get_wss, 800 }; 801 802 static void venc_init_output(struct platform_device *pdev) 803 { 804 struct omap_dss_device *out = &venc.output; 805 806 out->dev = &pdev->dev; 807 out->id = OMAP_DSS_OUTPUT_VENC; 808 out->output_type = OMAP_DISPLAY_TYPE_VENC; 809 out->name = "venc.0"; 810 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 811 out->ops.atv = &venc_ops; 812 out->owner = THIS_MODULE; 813 814 omapdss_register_output(out); 815 } 816 817 static void venc_uninit_output(struct platform_device *pdev) 818 { 819 struct omap_dss_device *out = &venc.output; 820 821 omapdss_unregister_output(out); 822 } 823 824 static int venc_probe_of(struct platform_device *pdev) 825 { 826 struct device_node *node = pdev->dev.of_node; 827 struct device_node *ep; 828 u32 channels; 829 int r; 830 831 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 832 if (!ep) 833 return 0; 834 835 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 836 837 r = of_property_read_u32(ep, "ti,channels", &channels); 838 if (r) { 839 dev_err(&pdev->dev, 840 "failed to read property 'ti,channels': %d\n", r); 841 goto err; 842 } 843 844 switch (channels) { 845 case 1: 846 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; 847 break; 848 case 2: 849 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; 850 break; 851 default: 852 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels); 853 r = -EINVAL; 854 goto err; 855 } 856 857 of_node_put(ep); 858 859 return 0; 860 err: 861 of_node_put(ep); 862 863 return 0; 864 } 865 866 /* VENC HW IP initialisation */ 867 static const struct soc_device_attribute venc_soc_devices[] = { 868 { .machine = "OMAP3[45]*" }, 869 { .machine = "AM35*" }, 870 { /* sentinel */ } 871 }; 872 873 static int venc_bind(struct device *dev, struct device *master, void *data) 874 { 875 struct platform_device *pdev = to_platform_device(dev); 876 u8 rev_id; 877 struct resource *venc_mem; 878 int r; 879 880 venc.pdev = pdev; 881 882 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 883 if (soc_device_match(venc_soc_devices)) 884 venc.requires_tv_dac_clk = true; 885 886 mutex_init(&venc.venc_lock); 887 888 venc.wss_data = 0; 889 890 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); 891 venc.base = devm_ioremap_resource(&pdev->dev, venc_mem); 892 if (IS_ERR(venc.base)) 893 return PTR_ERR(venc.base); 894 895 r = venc_get_clocks(pdev); 896 if (r) 897 return r; 898 899 pm_runtime_enable(&pdev->dev); 900 901 r = venc_runtime_get(); 902 if (r) 903 goto err_runtime_get; 904 905 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); 906 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); 907 908 venc_runtime_put(); 909 910 r = venc_probe_of(pdev); 911 if (r) { 912 DSSERR("Invalid DT data\n"); 913 goto err_probe_of; 914 } 915 916 dss_debugfs_create_file("venc", venc_dump_regs); 917 918 venc_init_output(pdev); 919 920 return 0; 921 922 err_probe_of: 923 err_runtime_get: 924 pm_runtime_disable(&pdev->dev); 925 return r; 926 } 927 928 static void venc_unbind(struct device *dev, struct device *master, void *data) 929 { 930 struct platform_device *pdev = to_platform_device(dev); 931 932 venc_uninit_output(pdev); 933 934 pm_runtime_disable(&pdev->dev); 935 } 936 937 static const struct component_ops venc_component_ops = { 938 .bind = venc_bind, 939 .unbind = venc_unbind, 940 }; 941 942 static int venc_probe(struct platform_device *pdev) 943 { 944 return component_add(&pdev->dev, &venc_component_ops); 945 } 946 947 static int venc_remove(struct platform_device *pdev) 948 { 949 component_del(&pdev->dev, &venc_component_ops); 950 return 0; 951 } 952 953 static int venc_runtime_suspend(struct device *dev) 954 { 955 if (venc.tv_dac_clk) 956 clk_disable_unprepare(venc.tv_dac_clk); 957 958 dispc_runtime_put(); 959 960 return 0; 961 } 962 963 static int venc_runtime_resume(struct device *dev) 964 { 965 int r; 966 967 r = dispc_runtime_get(); 968 if (r < 0) 969 return r; 970 971 if (venc.tv_dac_clk) 972 clk_prepare_enable(venc.tv_dac_clk); 973 974 return 0; 975 } 976 977 static const struct dev_pm_ops venc_pm_ops = { 978 .runtime_suspend = venc_runtime_suspend, 979 .runtime_resume = venc_runtime_resume, 980 }; 981 982 static const struct of_device_id venc_of_match[] = { 983 { .compatible = "ti,omap2-venc", }, 984 { .compatible = "ti,omap3-venc", }, 985 { .compatible = "ti,omap4-venc", }, 986 {}, 987 }; 988 989 static struct platform_driver omap_venchw_driver = { 990 .probe = venc_probe, 991 .remove = venc_remove, 992 .driver = { 993 .name = "omapdss_venc", 994 .pm = &venc_pm_ops, 995 .of_match_table = venc_of_match, 996 .suppress_bind_attrs = true, 997 }, 998 }; 999 1000 int __init venc_init_platform_driver(void) 1001 { 1002 return platform_driver_register(&omap_venchw_driver); 1003 } 1004 1005 void venc_uninit_platform_driver(void) 1006 { 1007 platform_driver_unregister(&omap_venchw_driver); 1008 } 1009