1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * VENC settings from TI's DSS driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "VENC" 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/mutex.h> 28 #include <linux/completion.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/seq_file.h> 32 #include <linux/platform_device.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/of.h> 36 #include <linux/of_graph.h> 37 #include <linux/component.h> 38 #include <linux/sys_soc.h> 39 40 #include "omapdss.h" 41 #include "dss.h" 42 43 /* Venc registers */ 44 #define VENC_REV_ID 0x00 45 #define VENC_STATUS 0x04 46 #define VENC_F_CONTROL 0x08 47 #define VENC_VIDOUT_CTRL 0x10 48 #define VENC_SYNC_CTRL 0x14 49 #define VENC_LLEN 0x1C 50 #define VENC_FLENS 0x20 51 #define VENC_HFLTR_CTRL 0x24 52 #define VENC_CC_CARR_WSS_CARR 0x28 53 #define VENC_C_PHASE 0x2C 54 #define VENC_GAIN_U 0x30 55 #define VENC_GAIN_V 0x34 56 #define VENC_GAIN_Y 0x38 57 #define VENC_BLACK_LEVEL 0x3C 58 #define VENC_BLANK_LEVEL 0x40 59 #define VENC_X_COLOR 0x44 60 #define VENC_M_CONTROL 0x48 61 #define VENC_BSTAMP_WSS_DATA 0x4C 62 #define VENC_S_CARR 0x50 63 #define VENC_LINE21 0x54 64 #define VENC_LN_SEL 0x58 65 #define VENC_L21__WC_CTL 0x5C 66 #define VENC_HTRIGGER_VTRIGGER 0x60 67 #define VENC_SAVID__EAVID 0x64 68 #define VENC_FLEN__FAL 0x68 69 #define VENC_LAL__PHASE_RESET 0x6C 70 #define VENC_HS_INT_START_STOP_X 0x70 71 #define VENC_HS_EXT_START_STOP_X 0x74 72 #define VENC_VS_INT_START_X 0x78 73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 76 #define VENC_VS_EXT_STOP_Y 0x88 77 #define VENC_AVID_START_STOP_X 0x90 78 #define VENC_AVID_START_STOP_Y 0x94 79 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 82 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 83 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 84 #define VENC_GEN_CTRL 0xB8 85 #define VENC_OUTPUT_CONTROL 0xC4 86 #define VENC_OUTPUT_TEST 0xC8 87 #define VENC_DAC_B__DAC_C 0xC8 88 89 struct venc_config { 90 u32 f_control; 91 u32 vidout_ctrl; 92 u32 sync_ctrl; 93 u32 llen; 94 u32 flens; 95 u32 hfltr_ctrl; 96 u32 cc_carr_wss_carr; 97 u32 c_phase; 98 u32 gain_u; 99 u32 gain_v; 100 u32 gain_y; 101 u32 black_level; 102 u32 blank_level; 103 u32 x_color; 104 u32 m_control; 105 u32 bstamp_wss_data; 106 u32 s_carr; 107 u32 line21; 108 u32 ln_sel; 109 u32 l21__wc_ctl; 110 u32 htrigger_vtrigger; 111 u32 savid__eavid; 112 u32 flen__fal; 113 u32 lal__phase_reset; 114 u32 hs_int_start_stop_x; 115 u32 hs_ext_start_stop_x; 116 u32 vs_int_start_x; 117 u32 vs_int_stop_x__vs_int_start_y; 118 u32 vs_int_stop_y__vs_ext_start_x; 119 u32 vs_ext_stop_x__vs_ext_start_y; 120 u32 vs_ext_stop_y; 121 u32 avid_start_stop_x; 122 u32 avid_start_stop_y; 123 u32 fid_int_start_x__fid_int_start_y; 124 u32 fid_int_offset_y__fid_ext_start_x; 125 u32 fid_ext_start_y__fid_ext_offset_y; 126 u32 tvdetgp_int_start_stop_x; 127 u32 tvdetgp_int_start_stop_y; 128 u32 gen_ctrl; 129 }; 130 131 /* from TRM */ 132 static const struct venc_config venc_config_pal_trm = { 133 .f_control = 0, 134 .vidout_ctrl = 1, 135 .sync_ctrl = 0x40, 136 .llen = 0x35F, /* 863 */ 137 .flens = 0x270, /* 624 */ 138 .hfltr_ctrl = 0, 139 .cc_carr_wss_carr = 0x2F7225ED, 140 .c_phase = 0, 141 .gain_u = 0x111, 142 .gain_v = 0x181, 143 .gain_y = 0x140, 144 .black_level = 0x3B, 145 .blank_level = 0x3B, 146 .x_color = 0x7, 147 .m_control = 0x2, 148 .bstamp_wss_data = 0x3F, 149 .s_carr = 0x2A098ACB, 150 .line21 = 0, 151 .ln_sel = 0x01290015, 152 .l21__wc_ctl = 0x0000F603, 153 .htrigger_vtrigger = 0, 154 155 .savid__eavid = 0x06A70108, 156 .flen__fal = 0x00180270, 157 .lal__phase_reset = 0x00040135, 158 .hs_int_start_stop_x = 0x00880358, 159 .hs_ext_start_stop_x = 0x000F035F, 160 .vs_int_start_x = 0x01A70000, 161 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 164 .vs_ext_stop_y = 0x00000025, 165 .avid_start_stop_x = 0x03530083, 166 .avid_start_stop_y = 0x026C002E, 167 .fid_int_start_x__fid_int_start_y = 0x0001008A, 168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 170 171 .tvdetgp_int_start_stop_x = 0x00140001, 172 .tvdetgp_int_start_stop_y = 0x00010001, 173 .gen_ctrl = 0x00FF0000, 174 }; 175 176 /* from TRM */ 177 static const struct venc_config venc_config_ntsc_trm = { 178 .f_control = 0, 179 .vidout_ctrl = 1, 180 .sync_ctrl = 0x8040, 181 .llen = 0x359, 182 .flens = 0x20C, 183 .hfltr_ctrl = 0, 184 .cc_carr_wss_carr = 0x043F2631, 185 .c_phase = 0, 186 .gain_u = 0x102, 187 .gain_v = 0x16C, 188 .gain_y = 0x12F, 189 .black_level = 0x43, 190 .blank_level = 0x38, 191 .x_color = 0x7, 192 .m_control = 0x1, 193 .bstamp_wss_data = 0x38, 194 .s_carr = 0x21F07C1F, 195 .line21 = 0, 196 .ln_sel = 0x01310011, 197 .l21__wc_ctl = 0x0000F003, 198 .htrigger_vtrigger = 0, 199 200 .savid__eavid = 0x069300F4, 201 .flen__fal = 0x0016020C, 202 .lal__phase_reset = 0x00060107, 203 .hs_int_start_stop_x = 0x008E0350, 204 .hs_ext_start_stop_x = 0x000F0359, 205 .vs_int_start_x = 0x01A00000, 206 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 209 .vs_ext_stop_y = 0x00000006, 210 .avid_start_stop_x = 0x03480078, 211 .avid_start_stop_y = 0x02060024, 212 .fid_int_start_x__fid_int_start_y = 0x0001008A, 213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 215 216 .tvdetgp_int_start_stop_x = 0x00140001, 217 .tvdetgp_int_start_stop_y = 0x00010001, 218 .gen_ctrl = 0x00F90000, 219 }; 220 221 static const struct venc_config venc_config_pal_bdghi = { 222 .f_control = 0, 223 .vidout_ctrl = 0, 224 .sync_ctrl = 0, 225 .hfltr_ctrl = 0, 226 .x_color = 0, 227 .line21 = 0, 228 .ln_sel = 21, 229 .htrigger_vtrigger = 0, 230 .tvdetgp_int_start_stop_x = 0x00140001, 231 .tvdetgp_int_start_stop_y = 0x00010001, 232 .gen_ctrl = 0x00FB0000, 233 234 .llen = 864-1, 235 .flens = 625-1, 236 .cc_carr_wss_carr = 0x2F7625ED, 237 .c_phase = 0xDF, 238 .gain_u = 0x111, 239 .gain_v = 0x181, 240 .gain_y = 0x140, 241 .black_level = 0x3e, 242 .blank_level = 0x3e, 243 .m_control = 0<<2 | 1<<1, 244 .bstamp_wss_data = 0x42, 245 .s_carr = 0x2a098acb, 246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, 247 .savid__eavid = 0x06A70108, 248 .flen__fal = 23<<16 | 624<<0, 249 .lal__phase_reset = 2<<17 | 310<<0, 250 .hs_int_start_stop_x = 0x00920358, 251 .hs_ext_start_stop_x = 0x000F035F, 252 .vs_int_start_x = 0x1a7<<16, 253 .vs_int_stop_x__vs_int_start_y = 0x000601A7, 254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, 255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af, 256 .vs_ext_stop_y = 0x05, 257 .avid_start_stop_x = 0x03530082, 258 .avid_start_stop_y = 0x0270002E, 259 .fid_int_start_x__fid_int_start_y = 0x0005008A, 260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 }; 263 264 enum venc_videomode { 265 VENC_MODE_UNKNOWN, 266 VENC_MODE_PAL, 267 VENC_MODE_NTSC, 268 }; 269 270 static const struct videomode omap_dss_pal_vm = { 271 .hactive = 720, 272 .vactive = 574, 273 .pixelclock = 13500000, 274 .hsync_len = 64, 275 .hfront_porch = 12, 276 .hback_porch = 68, 277 .vsync_len = 5, 278 .vfront_porch = 5, 279 .vback_porch = 41, 280 281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 283 DISPLAY_FLAGS_PIXDATA_POSEDGE | 284 DISPLAY_FLAGS_SYNC_NEGEDGE, 285 }; 286 287 static const struct videomode omap_dss_ntsc_vm = { 288 .hactive = 720, 289 .vactive = 482, 290 .pixelclock = 13500000, 291 .hsync_len = 64, 292 .hfront_porch = 16, 293 .hback_porch = 58, 294 .vsync_len = 6, 295 .vfront_porch = 6, 296 .vback_porch = 31, 297 298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 300 DISPLAY_FLAGS_PIXDATA_POSEDGE | 301 DISPLAY_FLAGS_SYNC_NEGEDGE, 302 }; 303 304 static enum venc_videomode venc_get_videomode(const struct videomode *vm) 305 { 306 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) 307 return VENC_MODE_UNKNOWN; 308 309 if (vm->pixelclock == omap_dss_pal_vm.pixelclock && 310 vm->hactive == omap_dss_pal_vm.hactive && 311 vm->vactive == omap_dss_pal_vm.vactive) 312 return VENC_MODE_PAL; 313 314 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && 315 vm->hactive == omap_dss_ntsc_vm.hactive && 316 vm->vactive == omap_dss_ntsc_vm.vactive) 317 return VENC_MODE_NTSC; 318 319 return VENC_MODE_UNKNOWN; 320 } 321 322 struct venc_device { 323 struct platform_device *pdev; 324 void __iomem *base; 325 struct mutex venc_lock; 326 u32 wss_data; 327 struct regulator *vdda_dac_reg; 328 struct dss_device *dss; 329 330 struct dss_debugfs_entry *debugfs; 331 332 struct clk *tv_dac_clk; 333 334 struct videomode vm; 335 enum omap_dss_venc_type type; 336 bool invert_polarity; 337 bool requires_tv_dac_clk; 338 339 struct omap_dss_device output; 340 }; 341 342 #define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output) 343 344 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val) 345 { 346 __raw_writel(val, venc->base + idx); 347 } 348 349 static inline u32 venc_read_reg(struct venc_device *venc, int idx) 350 { 351 u32 l = __raw_readl(venc->base + idx); 352 return l; 353 } 354 355 static void venc_write_config(struct venc_device *venc, 356 const struct venc_config *config) 357 { 358 DSSDBG("write venc conf\n"); 359 360 venc_write_reg(venc, VENC_LLEN, config->llen); 361 venc_write_reg(venc, VENC_FLENS, config->flens); 362 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 363 venc_write_reg(venc, VENC_C_PHASE, config->c_phase); 364 venc_write_reg(venc, VENC_GAIN_U, config->gain_u); 365 venc_write_reg(venc, VENC_GAIN_V, config->gain_v); 366 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y); 367 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level); 368 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level); 369 venc_write_reg(venc, VENC_M_CONTROL, config->m_control); 370 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 371 venc->wss_data); 372 venc_write_reg(venc, VENC_S_CARR, config->s_carr); 373 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl); 374 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid); 375 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal); 376 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset); 377 venc_write_reg(venc, VENC_HS_INT_START_STOP_X, 378 config->hs_int_start_stop_x); 379 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X, 380 config->hs_ext_start_stop_x); 381 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x); 382 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y, 383 config->vs_int_stop_x__vs_int_start_y); 384 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X, 385 config->vs_int_stop_y__vs_ext_start_x); 386 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 387 config->vs_ext_stop_x__vs_ext_start_y); 388 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 389 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x); 390 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 391 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y, 392 config->fid_int_start_x__fid_int_start_y); 393 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 394 config->fid_int_offset_y__fid_ext_start_x); 395 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 396 config->fid_ext_start_y__fid_ext_offset_y); 397 398 venc_write_reg(venc, VENC_DAC_B__DAC_C, 399 venc_read_reg(venc, VENC_DAC_B__DAC_C)); 400 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl); 401 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl); 402 venc_write_reg(venc, VENC_X_COLOR, config->x_color); 403 venc_write_reg(venc, VENC_LINE21, config->line21); 404 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel); 405 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 406 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X, 407 config->tvdetgp_int_start_stop_x); 408 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y, 409 config->tvdetgp_int_start_stop_y); 410 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl); 411 venc_write_reg(venc, VENC_F_CONTROL, config->f_control); 412 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl); 413 } 414 415 static void venc_reset(struct venc_device *venc) 416 { 417 int t = 1000; 418 419 venc_write_reg(venc, VENC_F_CONTROL, 1<<8); 420 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) { 421 if (--t == 0) { 422 DSSERR("Failed to reset venc\n"); 423 return; 424 } 425 } 426 427 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 428 /* the magical sleep that makes things work */ 429 /* XXX more info? What bug this circumvents? */ 430 msleep(20); 431 #endif 432 } 433 434 static int venc_runtime_get(struct venc_device *venc) 435 { 436 int r; 437 438 DSSDBG("venc_runtime_get\n"); 439 440 r = pm_runtime_get_sync(&venc->pdev->dev); 441 WARN_ON(r < 0); 442 return r < 0 ? r : 0; 443 } 444 445 static void venc_runtime_put(struct venc_device *venc) 446 { 447 int r; 448 449 DSSDBG("venc_runtime_put\n"); 450 451 r = pm_runtime_put_sync(&venc->pdev->dev); 452 WARN_ON(r < 0 && r != -ENOSYS); 453 } 454 455 static const struct venc_config *venc_timings_to_config(const struct videomode *vm) 456 { 457 switch (venc_get_videomode(vm)) { 458 default: 459 WARN_ON_ONCE(1); 460 case VENC_MODE_PAL: 461 return &venc_config_pal_trm; 462 case VENC_MODE_NTSC: 463 return &venc_config_ntsc_trm; 464 } 465 } 466 467 static int venc_power_on(struct venc_device *venc) 468 { 469 u32 l; 470 int r; 471 472 r = venc_runtime_get(venc); 473 if (r) 474 goto err0; 475 476 venc_reset(venc); 477 venc_write_config(venc, venc_timings_to_config(&venc->vm)); 478 479 dss_set_venc_output(venc->dss, venc->type); 480 dss_set_dac_pwrdn_bgz(venc->dss, 1); 481 482 l = 0; 483 484 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE) 485 l |= 1 << 1; 486 else /* S-Video */ 487 l |= (1 << 0) | (1 << 2); 488 489 if (venc->invert_polarity == false) 490 l |= 1 << 3; 491 492 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l); 493 494 r = regulator_enable(venc->vdda_dac_reg); 495 if (r) 496 goto err1; 497 498 r = dss_mgr_enable(&venc->output); 499 if (r) 500 goto err2; 501 502 return 0; 503 504 err2: 505 regulator_disable(venc->vdda_dac_reg); 506 err1: 507 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 508 dss_set_dac_pwrdn_bgz(venc->dss, 0); 509 510 venc_runtime_put(venc); 511 err0: 512 return r; 513 } 514 515 static void venc_power_off(struct venc_device *venc) 516 { 517 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 518 dss_set_dac_pwrdn_bgz(venc->dss, 0); 519 520 dss_mgr_disable(&venc->output); 521 522 regulator_disable(venc->vdda_dac_reg); 523 524 venc_runtime_put(venc); 525 } 526 527 static int venc_display_enable(struct omap_dss_device *dssdev) 528 { 529 struct venc_device *venc = dssdev_to_venc(dssdev); 530 int r; 531 532 DSSDBG("venc_display_enable\n"); 533 534 mutex_lock(&venc->venc_lock); 535 536 if (!dssdev->dispc_channel_connected) { 537 DSSERR("Failed to enable display: no output/manager\n"); 538 r = -ENODEV; 539 goto err0; 540 } 541 542 r = venc_power_on(venc); 543 if (r) 544 goto err0; 545 546 venc->wss_data = 0; 547 548 mutex_unlock(&venc->venc_lock); 549 550 return 0; 551 err0: 552 mutex_unlock(&venc->venc_lock); 553 return r; 554 } 555 556 static void venc_display_disable(struct omap_dss_device *dssdev) 557 { 558 struct venc_device *venc = dssdev_to_venc(dssdev); 559 560 DSSDBG("venc_display_disable\n"); 561 562 mutex_lock(&venc->venc_lock); 563 564 venc_power_off(venc); 565 566 mutex_unlock(&venc->venc_lock); 567 } 568 569 static void venc_get_timings(struct omap_dss_device *dssdev, 570 struct videomode *vm) 571 { 572 struct venc_device *venc = dssdev_to_venc(dssdev); 573 574 mutex_lock(&venc->venc_lock); 575 *vm = venc->vm; 576 mutex_unlock(&venc->venc_lock); 577 } 578 579 static void venc_set_timings(struct omap_dss_device *dssdev, 580 const struct videomode *vm) 581 { 582 struct venc_device *venc = dssdev_to_venc(dssdev); 583 584 DSSDBG("venc_set_timings\n"); 585 586 mutex_lock(&venc->venc_lock); 587 588 /* Reset WSS data when the TV standard changes. */ 589 if (memcmp(&venc->vm, vm, sizeof(*vm))) 590 venc->wss_data = 0; 591 592 venc->vm = *vm; 593 594 dispc_set_tv_pclk(venc->dss->dispc, 13500000); 595 596 mutex_unlock(&venc->venc_lock); 597 } 598 599 static int venc_check_timings(struct omap_dss_device *dssdev, 600 struct videomode *vm) 601 { 602 DSSDBG("venc_check_timings\n"); 603 604 switch (venc_get_videomode(vm)) { 605 case VENC_MODE_PAL: 606 *vm = omap_dss_pal_vm; 607 return 0; 608 609 case VENC_MODE_NTSC: 610 *vm = omap_dss_ntsc_vm; 611 return 0; 612 613 default: 614 return -EINVAL; 615 } 616 } 617 618 static int venc_dump_regs(struct seq_file *s, void *p) 619 { 620 struct venc_device *venc = s->private; 621 622 #define DUMPREG(venc, r) \ 623 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r)) 624 625 if (venc_runtime_get(venc)) 626 return 0; 627 628 DUMPREG(venc, VENC_F_CONTROL); 629 DUMPREG(venc, VENC_VIDOUT_CTRL); 630 DUMPREG(venc, VENC_SYNC_CTRL); 631 DUMPREG(venc, VENC_LLEN); 632 DUMPREG(venc, VENC_FLENS); 633 DUMPREG(venc, VENC_HFLTR_CTRL); 634 DUMPREG(venc, VENC_CC_CARR_WSS_CARR); 635 DUMPREG(venc, VENC_C_PHASE); 636 DUMPREG(venc, VENC_GAIN_U); 637 DUMPREG(venc, VENC_GAIN_V); 638 DUMPREG(venc, VENC_GAIN_Y); 639 DUMPREG(venc, VENC_BLACK_LEVEL); 640 DUMPREG(venc, VENC_BLANK_LEVEL); 641 DUMPREG(venc, VENC_X_COLOR); 642 DUMPREG(venc, VENC_M_CONTROL); 643 DUMPREG(venc, VENC_BSTAMP_WSS_DATA); 644 DUMPREG(venc, VENC_S_CARR); 645 DUMPREG(venc, VENC_LINE21); 646 DUMPREG(venc, VENC_LN_SEL); 647 DUMPREG(venc, VENC_L21__WC_CTL); 648 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER); 649 DUMPREG(venc, VENC_SAVID__EAVID); 650 DUMPREG(venc, VENC_FLEN__FAL); 651 DUMPREG(venc, VENC_LAL__PHASE_RESET); 652 DUMPREG(venc, VENC_HS_INT_START_STOP_X); 653 DUMPREG(venc, VENC_HS_EXT_START_STOP_X); 654 DUMPREG(venc, VENC_VS_INT_START_X); 655 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y); 656 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X); 657 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 658 DUMPREG(venc, VENC_VS_EXT_STOP_Y); 659 DUMPREG(venc, VENC_AVID_START_STOP_X); 660 DUMPREG(venc, VENC_AVID_START_STOP_Y); 661 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y); 662 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 663 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 664 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X); 665 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y); 666 DUMPREG(venc, VENC_GEN_CTRL); 667 DUMPREG(venc, VENC_OUTPUT_CONTROL); 668 DUMPREG(venc, VENC_OUTPUT_TEST); 669 670 venc_runtime_put(venc); 671 672 #undef DUMPREG 673 return 0; 674 } 675 676 static int venc_get_clocks(struct venc_device *venc) 677 { 678 struct clk *clk; 679 680 if (venc->requires_tv_dac_clk) { 681 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk"); 682 if (IS_ERR(clk)) { 683 DSSERR("can't get tv_dac_clk\n"); 684 return PTR_ERR(clk); 685 } 686 } else { 687 clk = NULL; 688 } 689 690 venc->tv_dac_clk = clk; 691 692 return 0; 693 } 694 695 static int venc_connect(struct omap_dss_device *src, 696 struct omap_dss_device *dst) 697 { 698 int r; 699 700 r = omapdss_device_connect(dst->dss, dst, dst->next); 701 if (r) 702 return r; 703 704 dst->dispc_channel_connected = true; 705 return 0; 706 } 707 708 static void venc_disconnect(struct omap_dss_device *src, 709 struct omap_dss_device *dst) 710 { 711 dst->dispc_channel_connected = false; 712 713 omapdss_device_disconnect(dst, dst->next); 714 } 715 716 static const struct omap_dss_device_ops venc_ops = { 717 .connect = venc_connect, 718 .disconnect = venc_disconnect, 719 720 .enable = venc_display_enable, 721 .disable = venc_display_disable, 722 723 .check_timings = venc_check_timings, 724 .get_timings = venc_get_timings, 725 .set_timings = venc_set_timings, 726 }; 727 728 /* ----------------------------------------------------------------------------- 729 * Component Bind & Unbind 730 */ 731 732 static int venc_bind(struct device *dev, struct device *master, void *data) 733 { 734 struct dss_device *dss = dss_get_device(master); 735 struct venc_device *venc = dev_get_drvdata(dev); 736 u8 rev_id; 737 int r; 738 739 venc->dss = dss; 740 741 r = venc_runtime_get(venc); 742 if (r) 743 return r; 744 745 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff); 746 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id); 747 748 venc_runtime_put(venc); 749 750 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs, 751 venc); 752 753 return 0; 754 } 755 756 static void venc_unbind(struct device *dev, struct device *master, void *data) 757 { 758 struct venc_device *venc = dev_get_drvdata(dev); 759 760 dss_debugfs_remove_file(venc->debugfs); 761 } 762 763 static const struct component_ops venc_component_ops = { 764 .bind = venc_bind, 765 .unbind = venc_unbind, 766 }; 767 768 /* ----------------------------------------------------------------------------- 769 * Probe & Remove, Suspend & Resume 770 */ 771 772 static int venc_init_output(struct venc_device *venc) 773 { 774 struct omap_dss_device *out = &venc->output; 775 int r; 776 777 out->dev = &venc->pdev->dev; 778 out->id = OMAP_DSS_OUTPUT_VENC; 779 out->output_type = OMAP_DISPLAY_TYPE_VENC; 780 out->name = "venc.0"; 781 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 782 out->ops = &venc_ops; 783 out->owner = THIS_MODULE; 784 out->of_ports = BIT(0); 785 786 out->next = omapdss_of_find_connected_device(out->dev->of_node, 0); 787 if (IS_ERR(out->next)) { 788 if (PTR_ERR(out->next) != -EPROBE_DEFER) 789 dev_err(out->dev, "failed to find video sink\n"); 790 return PTR_ERR(out->next); 791 } 792 793 r = omapdss_output_validate(out); 794 if (r) { 795 omapdss_device_put(out->next); 796 out->next = NULL; 797 return r; 798 } 799 800 omapdss_device_register(out); 801 802 return 0; 803 } 804 805 static void venc_uninit_output(struct venc_device *venc) 806 { 807 if (venc->output.next) 808 omapdss_device_put(venc->output.next); 809 omapdss_device_unregister(&venc->output); 810 } 811 812 static int venc_probe_of(struct venc_device *venc) 813 { 814 struct device_node *node = venc->pdev->dev.of_node; 815 struct device_node *ep; 816 u32 channels; 817 int r; 818 819 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 820 if (!ep) 821 return 0; 822 823 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 824 825 r = of_property_read_u32(ep, "ti,channels", &channels); 826 if (r) { 827 dev_err(&venc->pdev->dev, 828 "failed to read property 'ti,channels': %d\n", r); 829 goto err; 830 } 831 832 switch (channels) { 833 case 1: 834 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE; 835 break; 836 case 2: 837 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO; 838 break; 839 default: 840 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n", 841 channels); 842 r = -EINVAL; 843 goto err; 844 } 845 846 of_node_put(ep); 847 848 return 0; 849 850 err: 851 of_node_put(ep); 852 return r; 853 } 854 855 static const struct soc_device_attribute venc_soc_devices[] = { 856 { .machine = "OMAP3[45]*" }, 857 { .machine = "AM35*" }, 858 { /* sentinel */ } 859 }; 860 861 static int venc_probe(struct platform_device *pdev) 862 { 863 struct venc_device *venc; 864 struct resource *venc_mem; 865 int r; 866 867 venc = kzalloc(sizeof(*venc), GFP_KERNEL); 868 if (!venc) 869 return -ENOMEM; 870 871 venc->pdev = pdev; 872 873 platform_set_drvdata(pdev, venc); 874 875 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 876 if (soc_device_match(venc_soc_devices)) 877 venc->requires_tv_dac_clk = true; 878 879 mutex_init(&venc->venc_lock); 880 881 venc->wss_data = 0; 882 venc->vm = omap_dss_pal_vm; 883 884 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0); 885 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem); 886 if (IS_ERR(venc->base)) { 887 r = PTR_ERR(venc->base); 888 goto err_free; 889 } 890 891 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda"); 892 if (IS_ERR(venc->vdda_dac_reg)) { 893 r = PTR_ERR(venc->vdda_dac_reg); 894 if (r != -EPROBE_DEFER) 895 DSSERR("can't get VDDA_DAC regulator\n"); 896 goto err_free; 897 } 898 899 r = venc_get_clocks(venc); 900 if (r) 901 goto err_free; 902 903 r = venc_probe_of(venc); 904 if (r) 905 goto err_free; 906 907 pm_runtime_enable(&pdev->dev); 908 909 r = venc_init_output(venc); 910 if (r) 911 goto err_pm_disable; 912 913 r = component_add(&pdev->dev, &venc_component_ops); 914 if (r) 915 goto err_uninit_output; 916 917 return 0; 918 919 err_uninit_output: 920 venc_uninit_output(venc); 921 err_pm_disable: 922 pm_runtime_disable(&pdev->dev); 923 err_free: 924 kfree(venc); 925 return r; 926 } 927 928 static int venc_remove(struct platform_device *pdev) 929 { 930 struct venc_device *venc = platform_get_drvdata(pdev); 931 932 component_del(&pdev->dev, &venc_component_ops); 933 934 venc_uninit_output(venc); 935 936 pm_runtime_disable(&pdev->dev); 937 938 kfree(venc); 939 return 0; 940 } 941 942 static int venc_runtime_suspend(struct device *dev) 943 { 944 struct venc_device *venc = dev_get_drvdata(dev); 945 946 if (venc->tv_dac_clk) 947 clk_disable_unprepare(venc->tv_dac_clk); 948 949 return 0; 950 } 951 952 static int venc_runtime_resume(struct device *dev) 953 { 954 struct venc_device *venc = dev_get_drvdata(dev); 955 956 if (venc->tv_dac_clk) 957 clk_prepare_enable(venc->tv_dac_clk); 958 959 return 0; 960 } 961 962 static const struct dev_pm_ops venc_pm_ops = { 963 .runtime_suspend = venc_runtime_suspend, 964 .runtime_resume = venc_runtime_resume, 965 }; 966 967 static const struct of_device_id venc_of_match[] = { 968 { .compatible = "ti,omap2-venc", }, 969 { .compatible = "ti,omap3-venc", }, 970 { .compatible = "ti,omap4-venc", }, 971 {}, 972 }; 973 974 struct platform_driver omap_venchw_driver = { 975 .probe = venc_probe, 976 .remove = venc_remove, 977 .driver = { 978 .name = "omapdss_venc", 979 .pm = &venc_pm_ops, 980 .of_match_table = venc_of_match, 981 .suppress_bind_attrs = true, 982 }, 983 }; 984