1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * VENC settings from TI's DSS driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "VENC" 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/mutex.h> 28 #include <linux/completion.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/seq_file.h> 32 #include <linux/platform_device.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/of.h> 36 #include <linux/of_graph.h> 37 #include <linux/component.h> 38 #include <linux/sys_soc.h> 39 40 #include "omapdss.h" 41 #include "dss.h" 42 43 /* Venc registers */ 44 #define VENC_REV_ID 0x00 45 #define VENC_STATUS 0x04 46 #define VENC_F_CONTROL 0x08 47 #define VENC_VIDOUT_CTRL 0x10 48 #define VENC_SYNC_CTRL 0x14 49 #define VENC_LLEN 0x1C 50 #define VENC_FLENS 0x20 51 #define VENC_HFLTR_CTRL 0x24 52 #define VENC_CC_CARR_WSS_CARR 0x28 53 #define VENC_C_PHASE 0x2C 54 #define VENC_GAIN_U 0x30 55 #define VENC_GAIN_V 0x34 56 #define VENC_GAIN_Y 0x38 57 #define VENC_BLACK_LEVEL 0x3C 58 #define VENC_BLANK_LEVEL 0x40 59 #define VENC_X_COLOR 0x44 60 #define VENC_M_CONTROL 0x48 61 #define VENC_BSTAMP_WSS_DATA 0x4C 62 #define VENC_S_CARR 0x50 63 #define VENC_LINE21 0x54 64 #define VENC_LN_SEL 0x58 65 #define VENC_L21__WC_CTL 0x5C 66 #define VENC_HTRIGGER_VTRIGGER 0x60 67 #define VENC_SAVID__EAVID 0x64 68 #define VENC_FLEN__FAL 0x68 69 #define VENC_LAL__PHASE_RESET 0x6C 70 #define VENC_HS_INT_START_STOP_X 0x70 71 #define VENC_HS_EXT_START_STOP_X 0x74 72 #define VENC_VS_INT_START_X 0x78 73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 76 #define VENC_VS_EXT_STOP_Y 0x88 77 #define VENC_AVID_START_STOP_X 0x90 78 #define VENC_AVID_START_STOP_Y 0x94 79 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 82 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 83 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 84 #define VENC_GEN_CTRL 0xB8 85 #define VENC_OUTPUT_CONTROL 0xC4 86 #define VENC_OUTPUT_TEST 0xC8 87 #define VENC_DAC_B__DAC_C 0xC8 88 89 struct venc_config { 90 u32 f_control; 91 u32 vidout_ctrl; 92 u32 sync_ctrl; 93 u32 llen; 94 u32 flens; 95 u32 hfltr_ctrl; 96 u32 cc_carr_wss_carr; 97 u32 c_phase; 98 u32 gain_u; 99 u32 gain_v; 100 u32 gain_y; 101 u32 black_level; 102 u32 blank_level; 103 u32 x_color; 104 u32 m_control; 105 u32 bstamp_wss_data; 106 u32 s_carr; 107 u32 line21; 108 u32 ln_sel; 109 u32 l21__wc_ctl; 110 u32 htrigger_vtrigger; 111 u32 savid__eavid; 112 u32 flen__fal; 113 u32 lal__phase_reset; 114 u32 hs_int_start_stop_x; 115 u32 hs_ext_start_stop_x; 116 u32 vs_int_start_x; 117 u32 vs_int_stop_x__vs_int_start_y; 118 u32 vs_int_stop_y__vs_ext_start_x; 119 u32 vs_ext_stop_x__vs_ext_start_y; 120 u32 vs_ext_stop_y; 121 u32 avid_start_stop_x; 122 u32 avid_start_stop_y; 123 u32 fid_int_start_x__fid_int_start_y; 124 u32 fid_int_offset_y__fid_ext_start_x; 125 u32 fid_ext_start_y__fid_ext_offset_y; 126 u32 tvdetgp_int_start_stop_x; 127 u32 tvdetgp_int_start_stop_y; 128 u32 gen_ctrl; 129 }; 130 131 /* from TRM */ 132 static const struct venc_config venc_config_pal_trm = { 133 .f_control = 0, 134 .vidout_ctrl = 1, 135 .sync_ctrl = 0x40, 136 .llen = 0x35F, /* 863 */ 137 .flens = 0x270, /* 624 */ 138 .hfltr_ctrl = 0, 139 .cc_carr_wss_carr = 0x2F7225ED, 140 .c_phase = 0, 141 .gain_u = 0x111, 142 .gain_v = 0x181, 143 .gain_y = 0x140, 144 .black_level = 0x3B, 145 .blank_level = 0x3B, 146 .x_color = 0x7, 147 .m_control = 0x2, 148 .bstamp_wss_data = 0x3F, 149 .s_carr = 0x2A098ACB, 150 .line21 = 0, 151 .ln_sel = 0x01290015, 152 .l21__wc_ctl = 0x0000F603, 153 .htrigger_vtrigger = 0, 154 155 .savid__eavid = 0x06A70108, 156 .flen__fal = 0x00180270, 157 .lal__phase_reset = 0x00040135, 158 .hs_int_start_stop_x = 0x00880358, 159 .hs_ext_start_stop_x = 0x000F035F, 160 .vs_int_start_x = 0x01A70000, 161 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 164 .vs_ext_stop_y = 0x00000025, 165 .avid_start_stop_x = 0x03530083, 166 .avid_start_stop_y = 0x026C002E, 167 .fid_int_start_x__fid_int_start_y = 0x0001008A, 168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 170 171 .tvdetgp_int_start_stop_x = 0x00140001, 172 .tvdetgp_int_start_stop_y = 0x00010001, 173 .gen_ctrl = 0x00FF0000, 174 }; 175 176 /* from TRM */ 177 static const struct venc_config venc_config_ntsc_trm = { 178 .f_control = 0, 179 .vidout_ctrl = 1, 180 .sync_ctrl = 0x8040, 181 .llen = 0x359, 182 .flens = 0x20C, 183 .hfltr_ctrl = 0, 184 .cc_carr_wss_carr = 0x043F2631, 185 .c_phase = 0, 186 .gain_u = 0x102, 187 .gain_v = 0x16C, 188 .gain_y = 0x12F, 189 .black_level = 0x43, 190 .blank_level = 0x38, 191 .x_color = 0x7, 192 .m_control = 0x1, 193 .bstamp_wss_data = 0x38, 194 .s_carr = 0x21F07C1F, 195 .line21 = 0, 196 .ln_sel = 0x01310011, 197 .l21__wc_ctl = 0x0000F003, 198 .htrigger_vtrigger = 0, 199 200 .savid__eavid = 0x069300F4, 201 .flen__fal = 0x0016020C, 202 .lal__phase_reset = 0x00060107, 203 .hs_int_start_stop_x = 0x008E0350, 204 .hs_ext_start_stop_x = 0x000F0359, 205 .vs_int_start_x = 0x01A00000, 206 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 209 .vs_ext_stop_y = 0x00000006, 210 .avid_start_stop_x = 0x03480078, 211 .avid_start_stop_y = 0x02060024, 212 .fid_int_start_x__fid_int_start_y = 0x0001008A, 213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 215 216 .tvdetgp_int_start_stop_x = 0x00140001, 217 .tvdetgp_int_start_stop_y = 0x00010001, 218 .gen_ctrl = 0x00F90000, 219 }; 220 221 static const struct venc_config venc_config_pal_bdghi = { 222 .f_control = 0, 223 .vidout_ctrl = 0, 224 .sync_ctrl = 0, 225 .hfltr_ctrl = 0, 226 .x_color = 0, 227 .line21 = 0, 228 .ln_sel = 21, 229 .htrigger_vtrigger = 0, 230 .tvdetgp_int_start_stop_x = 0x00140001, 231 .tvdetgp_int_start_stop_y = 0x00010001, 232 .gen_ctrl = 0x00FB0000, 233 234 .llen = 864-1, 235 .flens = 625-1, 236 .cc_carr_wss_carr = 0x2F7625ED, 237 .c_phase = 0xDF, 238 .gain_u = 0x111, 239 .gain_v = 0x181, 240 .gain_y = 0x140, 241 .black_level = 0x3e, 242 .blank_level = 0x3e, 243 .m_control = 0<<2 | 1<<1, 244 .bstamp_wss_data = 0x42, 245 .s_carr = 0x2a098acb, 246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, 247 .savid__eavid = 0x06A70108, 248 .flen__fal = 23<<16 | 624<<0, 249 .lal__phase_reset = 2<<17 | 310<<0, 250 .hs_int_start_stop_x = 0x00920358, 251 .hs_ext_start_stop_x = 0x000F035F, 252 .vs_int_start_x = 0x1a7<<16, 253 .vs_int_stop_x__vs_int_start_y = 0x000601A7, 254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, 255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af, 256 .vs_ext_stop_y = 0x05, 257 .avid_start_stop_x = 0x03530082, 258 .avid_start_stop_y = 0x0270002E, 259 .fid_int_start_x__fid_int_start_y = 0x0005008A, 260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 }; 263 264 enum venc_videomode { 265 VENC_MODE_UNKNOWN, 266 VENC_MODE_PAL, 267 VENC_MODE_NTSC, 268 }; 269 270 static const struct videomode omap_dss_pal_vm = { 271 .hactive = 720, 272 .vactive = 574, 273 .pixelclock = 13500000, 274 .hsync_len = 64, 275 .hfront_porch = 12, 276 .hback_porch = 68, 277 .vsync_len = 5, 278 .vfront_porch = 5, 279 .vback_porch = 41, 280 281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 283 DISPLAY_FLAGS_PIXDATA_POSEDGE | 284 DISPLAY_FLAGS_SYNC_NEGEDGE, 285 }; 286 287 static const struct videomode omap_dss_ntsc_vm = { 288 .hactive = 720, 289 .vactive = 482, 290 .pixelclock = 13500000, 291 .hsync_len = 64, 292 .hfront_porch = 16, 293 .hback_porch = 58, 294 .vsync_len = 6, 295 .vfront_porch = 6, 296 .vback_porch = 31, 297 298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 300 DISPLAY_FLAGS_PIXDATA_POSEDGE | 301 DISPLAY_FLAGS_SYNC_NEGEDGE, 302 }; 303 304 static enum venc_videomode venc_get_videomode(const struct videomode *vm) 305 { 306 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) 307 return VENC_MODE_UNKNOWN; 308 309 if (vm->pixelclock == omap_dss_pal_vm.pixelclock && 310 vm->hactive == omap_dss_pal_vm.hactive && 311 vm->vactive == omap_dss_pal_vm.vactive) 312 return VENC_MODE_PAL; 313 314 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && 315 vm->hactive == omap_dss_ntsc_vm.hactive && 316 vm->vactive == omap_dss_ntsc_vm.vactive) 317 return VENC_MODE_NTSC; 318 319 return VENC_MODE_UNKNOWN; 320 } 321 322 static struct { 323 struct platform_device *pdev; 324 void __iomem *base; 325 struct mutex venc_lock; 326 u32 wss_data; 327 struct regulator *vdda_dac_reg; 328 329 struct clk *tv_dac_clk; 330 331 struct videomode vm; 332 enum omap_dss_venc_type type; 333 bool invert_polarity; 334 bool requires_tv_dac_clk; 335 336 struct omap_dss_device output; 337 } venc; 338 339 static inline void venc_write_reg(int idx, u32 val) 340 { 341 __raw_writel(val, venc.base + idx); 342 } 343 344 static inline u32 venc_read_reg(int idx) 345 { 346 u32 l = __raw_readl(venc.base + idx); 347 return l; 348 } 349 350 static void venc_write_config(const struct venc_config *config) 351 { 352 DSSDBG("write venc conf\n"); 353 354 venc_write_reg(VENC_LLEN, config->llen); 355 venc_write_reg(VENC_FLENS, config->flens); 356 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 357 venc_write_reg(VENC_C_PHASE, config->c_phase); 358 venc_write_reg(VENC_GAIN_U, config->gain_u); 359 venc_write_reg(VENC_GAIN_V, config->gain_v); 360 venc_write_reg(VENC_GAIN_Y, config->gain_y); 361 venc_write_reg(VENC_BLACK_LEVEL, config->black_level); 362 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); 363 venc_write_reg(VENC_M_CONTROL, config->m_control); 364 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 365 venc.wss_data); 366 venc_write_reg(VENC_S_CARR, config->s_carr); 367 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); 368 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); 369 venc_write_reg(VENC_FLEN__FAL, config->flen__fal); 370 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); 371 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); 372 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); 373 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); 374 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, 375 config->vs_int_stop_x__vs_int_start_y); 376 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, 377 config->vs_int_stop_y__vs_ext_start_x); 378 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 379 config->vs_ext_stop_x__vs_ext_start_y); 380 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 381 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); 382 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 383 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, 384 config->fid_int_start_x__fid_int_start_y); 385 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 386 config->fid_int_offset_y__fid_ext_start_x); 387 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 388 config->fid_ext_start_y__fid_ext_offset_y); 389 390 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); 391 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); 392 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); 393 venc_write_reg(VENC_X_COLOR, config->x_color); 394 venc_write_reg(VENC_LINE21, config->line21); 395 venc_write_reg(VENC_LN_SEL, config->ln_sel); 396 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 397 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, 398 config->tvdetgp_int_start_stop_x); 399 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, 400 config->tvdetgp_int_start_stop_y); 401 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); 402 venc_write_reg(VENC_F_CONTROL, config->f_control); 403 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); 404 } 405 406 static void venc_reset(void) 407 { 408 int t = 1000; 409 410 venc_write_reg(VENC_F_CONTROL, 1<<8); 411 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { 412 if (--t == 0) { 413 DSSERR("Failed to reset venc\n"); 414 return; 415 } 416 } 417 418 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 419 /* the magical sleep that makes things work */ 420 /* XXX more info? What bug this circumvents? */ 421 msleep(20); 422 #endif 423 } 424 425 static int venc_runtime_get(void) 426 { 427 int r; 428 429 DSSDBG("venc_runtime_get\n"); 430 431 r = pm_runtime_get_sync(&venc.pdev->dev); 432 WARN_ON(r < 0); 433 return r < 0 ? r : 0; 434 } 435 436 static void venc_runtime_put(void) 437 { 438 int r; 439 440 DSSDBG("venc_runtime_put\n"); 441 442 r = pm_runtime_put_sync(&venc.pdev->dev); 443 WARN_ON(r < 0 && r != -ENOSYS); 444 } 445 446 static const struct venc_config *venc_timings_to_config(struct videomode *vm) 447 { 448 switch (venc_get_videomode(vm)) { 449 default: 450 WARN_ON_ONCE(1); 451 case VENC_MODE_PAL: 452 return &venc_config_pal_trm; 453 case VENC_MODE_NTSC: 454 return &venc_config_ntsc_trm; 455 } 456 } 457 458 static int venc_power_on(struct omap_dss_device *dssdev) 459 { 460 enum omap_channel channel = dssdev->dispc_channel; 461 u32 l; 462 int r; 463 464 r = venc_runtime_get(); 465 if (r) 466 goto err0; 467 468 venc_reset(); 469 venc_write_config(venc_timings_to_config(&venc.vm)); 470 471 dss_set_venc_output(venc.type); 472 dss_set_dac_pwrdn_bgz(1); 473 474 l = 0; 475 476 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) 477 l |= 1 << 1; 478 else /* S-Video */ 479 l |= (1 << 0) | (1 << 2); 480 481 if (venc.invert_polarity == false) 482 l |= 1 << 3; 483 484 venc_write_reg(VENC_OUTPUT_CONTROL, l); 485 486 dss_mgr_set_timings(channel, &venc.vm); 487 488 r = regulator_enable(venc.vdda_dac_reg); 489 if (r) 490 goto err1; 491 492 r = dss_mgr_enable(channel); 493 if (r) 494 goto err2; 495 496 return 0; 497 498 err2: 499 regulator_disable(venc.vdda_dac_reg); 500 err1: 501 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 502 dss_set_dac_pwrdn_bgz(0); 503 504 venc_runtime_put(); 505 err0: 506 return r; 507 } 508 509 static void venc_power_off(struct omap_dss_device *dssdev) 510 { 511 enum omap_channel channel = dssdev->dispc_channel; 512 513 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 514 dss_set_dac_pwrdn_bgz(0); 515 516 dss_mgr_disable(channel); 517 518 regulator_disable(venc.vdda_dac_reg); 519 520 venc_runtime_put(); 521 } 522 523 static int venc_display_enable(struct omap_dss_device *dssdev) 524 { 525 struct omap_dss_device *out = &venc.output; 526 int r; 527 528 DSSDBG("venc_display_enable\n"); 529 530 mutex_lock(&venc.venc_lock); 531 532 if (!out->dispc_channel_connected) { 533 DSSERR("Failed to enable display: no output/manager\n"); 534 r = -ENODEV; 535 goto err0; 536 } 537 538 r = venc_power_on(dssdev); 539 if (r) 540 goto err0; 541 542 venc.wss_data = 0; 543 544 mutex_unlock(&venc.venc_lock); 545 546 return 0; 547 err0: 548 mutex_unlock(&venc.venc_lock); 549 return r; 550 } 551 552 static void venc_display_disable(struct omap_dss_device *dssdev) 553 { 554 DSSDBG("venc_display_disable\n"); 555 556 mutex_lock(&venc.venc_lock); 557 558 venc_power_off(dssdev); 559 560 mutex_unlock(&venc.venc_lock); 561 } 562 563 static void venc_set_timings(struct omap_dss_device *dssdev, 564 struct videomode *vm) 565 { 566 struct videomode actual_vm; 567 568 DSSDBG("venc_set_timings\n"); 569 570 mutex_lock(&venc.venc_lock); 571 572 switch (venc_get_videomode(vm)) { 573 default: 574 WARN_ON_ONCE(1); 575 case VENC_MODE_PAL: 576 actual_vm = omap_dss_pal_vm; 577 break; 578 case VENC_MODE_NTSC: 579 actual_vm = omap_dss_ntsc_vm; 580 break; 581 } 582 583 /* Reset WSS data when the TV standard changes. */ 584 if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm))) 585 venc.wss_data = 0; 586 587 venc.vm = actual_vm; 588 589 dispc_set_tv_pclk(13500000); 590 591 mutex_unlock(&venc.venc_lock); 592 } 593 594 static int venc_check_timings(struct omap_dss_device *dssdev, 595 struct videomode *vm) 596 { 597 DSSDBG("venc_check_timings\n"); 598 599 switch (venc_get_videomode(vm)) { 600 case VENC_MODE_PAL: 601 case VENC_MODE_NTSC: 602 return 0; 603 default: 604 return -EINVAL; 605 } 606 } 607 608 static void venc_get_timings(struct omap_dss_device *dssdev, 609 struct videomode *vm) 610 { 611 mutex_lock(&venc.venc_lock); 612 613 *vm = venc.vm; 614 615 mutex_unlock(&venc.venc_lock); 616 } 617 618 static u32 venc_get_wss(struct omap_dss_device *dssdev) 619 { 620 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 621 return (venc.wss_data >> 8) ^ 0xfffff; 622 } 623 624 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) 625 { 626 const struct venc_config *config; 627 int r; 628 629 DSSDBG("venc_set_wss\n"); 630 631 mutex_lock(&venc.venc_lock); 632 633 config = venc_timings_to_config(&venc.vm); 634 635 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 636 venc.wss_data = (wss ^ 0xfffff) << 8; 637 638 r = venc_runtime_get(); 639 if (r) 640 goto err; 641 642 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 643 venc.wss_data); 644 645 venc_runtime_put(); 646 647 err: 648 mutex_unlock(&venc.venc_lock); 649 650 return r; 651 } 652 653 static int venc_init_regulator(void) 654 { 655 struct regulator *vdda_dac; 656 657 if (venc.vdda_dac_reg != NULL) 658 return 0; 659 660 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); 661 if (IS_ERR(vdda_dac)) { 662 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) 663 DSSERR("can't get VDDA_DAC regulator\n"); 664 return PTR_ERR(vdda_dac); 665 } 666 667 venc.vdda_dac_reg = vdda_dac; 668 669 return 0; 670 } 671 672 static void venc_dump_regs(struct seq_file *s) 673 { 674 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) 675 676 if (venc_runtime_get()) 677 return; 678 679 DUMPREG(VENC_F_CONTROL); 680 DUMPREG(VENC_VIDOUT_CTRL); 681 DUMPREG(VENC_SYNC_CTRL); 682 DUMPREG(VENC_LLEN); 683 DUMPREG(VENC_FLENS); 684 DUMPREG(VENC_HFLTR_CTRL); 685 DUMPREG(VENC_CC_CARR_WSS_CARR); 686 DUMPREG(VENC_C_PHASE); 687 DUMPREG(VENC_GAIN_U); 688 DUMPREG(VENC_GAIN_V); 689 DUMPREG(VENC_GAIN_Y); 690 DUMPREG(VENC_BLACK_LEVEL); 691 DUMPREG(VENC_BLANK_LEVEL); 692 DUMPREG(VENC_X_COLOR); 693 DUMPREG(VENC_M_CONTROL); 694 DUMPREG(VENC_BSTAMP_WSS_DATA); 695 DUMPREG(VENC_S_CARR); 696 DUMPREG(VENC_LINE21); 697 DUMPREG(VENC_LN_SEL); 698 DUMPREG(VENC_L21__WC_CTL); 699 DUMPREG(VENC_HTRIGGER_VTRIGGER); 700 DUMPREG(VENC_SAVID__EAVID); 701 DUMPREG(VENC_FLEN__FAL); 702 DUMPREG(VENC_LAL__PHASE_RESET); 703 DUMPREG(VENC_HS_INT_START_STOP_X); 704 DUMPREG(VENC_HS_EXT_START_STOP_X); 705 DUMPREG(VENC_VS_INT_START_X); 706 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); 707 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); 708 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 709 DUMPREG(VENC_VS_EXT_STOP_Y); 710 DUMPREG(VENC_AVID_START_STOP_X); 711 DUMPREG(VENC_AVID_START_STOP_Y); 712 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); 713 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 714 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 715 DUMPREG(VENC_TVDETGP_INT_START_STOP_X); 716 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); 717 DUMPREG(VENC_GEN_CTRL); 718 DUMPREG(VENC_OUTPUT_CONTROL); 719 DUMPREG(VENC_OUTPUT_TEST); 720 721 venc_runtime_put(); 722 723 #undef DUMPREG 724 } 725 726 static int venc_get_clocks(struct platform_device *pdev) 727 { 728 struct clk *clk; 729 730 if (venc.requires_tv_dac_clk) { 731 clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); 732 if (IS_ERR(clk)) { 733 DSSERR("can't get tv_dac_clk\n"); 734 return PTR_ERR(clk); 735 } 736 } else { 737 clk = NULL; 738 } 739 740 venc.tv_dac_clk = clk; 741 742 return 0; 743 } 744 745 static int venc_connect(struct omap_dss_device *dssdev, 746 struct omap_dss_device *dst) 747 { 748 enum omap_channel channel = dssdev->dispc_channel; 749 int r; 750 751 r = venc_init_regulator(); 752 if (r) 753 return r; 754 755 r = dss_mgr_connect(channel, dssdev); 756 if (r) 757 return r; 758 759 r = omapdss_output_set_device(dssdev, dst); 760 if (r) { 761 DSSERR("failed to connect output to new device: %s\n", 762 dst->name); 763 dss_mgr_disconnect(channel, dssdev); 764 return r; 765 } 766 767 return 0; 768 } 769 770 static void venc_disconnect(struct omap_dss_device *dssdev, 771 struct omap_dss_device *dst) 772 { 773 enum omap_channel channel = dssdev->dispc_channel; 774 775 WARN_ON(dst != dssdev->dst); 776 777 if (dst != dssdev->dst) 778 return; 779 780 omapdss_output_unset_device(dssdev); 781 782 dss_mgr_disconnect(channel, dssdev); 783 } 784 785 static const struct omapdss_atv_ops venc_ops = { 786 .connect = venc_connect, 787 .disconnect = venc_disconnect, 788 789 .enable = venc_display_enable, 790 .disable = venc_display_disable, 791 792 .check_timings = venc_check_timings, 793 .set_timings = venc_set_timings, 794 .get_timings = venc_get_timings, 795 796 .set_wss = venc_set_wss, 797 .get_wss = venc_get_wss, 798 }; 799 800 static void venc_init_output(struct platform_device *pdev) 801 { 802 struct omap_dss_device *out = &venc.output; 803 804 out->dev = &pdev->dev; 805 out->id = OMAP_DSS_OUTPUT_VENC; 806 out->output_type = OMAP_DISPLAY_TYPE_VENC; 807 out->name = "venc.0"; 808 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 809 out->ops.atv = &venc_ops; 810 out->owner = THIS_MODULE; 811 812 omapdss_register_output(out); 813 } 814 815 static void venc_uninit_output(struct platform_device *pdev) 816 { 817 struct omap_dss_device *out = &venc.output; 818 819 omapdss_unregister_output(out); 820 } 821 822 static int venc_probe_of(struct platform_device *pdev) 823 { 824 struct device_node *node = pdev->dev.of_node; 825 struct device_node *ep; 826 u32 channels; 827 int r; 828 829 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 830 if (!ep) 831 return 0; 832 833 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 834 835 r = of_property_read_u32(ep, "ti,channels", &channels); 836 if (r) { 837 dev_err(&pdev->dev, 838 "failed to read property 'ti,channels': %d\n", r); 839 goto err; 840 } 841 842 switch (channels) { 843 case 1: 844 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; 845 break; 846 case 2: 847 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; 848 break; 849 default: 850 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels); 851 r = -EINVAL; 852 goto err; 853 } 854 855 of_node_put(ep); 856 857 return 0; 858 859 err: 860 of_node_put(ep); 861 return r; 862 } 863 864 /* VENC HW IP initialisation */ 865 static const struct soc_device_attribute venc_soc_devices[] = { 866 { .machine = "OMAP3[45]*" }, 867 { .machine = "AM35*" }, 868 { /* sentinel */ } 869 }; 870 871 static int venc_bind(struct device *dev, struct device *master, void *data) 872 { 873 struct platform_device *pdev = to_platform_device(dev); 874 u8 rev_id; 875 struct resource *venc_mem; 876 int r; 877 878 venc.pdev = pdev; 879 880 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 881 if (soc_device_match(venc_soc_devices)) 882 venc.requires_tv_dac_clk = true; 883 884 mutex_init(&venc.venc_lock); 885 886 venc.wss_data = 0; 887 888 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); 889 venc.base = devm_ioremap_resource(&pdev->dev, venc_mem); 890 if (IS_ERR(venc.base)) 891 return PTR_ERR(venc.base); 892 893 r = venc_get_clocks(pdev); 894 if (r) 895 return r; 896 897 pm_runtime_enable(&pdev->dev); 898 899 r = venc_runtime_get(); 900 if (r) 901 goto err_runtime_get; 902 903 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); 904 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); 905 906 venc_runtime_put(); 907 908 r = venc_probe_of(pdev); 909 if (r) { 910 DSSERR("Invalid DT data\n"); 911 goto err_probe_of; 912 } 913 914 dss_debugfs_create_file("venc", venc_dump_regs); 915 916 venc_init_output(pdev); 917 918 return 0; 919 920 err_probe_of: 921 err_runtime_get: 922 pm_runtime_disable(&pdev->dev); 923 return r; 924 } 925 926 static void venc_unbind(struct device *dev, struct device *master, void *data) 927 { 928 struct platform_device *pdev = to_platform_device(dev); 929 930 venc_uninit_output(pdev); 931 932 pm_runtime_disable(&pdev->dev); 933 } 934 935 static const struct component_ops venc_component_ops = { 936 .bind = venc_bind, 937 .unbind = venc_unbind, 938 }; 939 940 static int venc_probe(struct platform_device *pdev) 941 { 942 return component_add(&pdev->dev, &venc_component_ops); 943 } 944 945 static int venc_remove(struct platform_device *pdev) 946 { 947 component_del(&pdev->dev, &venc_component_ops); 948 return 0; 949 } 950 951 static int venc_runtime_suspend(struct device *dev) 952 { 953 if (venc.tv_dac_clk) 954 clk_disable_unprepare(venc.tv_dac_clk); 955 956 dispc_runtime_put(); 957 958 return 0; 959 } 960 961 static int venc_runtime_resume(struct device *dev) 962 { 963 int r; 964 965 r = dispc_runtime_get(); 966 if (r < 0) 967 return r; 968 969 if (venc.tv_dac_clk) 970 clk_prepare_enable(venc.tv_dac_clk); 971 972 return 0; 973 } 974 975 static const struct dev_pm_ops venc_pm_ops = { 976 .runtime_suspend = venc_runtime_suspend, 977 .runtime_resume = venc_runtime_resume, 978 }; 979 980 static const struct of_device_id venc_of_match[] = { 981 { .compatible = "ti,omap2-venc", }, 982 { .compatible = "ti,omap3-venc", }, 983 { .compatible = "ti,omap4-venc", }, 984 {}, 985 }; 986 987 struct platform_driver omap_venchw_driver = { 988 .probe = venc_probe, 989 .remove = venc_remove, 990 .driver = { 991 .name = "omapdss_venc", 992 .pm = &venc_pm_ops, 993 .of_match_table = venc_of_match, 994 .suppress_bind_attrs = true, 995 }, 996 }; 997