1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * VENC settings from TI's DSS driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "VENC" 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/mutex.h> 28 #include <linux/completion.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/seq_file.h> 32 #include <linux/platform_device.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/of.h> 36 #include <linux/of_graph.h> 37 #include <linux/component.h> 38 #include <linux/sys_soc.h> 39 40 #include "omapdss.h" 41 #include "dss.h" 42 43 /* Venc registers */ 44 #define VENC_REV_ID 0x00 45 #define VENC_STATUS 0x04 46 #define VENC_F_CONTROL 0x08 47 #define VENC_VIDOUT_CTRL 0x10 48 #define VENC_SYNC_CTRL 0x14 49 #define VENC_LLEN 0x1C 50 #define VENC_FLENS 0x20 51 #define VENC_HFLTR_CTRL 0x24 52 #define VENC_CC_CARR_WSS_CARR 0x28 53 #define VENC_C_PHASE 0x2C 54 #define VENC_GAIN_U 0x30 55 #define VENC_GAIN_V 0x34 56 #define VENC_GAIN_Y 0x38 57 #define VENC_BLACK_LEVEL 0x3C 58 #define VENC_BLANK_LEVEL 0x40 59 #define VENC_X_COLOR 0x44 60 #define VENC_M_CONTROL 0x48 61 #define VENC_BSTAMP_WSS_DATA 0x4C 62 #define VENC_S_CARR 0x50 63 #define VENC_LINE21 0x54 64 #define VENC_LN_SEL 0x58 65 #define VENC_L21__WC_CTL 0x5C 66 #define VENC_HTRIGGER_VTRIGGER 0x60 67 #define VENC_SAVID__EAVID 0x64 68 #define VENC_FLEN__FAL 0x68 69 #define VENC_LAL__PHASE_RESET 0x6C 70 #define VENC_HS_INT_START_STOP_X 0x70 71 #define VENC_HS_EXT_START_STOP_X 0x74 72 #define VENC_VS_INT_START_X 0x78 73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 76 #define VENC_VS_EXT_STOP_Y 0x88 77 #define VENC_AVID_START_STOP_X 0x90 78 #define VENC_AVID_START_STOP_Y 0x94 79 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 82 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 83 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 84 #define VENC_GEN_CTRL 0xB8 85 #define VENC_OUTPUT_CONTROL 0xC4 86 #define VENC_OUTPUT_TEST 0xC8 87 #define VENC_DAC_B__DAC_C 0xC8 88 89 struct venc_config { 90 u32 f_control; 91 u32 vidout_ctrl; 92 u32 sync_ctrl; 93 u32 llen; 94 u32 flens; 95 u32 hfltr_ctrl; 96 u32 cc_carr_wss_carr; 97 u32 c_phase; 98 u32 gain_u; 99 u32 gain_v; 100 u32 gain_y; 101 u32 black_level; 102 u32 blank_level; 103 u32 x_color; 104 u32 m_control; 105 u32 bstamp_wss_data; 106 u32 s_carr; 107 u32 line21; 108 u32 ln_sel; 109 u32 l21__wc_ctl; 110 u32 htrigger_vtrigger; 111 u32 savid__eavid; 112 u32 flen__fal; 113 u32 lal__phase_reset; 114 u32 hs_int_start_stop_x; 115 u32 hs_ext_start_stop_x; 116 u32 vs_int_start_x; 117 u32 vs_int_stop_x__vs_int_start_y; 118 u32 vs_int_stop_y__vs_ext_start_x; 119 u32 vs_ext_stop_x__vs_ext_start_y; 120 u32 vs_ext_stop_y; 121 u32 avid_start_stop_x; 122 u32 avid_start_stop_y; 123 u32 fid_int_start_x__fid_int_start_y; 124 u32 fid_int_offset_y__fid_ext_start_x; 125 u32 fid_ext_start_y__fid_ext_offset_y; 126 u32 tvdetgp_int_start_stop_x; 127 u32 tvdetgp_int_start_stop_y; 128 u32 gen_ctrl; 129 }; 130 131 /* from TRM */ 132 static const struct venc_config venc_config_pal_trm = { 133 .f_control = 0, 134 .vidout_ctrl = 1, 135 .sync_ctrl = 0x40, 136 .llen = 0x35F, /* 863 */ 137 .flens = 0x270, /* 624 */ 138 .hfltr_ctrl = 0, 139 .cc_carr_wss_carr = 0x2F7225ED, 140 .c_phase = 0, 141 .gain_u = 0x111, 142 .gain_v = 0x181, 143 .gain_y = 0x140, 144 .black_level = 0x3B, 145 .blank_level = 0x3B, 146 .x_color = 0x7, 147 .m_control = 0x2, 148 .bstamp_wss_data = 0x3F, 149 .s_carr = 0x2A098ACB, 150 .line21 = 0, 151 .ln_sel = 0x01290015, 152 .l21__wc_ctl = 0x0000F603, 153 .htrigger_vtrigger = 0, 154 155 .savid__eavid = 0x06A70108, 156 .flen__fal = 0x00180270, 157 .lal__phase_reset = 0x00040135, 158 .hs_int_start_stop_x = 0x00880358, 159 .hs_ext_start_stop_x = 0x000F035F, 160 .vs_int_start_x = 0x01A70000, 161 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 164 .vs_ext_stop_y = 0x00000025, 165 .avid_start_stop_x = 0x03530083, 166 .avid_start_stop_y = 0x026C002E, 167 .fid_int_start_x__fid_int_start_y = 0x0001008A, 168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 170 171 .tvdetgp_int_start_stop_x = 0x00140001, 172 .tvdetgp_int_start_stop_y = 0x00010001, 173 .gen_ctrl = 0x00FF0000, 174 }; 175 176 /* from TRM */ 177 static const struct venc_config venc_config_ntsc_trm = { 178 .f_control = 0, 179 .vidout_ctrl = 1, 180 .sync_ctrl = 0x8040, 181 .llen = 0x359, 182 .flens = 0x20C, 183 .hfltr_ctrl = 0, 184 .cc_carr_wss_carr = 0x043F2631, 185 .c_phase = 0, 186 .gain_u = 0x102, 187 .gain_v = 0x16C, 188 .gain_y = 0x12F, 189 .black_level = 0x43, 190 .blank_level = 0x38, 191 .x_color = 0x7, 192 .m_control = 0x1, 193 .bstamp_wss_data = 0x38, 194 .s_carr = 0x21F07C1F, 195 .line21 = 0, 196 .ln_sel = 0x01310011, 197 .l21__wc_ctl = 0x0000F003, 198 .htrigger_vtrigger = 0, 199 200 .savid__eavid = 0x069300F4, 201 .flen__fal = 0x0016020C, 202 .lal__phase_reset = 0x00060107, 203 .hs_int_start_stop_x = 0x008E0350, 204 .hs_ext_start_stop_x = 0x000F0359, 205 .vs_int_start_x = 0x01A00000, 206 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 209 .vs_ext_stop_y = 0x00000006, 210 .avid_start_stop_x = 0x03480078, 211 .avid_start_stop_y = 0x02060024, 212 .fid_int_start_x__fid_int_start_y = 0x0001008A, 213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 215 216 .tvdetgp_int_start_stop_x = 0x00140001, 217 .tvdetgp_int_start_stop_y = 0x00010001, 218 .gen_ctrl = 0x00F90000, 219 }; 220 221 static const struct venc_config venc_config_pal_bdghi = { 222 .f_control = 0, 223 .vidout_ctrl = 0, 224 .sync_ctrl = 0, 225 .hfltr_ctrl = 0, 226 .x_color = 0, 227 .line21 = 0, 228 .ln_sel = 21, 229 .htrigger_vtrigger = 0, 230 .tvdetgp_int_start_stop_x = 0x00140001, 231 .tvdetgp_int_start_stop_y = 0x00010001, 232 .gen_ctrl = 0x00FB0000, 233 234 .llen = 864-1, 235 .flens = 625-1, 236 .cc_carr_wss_carr = 0x2F7625ED, 237 .c_phase = 0xDF, 238 .gain_u = 0x111, 239 .gain_v = 0x181, 240 .gain_y = 0x140, 241 .black_level = 0x3e, 242 .blank_level = 0x3e, 243 .m_control = 0<<2 | 1<<1, 244 .bstamp_wss_data = 0x42, 245 .s_carr = 0x2a098acb, 246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, 247 .savid__eavid = 0x06A70108, 248 .flen__fal = 23<<16 | 624<<0, 249 .lal__phase_reset = 2<<17 | 310<<0, 250 .hs_int_start_stop_x = 0x00920358, 251 .hs_ext_start_stop_x = 0x000F035F, 252 .vs_int_start_x = 0x1a7<<16, 253 .vs_int_stop_x__vs_int_start_y = 0x000601A7, 254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, 255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af, 256 .vs_ext_stop_y = 0x05, 257 .avid_start_stop_x = 0x03530082, 258 .avid_start_stop_y = 0x0270002E, 259 .fid_int_start_x__fid_int_start_y = 0x0005008A, 260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 }; 263 264 enum venc_videomode { 265 VENC_MODE_UNKNOWN, 266 VENC_MODE_PAL, 267 VENC_MODE_NTSC, 268 }; 269 270 static const struct drm_display_mode omap_dss_pal_mode = { 271 .hdisplay = 720, 272 .hsync_start = 732, 273 .hsync_end = 796, 274 .htotal = 864, 275 .vdisplay = 574, 276 .vsync_start = 579, 277 .vsync_end = 584, 278 .vtotal = 625, 279 .clock = 13500, 280 281 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC | 282 DRM_MODE_FLAG_NVSYNC, 283 }; 284 285 static const struct drm_display_mode omap_dss_ntsc_mode = { 286 .hdisplay = 720, 287 .hsync_start = 736, 288 .hsync_end = 800, 289 .htotal = 858, 290 .vdisplay = 482, 291 .vsync_start = 488, 292 .vsync_end = 494, 293 .vtotal = 525, 294 .clock = 13500, 295 296 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC | 297 DRM_MODE_FLAG_NVSYNC, 298 }; 299 300 struct venc_device { 301 struct platform_device *pdev; 302 void __iomem *base; 303 struct mutex venc_lock; 304 struct regulator *vdda_dac_reg; 305 struct dss_device *dss; 306 307 struct dss_debugfs_entry *debugfs; 308 309 struct clk *tv_dac_clk; 310 311 const struct venc_config *config; 312 enum omap_dss_venc_type type; 313 bool invert_polarity; 314 bool requires_tv_dac_clk; 315 316 struct omap_dss_device output; 317 }; 318 319 #define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output) 320 321 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val) 322 { 323 __raw_writel(val, venc->base + idx); 324 } 325 326 static inline u32 venc_read_reg(struct venc_device *venc, int idx) 327 { 328 u32 l = __raw_readl(venc->base + idx); 329 return l; 330 } 331 332 static void venc_write_config(struct venc_device *venc, 333 const struct venc_config *config) 334 { 335 DSSDBG("write venc conf\n"); 336 337 venc_write_reg(venc, VENC_LLEN, config->llen); 338 venc_write_reg(venc, VENC_FLENS, config->flens); 339 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 340 venc_write_reg(venc, VENC_C_PHASE, config->c_phase); 341 venc_write_reg(venc, VENC_GAIN_U, config->gain_u); 342 venc_write_reg(venc, VENC_GAIN_V, config->gain_v); 343 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y); 344 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level); 345 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level); 346 venc_write_reg(venc, VENC_M_CONTROL, config->m_control); 347 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data); 348 venc_write_reg(venc, VENC_S_CARR, config->s_carr); 349 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl); 350 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid); 351 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal); 352 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset); 353 venc_write_reg(venc, VENC_HS_INT_START_STOP_X, 354 config->hs_int_start_stop_x); 355 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X, 356 config->hs_ext_start_stop_x); 357 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x); 358 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y, 359 config->vs_int_stop_x__vs_int_start_y); 360 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X, 361 config->vs_int_stop_y__vs_ext_start_x); 362 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 363 config->vs_ext_stop_x__vs_ext_start_y); 364 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 365 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x); 366 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 367 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y, 368 config->fid_int_start_x__fid_int_start_y); 369 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 370 config->fid_int_offset_y__fid_ext_start_x); 371 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 372 config->fid_ext_start_y__fid_ext_offset_y); 373 374 venc_write_reg(venc, VENC_DAC_B__DAC_C, 375 venc_read_reg(venc, VENC_DAC_B__DAC_C)); 376 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl); 377 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl); 378 venc_write_reg(venc, VENC_X_COLOR, config->x_color); 379 venc_write_reg(venc, VENC_LINE21, config->line21); 380 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel); 381 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 382 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X, 383 config->tvdetgp_int_start_stop_x); 384 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y, 385 config->tvdetgp_int_start_stop_y); 386 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl); 387 venc_write_reg(venc, VENC_F_CONTROL, config->f_control); 388 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl); 389 } 390 391 static void venc_reset(struct venc_device *venc) 392 { 393 int t = 1000; 394 395 venc_write_reg(venc, VENC_F_CONTROL, 1<<8); 396 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) { 397 if (--t == 0) { 398 DSSERR("Failed to reset venc\n"); 399 return; 400 } 401 } 402 403 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 404 /* the magical sleep that makes things work */ 405 /* XXX more info? What bug this circumvents? */ 406 msleep(20); 407 #endif 408 } 409 410 static int venc_runtime_get(struct venc_device *venc) 411 { 412 int r; 413 414 DSSDBG("venc_runtime_get\n"); 415 416 r = pm_runtime_get_sync(&venc->pdev->dev); 417 WARN_ON(r < 0); 418 return r < 0 ? r : 0; 419 } 420 421 static void venc_runtime_put(struct venc_device *venc) 422 { 423 int r; 424 425 DSSDBG("venc_runtime_put\n"); 426 427 r = pm_runtime_put_sync(&venc->pdev->dev); 428 WARN_ON(r < 0 && r != -ENOSYS); 429 } 430 431 static int venc_power_on(struct venc_device *venc) 432 { 433 u32 l; 434 int r; 435 436 r = venc_runtime_get(venc); 437 if (r) 438 goto err0; 439 440 venc_reset(venc); 441 venc_write_config(venc, venc->config); 442 443 dss_set_venc_output(venc->dss, venc->type); 444 dss_set_dac_pwrdn_bgz(venc->dss, 1); 445 446 l = 0; 447 448 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE) 449 l |= 1 << 1; 450 else /* S-Video */ 451 l |= (1 << 0) | (1 << 2); 452 453 if (venc->invert_polarity == false) 454 l |= 1 << 3; 455 456 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l); 457 458 r = regulator_enable(venc->vdda_dac_reg); 459 if (r) 460 goto err1; 461 462 r = dss_mgr_enable(&venc->output); 463 if (r) 464 goto err2; 465 466 return 0; 467 468 err2: 469 regulator_disable(venc->vdda_dac_reg); 470 err1: 471 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 472 dss_set_dac_pwrdn_bgz(venc->dss, 0); 473 474 venc_runtime_put(venc); 475 err0: 476 return r; 477 } 478 479 static void venc_power_off(struct venc_device *venc) 480 { 481 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 482 dss_set_dac_pwrdn_bgz(venc->dss, 0); 483 484 dss_mgr_disable(&venc->output); 485 486 regulator_disable(venc->vdda_dac_reg); 487 488 venc_runtime_put(venc); 489 } 490 491 static void venc_display_enable(struct omap_dss_device *dssdev) 492 { 493 struct venc_device *venc = dssdev_to_venc(dssdev); 494 495 DSSDBG("venc_display_enable\n"); 496 497 mutex_lock(&venc->venc_lock); 498 499 venc_power_on(venc); 500 501 mutex_unlock(&venc->venc_lock); 502 } 503 504 static void venc_display_disable(struct omap_dss_device *dssdev) 505 { 506 struct venc_device *venc = dssdev_to_venc(dssdev); 507 508 DSSDBG("venc_display_disable\n"); 509 510 mutex_lock(&venc->venc_lock); 511 512 venc_power_off(venc); 513 514 mutex_unlock(&venc->venc_lock); 515 } 516 517 static int venc_get_modes(struct omap_dss_device *dssdev, 518 struct drm_connector *connector) 519 { 520 static const struct drm_display_mode *modes[] = { 521 &omap_dss_pal_mode, 522 &omap_dss_ntsc_mode, 523 }; 524 unsigned int i; 525 526 for (i = 0; i < ARRAY_SIZE(modes); ++i) { 527 struct drm_display_mode *mode; 528 529 mode = drm_mode_duplicate(connector->dev, modes[i]); 530 if (!mode) 531 return i; 532 533 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 534 drm_mode_set_name(mode); 535 drm_mode_probed_add(connector, mode); 536 } 537 538 return ARRAY_SIZE(modes); 539 } 540 541 static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode) 542 { 543 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 544 return VENC_MODE_UNKNOWN; 545 546 if (mode->clock == omap_dss_pal_mode.clock && 547 mode->hdisplay == omap_dss_pal_mode.hdisplay && 548 mode->vdisplay == omap_dss_pal_mode.vdisplay) 549 return VENC_MODE_PAL; 550 551 if (mode->clock == omap_dss_ntsc_mode.clock && 552 mode->hdisplay == omap_dss_ntsc_mode.hdisplay && 553 mode->vdisplay == omap_dss_ntsc_mode.vdisplay) 554 return VENC_MODE_NTSC; 555 556 return VENC_MODE_UNKNOWN; 557 } 558 559 static void venc_set_timings(struct omap_dss_device *dssdev, 560 const struct drm_display_mode *mode) 561 { 562 struct venc_device *venc = dssdev_to_venc(dssdev); 563 enum venc_videomode venc_mode = venc_get_videomode(mode); 564 565 DSSDBG("venc_set_timings\n"); 566 567 mutex_lock(&venc->venc_lock); 568 569 switch (venc_mode) { 570 default: 571 WARN_ON_ONCE(1); 572 /* Fall-through */ 573 case VENC_MODE_PAL: 574 venc->config = &venc_config_pal_trm; 575 break; 576 577 case VENC_MODE_NTSC: 578 venc->config = &venc_config_ntsc_trm; 579 break; 580 } 581 582 dispc_set_tv_pclk(venc->dss->dispc, 13500000); 583 584 mutex_unlock(&venc->venc_lock); 585 } 586 587 static int venc_check_timings(struct omap_dss_device *dssdev, 588 struct drm_display_mode *mode) 589 { 590 DSSDBG("venc_check_timings\n"); 591 592 switch (venc_get_videomode(mode)) { 593 case VENC_MODE_PAL: 594 drm_mode_copy(mode, &omap_dss_pal_mode); 595 break; 596 597 case VENC_MODE_NTSC: 598 drm_mode_copy(mode, &omap_dss_ntsc_mode); 599 break; 600 601 default: 602 return -EINVAL; 603 } 604 605 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); 606 drm_mode_set_name(mode); 607 return 0; 608 } 609 610 static int venc_dump_regs(struct seq_file *s, void *p) 611 { 612 struct venc_device *venc = s->private; 613 614 #define DUMPREG(venc, r) \ 615 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r)) 616 617 if (venc_runtime_get(venc)) 618 return 0; 619 620 DUMPREG(venc, VENC_F_CONTROL); 621 DUMPREG(venc, VENC_VIDOUT_CTRL); 622 DUMPREG(venc, VENC_SYNC_CTRL); 623 DUMPREG(venc, VENC_LLEN); 624 DUMPREG(venc, VENC_FLENS); 625 DUMPREG(venc, VENC_HFLTR_CTRL); 626 DUMPREG(venc, VENC_CC_CARR_WSS_CARR); 627 DUMPREG(venc, VENC_C_PHASE); 628 DUMPREG(venc, VENC_GAIN_U); 629 DUMPREG(venc, VENC_GAIN_V); 630 DUMPREG(venc, VENC_GAIN_Y); 631 DUMPREG(venc, VENC_BLACK_LEVEL); 632 DUMPREG(venc, VENC_BLANK_LEVEL); 633 DUMPREG(venc, VENC_X_COLOR); 634 DUMPREG(venc, VENC_M_CONTROL); 635 DUMPREG(venc, VENC_BSTAMP_WSS_DATA); 636 DUMPREG(venc, VENC_S_CARR); 637 DUMPREG(venc, VENC_LINE21); 638 DUMPREG(venc, VENC_LN_SEL); 639 DUMPREG(venc, VENC_L21__WC_CTL); 640 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER); 641 DUMPREG(venc, VENC_SAVID__EAVID); 642 DUMPREG(venc, VENC_FLEN__FAL); 643 DUMPREG(venc, VENC_LAL__PHASE_RESET); 644 DUMPREG(venc, VENC_HS_INT_START_STOP_X); 645 DUMPREG(venc, VENC_HS_EXT_START_STOP_X); 646 DUMPREG(venc, VENC_VS_INT_START_X); 647 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y); 648 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X); 649 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 650 DUMPREG(venc, VENC_VS_EXT_STOP_Y); 651 DUMPREG(venc, VENC_AVID_START_STOP_X); 652 DUMPREG(venc, VENC_AVID_START_STOP_Y); 653 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y); 654 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 655 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 656 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X); 657 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y); 658 DUMPREG(venc, VENC_GEN_CTRL); 659 DUMPREG(venc, VENC_OUTPUT_CONTROL); 660 DUMPREG(venc, VENC_OUTPUT_TEST); 661 662 venc_runtime_put(venc); 663 664 #undef DUMPREG 665 return 0; 666 } 667 668 static int venc_get_clocks(struct venc_device *venc) 669 { 670 struct clk *clk; 671 672 if (venc->requires_tv_dac_clk) { 673 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk"); 674 if (IS_ERR(clk)) { 675 DSSERR("can't get tv_dac_clk\n"); 676 return PTR_ERR(clk); 677 } 678 } else { 679 clk = NULL; 680 } 681 682 venc->tv_dac_clk = clk; 683 684 return 0; 685 } 686 687 static int venc_connect(struct omap_dss_device *src, 688 struct omap_dss_device *dst) 689 { 690 return omapdss_device_connect(dst->dss, dst, dst->next); 691 } 692 693 static void venc_disconnect(struct omap_dss_device *src, 694 struct omap_dss_device *dst) 695 { 696 omapdss_device_disconnect(dst, dst->next); 697 } 698 699 static const struct omap_dss_device_ops venc_ops = { 700 .connect = venc_connect, 701 .disconnect = venc_disconnect, 702 703 .enable = venc_display_enable, 704 .disable = venc_display_disable, 705 706 .check_timings = venc_check_timings, 707 .set_timings = venc_set_timings, 708 709 .get_modes = venc_get_modes, 710 }; 711 712 /* ----------------------------------------------------------------------------- 713 * Component Bind & Unbind 714 */ 715 716 static int venc_bind(struct device *dev, struct device *master, void *data) 717 { 718 struct dss_device *dss = dss_get_device(master); 719 struct venc_device *venc = dev_get_drvdata(dev); 720 u8 rev_id; 721 int r; 722 723 venc->dss = dss; 724 725 r = venc_runtime_get(venc); 726 if (r) 727 return r; 728 729 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff); 730 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id); 731 732 venc_runtime_put(venc); 733 734 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs, 735 venc); 736 737 return 0; 738 } 739 740 static void venc_unbind(struct device *dev, struct device *master, void *data) 741 { 742 struct venc_device *venc = dev_get_drvdata(dev); 743 744 dss_debugfs_remove_file(venc->debugfs); 745 } 746 747 static const struct component_ops venc_component_ops = { 748 .bind = venc_bind, 749 .unbind = venc_unbind, 750 }; 751 752 /* ----------------------------------------------------------------------------- 753 * Probe & Remove, Suspend & Resume 754 */ 755 756 static int venc_init_output(struct venc_device *venc) 757 { 758 struct omap_dss_device *out = &venc->output; 759 int r; 760 761 out->dev = &venc->pdev->dev; 762 out->id = OMAP_DSS_OUTPUT_VENC; 763 out->type = OMAP_DISPLAY_TYPE_VENC; 764 out->name = "venc.0"; 765 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 766 out->ops = &venc_ops; 767 out->owner = THIS_MODULE; 768 out->of_ports = BIT(0); 769 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES; 770 771 r = omapdss_device_init_output(out); 772 if (r < 0) 773 return r; 774 775 omapdss_device_register(out); 776 777 return 0; 778 } 779 780 static void venc_uninit_output(struct venc_device *venc) 781 { 782 omapdss_device_unregister(&venc->output); 783 omapdss_device_cleanup_output(&venc->output); 784 } 785 786 static int venc_probe_of(struct venc_device *venc) 787 { 788 struct device_node *node = venc->pdev->dev.of_node; 789 struct device_node *ep; 790 u32 channels; 791 int r; 792 793 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 794 if (!ep) 795 return 0; 796 797 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 798 799 r = of_property_read_u32(ep, "ti,channels", &channels); 800 if (r) { 801 dev_err(&venc->pdev->dev, 802 "failed to read property 'ti,channels': %d\n", r); 803 goto err; 804 } 805 806 switch (channels) { 807 case 1: 808 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE; 809 break; 810 case 2: 811 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO; 812 break; 813 default: 814 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n", 815 channels); 816 r = -EINVAL; 817 goto err; 818 } 819 820 of_node_put(ep); 821 822 return 0; 823 824 err: 825 of_node_put(ep); 826 return r; 827 } 828 829 static const struct soc_device_attribute venc_soc_devices[] = { 830 { .machine = "OMAP3[45]*" }, 831 { .machine = "AM35*" }, 832 { /* sentinel */ } 833 }; 834 835 static int venc_probe(struct platform_device *pdev) 836 { 837 struct venc_device *venc; 838 struct resource *venc_mem; 839 int r; 840 841 venc = kzalloc(sizeof(*venc), GFP_KERNEL); 842 if (!venc) 843 return -ENOMEM; 844 845 venc->pdev = pdev; 846 847 platform_set_drvdata(pdev, venc); 848 849 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 850 if (soc_device_match(venc_soc_devices)) 851 venc->requires_tv_dac_clk = true; 852 853 mutex_init(&venc->venc_lock); 854 855 venc->config = &venc_config_pal_trm; 856 857 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0); 858 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem); 859 if (IS_ERR(venc->base)) { 860 r = PTR_ERR(venc->base); 861 goto err_free; 862 } 863 864 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda"); 865 if (IS_ERR(venc->vdda_dac_reg)) { 866 r = PTR_ERR(venc->vdda_dac_reg); 867 if (r != -EPROBE_DEFER) 868 DSSERR("can't get VDDA_DAC regulator\n"); 869 goto err_free; 870 } 871 872 r = venc_get_clocks(venc); 873 if (r) 874 goto err_free; 875 876 r = venc_probe_of(venc); 877 if (r) 878 goto err_free; 879 880 pm_runtime_enable(&pdev->dev); 881 882 r = venc_init_output(venc); 883 if (r) 884 goto err_pm_disable; 885 886 r = component_add(&pdev->dev, &venc_component_ops); 887 if (r) 888 goto err_uninit_output; 889 890 return 0; 891 892 err_uninit_output: 893 venc_uninit_output(venc); 894 err_pm_disable: 895 pm_runtime_disable(&pdev->dev); 896 err_free: 897 kfree(venc); 898 return r; 899 } 900 901 static int venc_remove(struct platform_device *pdev) 902 { 903 struct venc_device *venc = platform_get_drvdata(pdev); 904 905 component_del(&pdev->dev, &venc_component_ops); 906 907 venc_uninit_output(venc); 908 909 pm_runtime_disable(&pdev->dev); 910 911 kfree(venc); 912 return 0; 913 } 914 915 static int venc_runtime_suspend(struct device *dev) 916 { 917 struct venc_device *venc = dev_get_drvdata(dev); 918 919 if (venc->tv_dac_clk) 920 clk_disable_unprepare(venc->tv_dac_clk); 921 922 return 0; 923 } 924 925 static int venc_runtime_resume(struct device *dev) 926 { 927 struct venc_device *venc = dev_get_drvdata(dev); 928 929 if (venc->tv_dac_clk) 930 clk_prepare_enable(venc->tv_dac_clk); 931 932 return 0; 933 } 934 935 static const struct dev_pm_ops venc_pm_ops = { 936 .runtime_suspend = venc_runtime_suspend, 937 .runtime_resume = venc_runtime_resume, 938 }; 939 940 static const struct of_device_id venc_of_match[] = { 941 { .compatible = "ti,omap2-venc", }, 942 { .compatible = "ti,omap3-venc", }, 943 { .compatible = "ti,omap4-venc", }, 944 {}, 945 }; 946 947 struct platform_driver omap_venchw_driver = { 948 .probe = venc_probe, 949 .remove = venc_remove, 950 .driver = { 951 .name = "omapdss_venc", 952 .pm = &venc_pm_ops, 953 .of_match_table = venc_of_match, 954 .suppress_bind_attrs = true, 955 }, 956 }; 957