1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 * 6 * VENC settings from TI's DSS driver 7 */ 8 9 #define DSS_SUBSYS_NAME "VENC" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/clk.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/string.h> 19 #include <linux/seq_file.h> 20 #include <linux/platform_device.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_graph.h> 25 #include <linux/component.h> 26 #include <linux/sys_soc.h> 27 28 #include <drm/drm_bridge.h> 29 30 #include "omapdss.h" 31 #include "dss.h" 32 33 /* Venc registers */ 34 #define VENC_REV_ID 0x00 35 #define VENC_STATUS 0x04 36 #define VENC_F_CONTROL 0x08 37 #define VENC_VIDOUT_CTRL 0x10 38 #define VENC_SYNC_CTRL 0x14 39 #define VENC_LLEN 0x1C 40 #define VENC_FLENS 0x20 41 #define VENC_HFLTR_CTRL 0x24 42 #define VENC_CC_CARR_WSS_CARR 0x28 43 #define VENC_C_PHASE 0x2C 44 #define VENC_GAIN_U 0x30 45 #define VENC_GAIN_V 0x34 46 #define VENC_GAIN_Y 0x38 47 #define VENC_BLACK_LEVEL 0x3C 48 #define VENC_BLANK_LEVEL 0x40 49 #define VENC_X_COLOR 0x44 50 #define VENC_M_CONTROL 0x48 51 #define VENC_BSTAMP_WSS_DATA 0x4C 52 #define VENC_S_CARR 0x50 53 #define VENC_LINE21 0x54 54 #define VENC_LN_SEL 0x58 55 #define VENC_L21__WC_CTL 0x5C 56 #define VENC_HTRIGGER_VTRIGGER 0x60 57 #define VENC_SAVID__EAVID 0x64 58 #define VENC_FLEN__FAL 0x68 59 #define VENC_LAL__PHASE_RESET 0x6C 60 #define VENC_HS_INT_START_STOP_X 0x70 61 #define VENC_HS_EXT_START_STOP_X 0x74 62 #define VENC_VS_INT_START_X 0x78 63 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 64 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 65 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 66 #define VENC_VS_EXT_STOP_Y 0x88 67 #define VENC_AVID_START_STOP_X 0x90 68 #define VENC_AVID_START_STOP_Y 0x94 69 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 70 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 71 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 72 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 73 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 74 #define VENC_GEN_CTRL 0xB8 75 #define VENC_OUTPUT_CONTROL 0xC4 76 #define VENC_OUTPUT_TEST 0xC8 77 #define VENC_DAC_B__DAC_C 0xC8 78 79 struct venc_config { 80 u32 f_control; 81 u32 vidout_ctrl; 82 u32 sync_ctrl; 83 u32 llen; 84 u32 flens; 85 u32 hfltr_ctrl; 86 u32 cc_carr_wss_carr; 87 u32 c_phase; 88 u32 gain_u; 89 u32 gain_v; 90 u32 gain_y; 91 u32 black_level; 92 u32 blank_level; 93 u32 x_color; 94 u32 m_control; 95 u32 bstamp_wss_data; 96 u32 s_carr; 97 u32 line21; 98 u32 ln_sel; 99 u32 l21__wc_ctl; 100 u32 htrigger_vtrigger; 101 u32 savid__eavid; 102 u32 flen__fal; 103 u32 lal__phase_reset; 104 u32 hs_int_start_stop_x; 105 u32 hs_ext_start_stop_x; 106 u32 vs_int_start_x; 107 u32 vs_int_stop_x__vs_int_start_y; 108 u32 vs_int_stop_y__vs_ext_start_x; 109 u32 vs_ext_stop_x__vs_ext_start_y; 110 u32 vs_ext_stop_y; 111 u32 avid_start_stop_x; 112 u32 avid_start_stop_y; 113 u32 fid_int_start_x__fid_int_start_y; 114 u32 fid_int_offset_y__fid_ext_start_x; 115 u32 fid_ext_start_y__fid_ext_offset_y; 116 u32 tvdetgp_int_start_stop_x; 117 u32 tvdetgp_int_start_stop_y; 118 u32 gen_ctrl; 119 }; 120 121 /* from TRM */ 122 static const struct venc_config venc_config_pal_trm = { 123 .f_control = 0, 124 .vidout_ctrl = 1, 125 .sync_ctrl = 0x40, 126 .llen = 0x35F, /* 863 */ 127 .flens = 0x270, /* 624 */ 128 .hfltr_ctrl = 0, 129 .cc_carr_wss_carr = 0x2F7225ED, 130 .c_phase = 0, 131 .gain_u = 0x111, 132 .gain_v = 0x181, 133 .gain_y = 0x140, 134 .black_level = 0x3B, 135 .blank_level = 0x3B, 136 .x_color = 0x7, 137 .m_control = 0x2, 138 .bstamp_wss_data = 0x3F, 139 .s_carr = 0x2A098ACB, 140 .line21 = 0, 141 .ln_sel = 0x01290015, 142 .l21__wc_ctl = 0x0000F603, 143 .htrigger_vtrigger = 0, 144 145 .savid__eavid = 0x06A70108, 146 .flen__fal = 0x00180270, 147 .lal__phase_reset = 0x00040135, 148 .hs_int_start_stop_x = 0x00880358, 149 .hs_ext_start_stop_x = 0x000F035F, 150 .vs_int_start_x = 0x01A70000, 151 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 152 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 153 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 154 .vs_ext_stop_y = 0x00000025, 155 .avid_start_stop_x = 0x03530083, 156 .avid_start_stop_y = 0x026C002E, 157 .fid_int_start_x__fid_int_start_y = 0x0001008A, 158 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 159 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 160 161 .tvdetgp_int_start_stop_x = 0x00140001, 162 .tvdetgp_int_start_stop_y = 0x00010001, 163 .gen_ctrl = 0x00FF0000, 164 }; 165 166 /* from TRM */ 167 static const struct venc_config venc_config_ntsc_trm = { 168 .f_control = 0, 169 .vidout_ctrl = 1, 170 .sync_ctrl = 0x8040, 171 .llen = 0x359, 172 .flens = 0x20C, 173 .hfltr_ctrl = 0, 174 .cc_carr_wss_carr = 0x043F2631, 175 .c_phase = 0, 176 .gain_u = 0x102, 177 .gain_v = 0x16C, 178 .gain_y = 0x12F, 179 .black_level = 0x43, 180 .blank_level = 0x38, 181 .x_color = 0x7, 182 .m_control = 0x1, 183 .bstamp_wss_data = 0x38, 184 .s_carr = 0x21F07C1F, 185 .line21 = 0, 186 .ln_sel = 0x01310011, 187 .l21__wc_ctl = 0x0000F003, 188 .htrigger_vtrigger = 0, 189 190 .savid__eavid = 0x069300F4, 191 .flen__fal = 0x0016020C, 192 .lal__phase_reset = 0x00060107, 193 .hs_int_start_stop_x = 0x008E0350, 194 .hs_ext_start_stop_x = 0x000F0359, 195 .vs_int_start_x = 0x01A00000, 196 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 197 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 198 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 199 .vs_ext_stop_y = 0x00000006, 200 .avid_start_stop_x = 0x03480078, 201 .avid_start_stop_y = 0x02060024, 202 .fid_int_start_x__fid_int_start_y = 0x0001008A, 203 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 204 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 205 206 .tvdetgp_int_start_stop_x = 0x00140001, 207 .tvdetgp_int_start_stop_y = 0x00010001, 208 .gen_ctrl = 0x00F90000, 209 }; 210 211 enum venc_videomode { 212 VENC_MODE_UNKNOWN, 213 VENC_MODE_PAL, 214 VENC_MODE_NTSC, 215 }; 216 217 static const struct drm_display_mode omap_dss_pal_mode = { 218 .hdisplay = 720, 219 .hsync_start = 732, 220 .hsync_end = 796, 221 .htotal = 864, 222 .vdisplay = 574, 223 .vsync_start = 579, 224 .vsync_end = 584, 225 .vtotal = 625, 226 .clock = 13500, 227 228 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC | 229 DRM_MODE_FLAG_NVSYNC, 230 }; 231 232 static const struct drm_display_mode omap_dss_ntsc_mode = { 233 .hdisplay = 720, 234 .hsync_start = 736, 235 .hsync_end = 800, 236 .htotal = 858, 237 .vdisplay = 482, 238 .vsync_start = 488, 239 .vsync_end = 494, 240 .vtotal = 525, 241 .clock = 13500, 242 243 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC | 244 DRM_MODE_FLAG_NVSYNC, 245 }; 246 247 struct venc_device { 248 struct platform_device *pdev; 249 void __iomem *base; 250 struct regulator *vdda_dac_reg; 251 struct dss_device *dss; 252 253 struct dss_debugfs_entry *debugfs; 254 255 struct clk *tv_dac_clk; 256 257 const struct venc_config *config; 258 enum omap_dss_venc_type type; 259 bool invert_polarity; 260 bool requires_tv_dac_clk; 261 262 struct omap_dss_device output; 263 struct drm_bridge bridge; 264 }; 265 266 #define drm_bridge_to_venc(b) container_of(b, struct venc_device, bridge) 267 268 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val) 269 { 270 __raw_writel(val, venc->base + idx); 271 } 272 273 static inline u32 venc_read_reg(struct venc_device *venc, int idx) 274 { 275 u32 l = __raw_readl(venc->base + idx); 276 return l; 277 } 278 279 static void venc_write_config(struct venc_device *venc, 280 const struct venc_config *config) 281 { 282 DSSDBG("write venc conf\n"); 283 284 venc_write_reg(venc, VENC_LLEN, config->llen); 285 venc_write_reg(venc, VENC_FLENS, config->flens); 286 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 287 venc_write_reg(venc, VENC_C_PHASE, config->c_phase); 288 venc_write_reg(venc, VENC_GAIN_U, config->gain_u); 289 venc_write_reg(venc, VENC_GAIN_V, config->gain_v); 290 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y); 291 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level); 292 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level); 293 venc_write_reg(venc, VENC_M_CONTROL, config->m_control); 294 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data); 295 venc_write_reg(venc, VENC_S_CARR, config->s_carr); 296 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl); 297 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid); 298 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal); 299 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset); 300 venc_write_reg(venc, VENC_HS_INT_START_STOP_X, 301 config->hs_int_start_stop_x); 302 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X, 303 config->hs_ext_start_stop_x); 304 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x); 305 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y, 306 config->vs_int_stop_x__vs_int_start_y); 307 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X, 308 config->vs_int_stop_y__vs_ext_start_x); 309 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 310 config->vs_ext_stop_x__vs_ext_start_y); 311 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 312 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x); 313 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 314 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y, 315 config->fid_int_start_x__fid_int_start_y); 316 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 317 config->fid_int_offset_y__fid_ext_start_x); 318 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 319 config->fid_ext_start_y__fid_ext_offset_y); 320 321 venc_write_reg(venc, VENC_DAC_B__DAC_C, 322 venc_read_reg(venc, VENC_DAC_B__DAC_C)); 323 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl); 324 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl); 325 venc_write_reg(venc, VENC_X_COLOR, config->x_color); 326 venc_write_reg(venc, VENC_LINE21, config->line21); 327 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel); 328 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 329 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X, 330 config->tvdetgp_int_start_stop_x); 331 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y, 332 config->tvdetgp_int_start_stop_y); 333 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl); 334 venc_write_reg(venc, VENC_F_CONTROL, config->f_control); 335 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl); 336 } 337 338 static void venc_reset(struct venc_device *venc) 339 { 340 int t = 1000; 341 342 venc_write_reg(venc, VENC_F_CONTROL, 1<<8); 343 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) { 344 if (--t == 0) { 345 DSSERR("Failed to reset venc\n"); 346 return; 347 } 348 } 349 350 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 351 /* the magical sleep that makes things work */ 352 /* XXX more info? What bug this circumvents? */ 353 msleep(20); 354 #endif 355 } 356 357 static int venc_runtime_get(struct venc_device *venc) 358 { 359 int r; 360 361 DSSDBG("venc_runtime_get\n"); 362 363 r = pm_runtime_get_sync(&venc->pdev->dev); 364 WARN_ON(r < 0); 365 return r < 0 ? r : 0; 366 } 367 368 static void venc_runtime_put(struct venc_device *venc) 369 { 370 int r; 371 372 DSSDBG("venc_runtime_put\n"); 373 374 r = pm_runtime_put_sync(&venc->pdev->dev); 375 WARN_ON(r < 0 && r != -ENOSYS); 376 } 377 378 static int venc_power_on(struct venc_device *venc) 379 { 380 u32 l; 381 int r; 382 383 r = venc_runtime_get(venc); 384 if (r) 385 goto err0; 386 387 venc_reset(venc); 388 venc_write_config(venc, venc->config); 389 390 dss_set_venc_output(venc->dss, venc->type); 391 dss_set_dac_pwrdn_bgz(venc->dss, 1); 392 393 l = 0; 394 395 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE) 396 l |= 1 << 1; 397 else /* S-Video */ 398 l |= (1 << 0) | (1 << 2); 399 400 if (venc->invert_polarity == false) 401 l |= 1 << 3; 402 403 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l); 404 405 r = regulator_enable(venc->vdda_dac_reg); 406 if (r) 407 goto err1; 408 409 r = dss_mgr_enable(&venc->output); 410 if (r) 411 goto err2; 412 413 return 0; 414 415 err2: 416 regulator_disable(venc->vdda_dac_reg); 417 err1: 418 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 419 dss_set_dac_pwrdn_bgz(venc->dss, 0); 420 421 venc_runtime_put(venc); 422 err0: 423 return r; 424 } 425 426 static void venc_power_off(struct venc_device *venc) 427 { 428 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 429 dss_set_dac_pwrdn_bgz(venc->dss, 0); 430 431 dss_mgr_disable(&venc->output); 432 433 regulator_disable(venc->vdda_dac_reg); 434 435 venc_runtime_put(venc); 436 } 437 438 static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode) 439 { 440 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 441 return VENC_MODE_UNKNOWN; 442 443 if (mode->clock == omap_dss_pal_mode.clock && 444 mode->hdisplay == omap_dss_pal_mode.hdisplay && 445 mode->vdisplay == omap_dss_pal_mode.vdisplay) 446 return VENC_MODE_PAL; 447 448 if (mode->clock == omap_dss_ntsc_mode.clock && 449 mode->hdisplay == omap_dss_ntsc_mode.hdisplay && 450 mode->vdisplay == omap_dss_ntsc_mode.vdisplay) 451 return VENC_MODE_NTSC; 452 453 return VENC_MODE_UNKNOWN; 454 } 455 456 static int venc_dump_regs(struct seq_file *s, void *p) 457 { 458 struct venc_device *venc = s->private; 459 460 #define DUMPREG(venc, r) \ 461 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r)) 462 463 if (venc_runtime_get(venc)) 464 return 0; 465 466 DUMPREG(venc, VENC_F_CONTROL); 467 DUMPREG(venc, VENC_VIDOUT_CTRL); 468 DUMPREG(venc, VENC_SYNC_CTRL); 469 DUMPREG(venc, VENC_LLEN); 470 DUMPREG(venc, VENC_FLENS); 471 DUMPREG(venc, VENC_HFLTR_CTRL); 472 DUMPREG(venc, VENC_CC_CARR_WSS_CARR); 473 DUMPREG(venc, VENC_C_PHASE); 474 DUMPREG(venc, VENC_GAIN_U); 475 DUMPREG(venc, VENC_GAIN_V); 476 DUMPREG(venc, VENC_GAIN_Y); 477 DUMPREG(venc, VENC_BLACK_LEVEL); 478 DUMPREG(venc, VENC_BLANK_LEVEL); 479 DUMPREG(venc, VENC_X_COLOR); 480 DUMPREG(venc, VENC_M_CONTROL); 481 DUMPREG(venc, VENC_BSTAMP_WSS_DATA); 482 DUMPREG(venc, VENC_S_CARR); 483 DUMPREG(venc, VENC_LINE21); 484 DUMPREG(venc, VENC_LN_SEL); 485 DUMPREG(venc, VENC_L21__WC_CTL); 486 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER); 487 DUMPREG(venc, VENC_SAVID__EAVID); 488 DUMPREG(venc, VENC_FLEN__FAL); 489 DUMPREG(venc, VENC_LAL__PHASE_RESET); 490 DUMPREG(venc, VENC_HS_INT_START_STOP_X); 491 DUMPREG(venc, VENC_HS_EXT_START_STOP_X); 492 DUMPREG(venc, VENC_VS_INT_START_X); 493 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y); 494 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X); 495 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 496 DUMPREG(venc, VENC_VS_EXT_STOP_Y); 497 DUMPREG(venc, VENC_AVID_START_STOP_X); 498 DUMPREG(venc, VENC_AVID_START_STOP_Y); 499 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y); 500 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 501 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 502 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X); 503 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y); 504 DUMPREG(venc, VENC_GEN_CTRL); 505 DUMPREG(venc, VENC_OUTPUT_CONTROL); 506 DUMPREG(venc, VENC_OUTPUT_TEST); 507 508 venc_runtime_put(venc); 509 510 #undef DUMPREG 511 return 0; 512 } 513 514 static int venc_get_clocks(struct venc_device *venc) 515 { 516 struct clk *clk; 517 518 if (venc->requires_tv_dac_clk) { 519 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk"); 520 if (IS_ERR(clk)) { 521 DSSERR("can't get tv_dac_clk\n"); 522 return PTR_ERR(clk); 523 } 524 } else { 525 clk = NULL; 526 } 527 528 venc->tv_dac_clk = clk; 529 530 return 0; 531 } 532 533 /* ----------------------------------------------------------------------------- 534 * DRM Bridge Operations 535 */ 536 537 static int venc_bridge_attach(struct drm_bridge *bridge, 538 enum drm_bridge_attach_flags flags) 539 { 540 struct venc_device *venc = drm_bridge_to_venc(bridge); 541 542 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 543 return -EINVAL; 544 545 return drm_bridge_attach(bridge->encoder, venc->output.next_bridge, 546 bridge, flags); 547 } 548 549 static enum drm_mode_status 550 venc_bridge_mode_valid(struct drm_bridge *bridge, 551 const struct drm_display_mode *mode) 552 { 553 switch (venc_get_videomode(mode)) { 554 case VENC_MODE_PAL: 555 case VENC_MODE_NTSC: 556 return MODE_OK; 557 558 default: 559 return MODE_BAD; 560 } 561 } 562 563 static bool venc_bridge_mode_fixup(struct drm_bridge *bridge, 564 const struct drm_display_mode *mode, 565 struct drm_display_mode *adjusted_mode) 566 { 567 const struct drm_display_mode *venc_mode; 568 569 switch (venc_get_videomode(adjusted_mode)) { 570 case VENC_MODE_PAL: 571 venc_mode = &omap_dss_pal_mode; 572 break; 573 574 case VENC_MODE_NTSC: 575 venc_mode = &omap_dss_ntsc_mode; 576 break; 577 578 default: 579 return false; 580 } 581 582 drm_mode_copy(adjusted_mode, venc_mode); 583 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 584 drm_mode_set_name(adjusted_mode); 585 586 return true; 587 } 588 589 static void venc_bridge_mode_set(struct drm_bridge *bridge, 590 const struct drm_display_mode *mode, 591 const struct drm_display_mode *adjusted_mode) 592 { 593 struct venc_device *venc = drm_bridge_to_venc(bridge); 594 enum venc_videomode venc_mode = venc_get_videomode(adjusted_mode); 595 596 switch (venc_mode) { 597 default: 598 WARN_ON_ONCE(1); 599 /* Fall-through */ 600 case VENC_MODE_PAL: 601 venc->config = &venc_config_pal_trm; 602 break; 603 604 case VENC_MODE_NTSC: 605 venc->config = &venc_config_ntsc_trm; 606 break; 607 } 608 609 dispc_set_tv_pclk(venc->dss->dispc, 13500000); 610 } 611 612 static void venc_bridge_enable(struct drm_bridge *bridge) 613 { 614 struct venc_device *venc = drm_bridge_to_venc(bridge); 615 616 venc_power_on(venc); 617 } 618 619 static void venc_bridge_disable(struct drm_bridge *bridge) 620 { 621 struct venc_device *venc = drm_bridge_to_venc(bridge); 622 623 venc_power_off(venc); 624 } 625 626 static int venc_bridge_get_modes(struct drm_bridge *bridge, 627 struct drm_connector *connector) 628 { 629 static const struct drm_display_mode *modes[] = { 630 &omap_dss_pal_mode, 631 &omap_dss_ntsc_mode, 632 }; 633 unsigned int i; 634 635 for (i = 0; i < ARRAY_SIZE(modes); ++i) { 636 struct drm_display_mode *mode; 637 638 mode = drm_mode_duplicate(connector->dev, modes[i]); 639 if (!mode) 640 return i; 641 642 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 643 drm_mode_set_name(mode); 644 drm_mode_probed_add(connector, mode); 645 } 646 647 return ARRAY_SIZE(modes); 648 } 649 650 static const struct drm_bridge_funcs venc_bridge_funcs = { 651 .attach = venc_bridge_attach, 652 .mode_valid = venc_bridge_mode_valid, 653 .mode_fixup = venc_bridge_mode_fixup, 654 .mode_set = venc_bridge_mode_set, 655 .enable = venc_bridge_enable, 656 .disable = venc_bridge_disable, 657 .get_modes = venc_bridge_get_modes, 658 }; 659 660 static void venc_bridge_init(struct venc_device *venc) 661 { 662 venc->bridge.funcs = &venc_bridge_funcs; 663 venc->bridge.of_node = venc->pdev->dev.of_node; 664 venc->bridge.ops = DRM_BRIDGE_OP_MODES; 665 venc->bridge.type = DRM_MODE_CONNECTOR_SVIDEO; 666 venc->bridge.interlace_allowed = true; 667 668 drm_bridge_add(&venc->bridge); 669 } 670 671 static void venc_bridge_cleanup(struct venc_device *venc) 672 { 673 drm_bridge_remove(&venc->bridge); 674 } 675 676 /* ----------------------------------------------------------------------------- 677 * Component Bind & Unbind 678 */ 679 680 static int venc_bind(struct device *dev, struct device *master, void *data) 681 { 682 struct dss_device *dss = dss_get_device(master); 683 struct venc_device *venc = dev_get_drvdata(dev); 684 u8 rev_id; 685 int r; 686 687 venc->dss = dss; 688 689 r = venc_runtime_get(venc); 690 if (r) 691 return r; 692 693 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff); 694 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id); 695 696 venc_runtime_put(venc); 697 698 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs, 699 venc); 700 701 return 0; 702 } 703 704 static void venc_unbind(struct device *dev, struct device *master, void *data) 705 { 706 struct venc_device *venc = dev_get_drvdata(dev); 707 708 dss_debugfs_remove_file(venc->debugfs); 709 } 710 711 static const struct component_ops venc_component_ops = { 712 .bind = venc_bind, 713 .unbind = venc_unbind, 714 }; 715 716 /* ----------------------------------------------------------------------------- 717 * Probe & Remove, Suspend & Resume 718 */ 719 720 static int venc_init_output(struct venc_device *venc) 721 { 722 struct omap_dss_device *out = &venc->output; 723 int r; 724 725 venc_bridge_init(venc); 726 727 out->dev = &venc->pdev->dev; 728 out->id = OMAP_DSS_OUTPUT_VENC; 729 out->type = OMAP_DISPLAY_TYPE_VENC; 730 out->name = "venc.0"; 731 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 732 out->owner = THIS_MODULE; 733 out->of_port = 0; 734 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES; 735 736 r = omapdss_device_init_output(out, &venc->bridge); 737 if (r < 0) { 738 venc_bridge_cleanup(venc); 739 return r; 740 } 741 742 omapdss_device_register(out); 743 744 return 0; 745 } 746 747 static void venc_uninit_output(struct venc_device *venc) 748 { 749 omapdss_device_unregister(&venc->output); 750 omapdss_device_cleanup_output(&venc->output); 751 752 venc_bridge_cleanup(venc); 753 } 754 755 static int venc_probe_of(struct venc_device *venc) 756 { 757 struct device_node *node = venc->pdev->dev.of_node; 758 struct device_node *ep; 759 u32 channels; 760 int r; 761 762 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 763 if (!ep) 764 return 0; 765 766 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 767 768 r = of_property_read_u32(ep, "ti,channels", &channels); 769 if (r) { 770 dev_err(&venc->pdev->dev, 771 "failed to read property 'ti,channels': %d\n", r); 772 goto err; 773 } 774 775 switch (channels) { 776 case 1: 777 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE; 778 break; 779 case 2: 780 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO; 781 break; 782 default: 783 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n", 784 channels); 785 r = -EINVAL; 786 goto err; 787 } 788 789 of_node_put(ep); 790 791 return 0; 792 793 err: 794 of_node_put(ep); 795 return r; 796 } 797 798 static const struct soc_device_attribute venc_soc_devices[] = { 799 { .machine = "OMAP3[45]*" }, 800 { .machine = "AM35*" }, 801 { /* sentinel */ } 802 }; 803 804 static int venc_probe(struct platform_device *pdev) 805 { 806 struct venc_device *venc; 807 struct resource *venc_mem; 808 int r; 809 810 venc = kzalloc(sizeof(*venc), GFP_KERNEL); 811 if (!venc) 812 return -ENOMEM; 813 814 venc->pdev = pdev; 815 816 platform_set_drvdata(pdev, venc); 817 818 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 819 if (soc_device_match(venc_soc_devices)) 820 venc->requires_tv_dac_clk = true; 821 822 venc->config = &venc_config_pal_trm; 823 824 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0); 825 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem); 826 if (IS_ERR(venc->base)) { 827 r = PTR_ERR(venc->base); 828 goto err_free; 829 } 830 831 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda"); 832 if (IS_ERR(venc->vdda_dac_reg)) { 833 r = PTR_ERR(venc->vdda_dac_reg); 834 if (r != -EPROBE_DEFER) 835 DSSERR("can't get VDDA_DAC regulator\n"); 836 goto err_free; 837 } 838 839 r = venc_get_clocks(venc); 840 if (r) 841 goto err_free; 842 843 r = venc_probe_of(venc); 844 if (r) 845 goto err_free; 846 847 pm_runtime_enable(&pdev->dev); 848 849 r = venc_init_output(venc); 850 if (r) 851 goto err_pm_disable; 852 853 r = component_add(&pdev->dev, &venc_component_ops); 854 if (r) 855 goto err_uninit_output; 856 857 return 0; 858 859 err_uninit_output: 860 venc_uninit_output(venc); 861 err_pm_disable: 862 pm_runtime_disable(&pdev->dev); 863 err_free: 864 kfree(venc); 865 return r; 866 } 867 868 static int venc_remove(struct platform_device *pdev) 869 { 870 struct venc_device *venc = platform_get_drvdata(pdev); 871 872 component_del(&pdev->dev, &venc_component_ops); 873 874 venc_uninit_output(venc); 875 876 pm_runtime_disable(&pdev->dev); 877 878 kfree(venc); 879 return 0; 880 } 881 882 static int venc_runtime_suspend(struct device *dev) 883 { 884 struct venc_device *venc = dev_get_drvdata(dev); 885 886 if (venc->tv_dac_clk) 887 clk_disable_unprepare(venc->tv_dac_clk); 888 889 return 0; 890 } 891 892 static int venc_runtime_resume(struct device *dev) 893 { 894 struct venc_device *venc = dev_get_drvdata(dev); 895 896 if (venc->tv_dac_clk) 897 clk_prepare_enable(venc->tv_dac_clk); 898 899 return 0; 900 } 901 902 static const struct dev_pm_ops venc_pm_ops = { 903 .runtime_suspend = venc_runtime_suspend, 904 .runtime_resume = venc_runtime_resume, 905 }; 906 907 static const struct of_device_id venc_of_match[] = { 908 { .compatible = "ti,omap2-venc", }, 909 { .compatible = "ti,omap3-venc", }, 910 { .compatible = "ti,omap4-venc", }, 911 {}, 912 }; 913 914 struct platform_driver omap_venchw_driver = { 915 .probe = venc_probe, 916 .remove = venc_remove, 917 .driver = { 918 .name = "omapdss_venc", 919 .pm = &venc_pm_ops, 920 .of_match_table = venc_of_match, 921 .suppress_bind_attrs = true, 922 }, 923 }; 924