1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * VENC settings from TI's DSS driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "VENC" 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/mutex.h> 28 #include <linux/completion.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/seq_file.h> 32 #include <linux/platform_device.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/of.h> 36 #include <linux/of_graph.h> 37 #include <linux/component.h> 38 #include <linux/sys_soc.h> 39 40 #include "omapdss.h" 41 #include "dss.h" 42 43 /* Venc registers */ 44 #define VENC_REV_ID 0x00 45 #define VENC_STATUS 0x04 46 #define VENC_F_CONTROL 0x08 47 #define VENC_VIDOUT_CTRL 0x10 48 #define VENC_SYNC_CTRL 0x14 49 #define VENC_LLEN 0x1C 50 #define VENC_FLENS 0x20 51 #define VENC_HFLTR_CTRL 0x24 52 #define VENC_CC_CARR_WSS_CARR 0x28 53 #define VENC_C_PHASE 0x2C 54 #define VENC_GAIN_U 0x30 55 #define VENC_GAIN_V 0x34 56 #define VENC_GAIN_Y 0x38 57 #define VENC_BLACK_LEVEL 0x3C 58 #define VENC_BLANK_LEVEL 0x40 59 #define VENC_X_COLOR 0x44 60 #define VENC_M_CONTROL 0x48 61 #define VENC_BSTAMP_WSS_DATA 0x4C 62 #define VENC_S_CARR 0x50 63 #define VENC_LINE21 0x54 64 #define VENC_LN_SEL 0x58 65 #define VENC_L21__WC_CTL 0x5C 66 #define VENC_HTRIGGER_VTRIGGER 0x60 67 #define VENC_SAVID__EAVID 0x64 68 #define VENC_FLEN__FAL 0x68 69 #define VENC_LAL__PHASE_RESET 0x6C 70 #define VENC_HS_INT_START_STOP_X 0x70 71 #define VENC_HS_EXT_START_STOP_X 0x74 72 #define VENC_VS_INT_START_X 0x78 73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 76 #define VENC_VS_EXT_STOP_Y 0x88 77 #define VENC_AVID_START_STOP_X 0x90 78 #define VENC_AVID_START_STOP_Y 0x94 79 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 82 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 83 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 84 #define VENC_GEN_CTRL 0xB8 85 #define VENC_OUTPUT_CONTROL 0xC4 86 #define VENC_OUTPUT_TEST 0xC8 87 #define VENC_DAC_B__DAC_C 0xC8 88 89 struct venc_config { 90 u32 f_control; 91 u32 vidout_ctrl; 92 u32 sync_ctrl; 93 u32 llen; 94 u32 flens; 95 u32 hfltr_ctrl; 96 u32 cc_carr_wss_carr; 97 u32 c_phase; 98 u32 gain_u; 99 u32 gain_v; 100 u32 gain_y; 101 u32 black_level; 102 u32 blank_level; 103 u32 x_color; 104 u32 m_control; 105 u32 bstamp_wss_data; 106 u32 s_carr; 107 u32 line21; 108 u32 ln_sel; 109 u32 l21__wc_ctl; 110 u32 htrigger_vtrigger; 111 u32 savid__eavid; 112 u32 flen__fal; 113 u32 lal__phase_reset; 114 u32 hs_int_start_stop_x; 115 u32 hs_ext_start_stop_x; 116 u32 vs_int_start_x; 117 u32 vs_int_stop_x__vs_int_start_y; 118 u32 vs_int_stop_y__vs_ext_start_x; 119 u32 vs_ext_stop_x__vs_ext_start_y; 120 u32 vs_ext_stop_y; 121 u32 avid_start_stop_x; 122 u32 avid_start_stop_y; 123 u32 fid_int_start_x__fid_int_start_y; 124 u32 fid_int_offset_y__fid_ext_start_x; 125 u32 fid_ext_start_y__fid_ext_offset_y; 126 u32 tvdetgp_int_start_stop_x; 127 u32 tvdetgp_int_start_stop_y; 128 u32 gen_ctrl; 129 }; 130 131 /* from TRM */ 132 static const struct venc_config venc_config_pal_trm = { 133 .f_control = 0, 134 .vidout_ctrl = 1, 135 .sync_ctrl = 0x40, 136 .llen = 0x35F, /* 863 */ 137 .flens = 0x270, /* 624 */ 138 .hfltr_ctrl = 0, 139 .cc_carr_wss_carr = 0x2F7225ED, 140 .c_phase = 0, 141 .gain_u = 0x111, 142 .gain_v = 0x181, 143 .gain_y = 0x140, 144 .black_level = 0x3B, 145 .blank_level = 0x3B, 146 .x_color = 0x7, 147 .m_control = 0x2, 148 .bstamp_wss_data = 0x3F, 149 .s_carr = 0x2A098ACB, 150 .line21 = 0, 151 .ln_sel = 0x01290015, 152 .l21__wc_ctl = 0x0000F603, 153 .htrigger_vtrigger = 0, 154 155 .savid__eavid = 0x06A70108, 156 .flen__fal = 0x00180270, 157 .lal__phase_reset = 0x00040135, 158 .hs_int_start_stop_x = 0x00880358, 159 .hs_ext_start_stop_x = 0x000F035F, 160 .vs_int_start_x = 0x01A70000, 161 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 164 .vs_ext_stop_y = 0x00000025, 165 .avid_start_stop_x = 0x03530083, 166 .avid_start_stop_y = 0x026C002E, 167 .fid_int_start_x__fid_int_start_y = 0x0001008A, 168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 170 171 .tvdetgp_int_start_stop_x = 0x00140001, 172 .tvdetgp_int_start_stop_y = 0x00010001, 173 .gen_ctrl = 0x00FF0000, 174 }; 175 176 /* from TRM */ 177 static const struct venc_config venc_config_ntsc_trm = { 178 .f_control = 0, 179 .vidout_ctrl = 1, 180 .sync_ctrl = 0x8040, 181 .llen = 0x359, 182 .flens = 0x20C, 183 .hfltr_ctrl = 0, 184 .cc_carr_wss_carr = 0x043F2631, 185 .c_phase = 0, 186 .gain_u = 0x102, 187 .gain_v = 0x16C, 188 .gain_y = 0x12F, 189 .black_level = 0x43, 190 .blank_level = 0x38, 191 .x_color = 0x7, 192 .m_control = 0x1, 193 .bstamp_wss_data = 0x38, 194 .s_carr = 0x21F07C1F, 195 .line21 = 0, 196 .ln_sel = 0x01310011, 197 .l21__wc_ctl = 0x0000F003, 198 .htrigger_vtrigger = 0, 199 200 .savid__eavid = 0x069300F4, 201 .flen__fal = 0x0016020C, 202 .lal__phase_reset = 0x00060107, 203 .hs_int_start_stop_x = 0x008E0350, 204 .hs_ext_start_stop_x = 0x000F0359, 205 .vs_int_start_x = 0x01A00000, 206 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 209 .vs_ext_stop_y = 0x00000006, 210 .avid_start_stop_x = 0x03480078, 211 .avid_start_stop_y = 0x02060024, 212 .fid_int_start_x__fid_int_start_y = 0x0001008A, 213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 215 216 .tvdetgp_int_start_stop_x = 0x00140001, 217 .tvdetgp_int_start_stop_y = 0x00010001, 218 .gen_ctrl = 0x00F90000, 219 }; 220 221 static const struct venc_config venc_config_pal_bdghi = { 222 .f_control = 0, 223 .vidout_ctrl = 0, 224 .sync_ctrl = 0, 225 .hfltr_ctrl = 0, 226 .x_color = 0, 227 .line21 = 0, 228 .ln_sel = 21, 229 .htrigger_vtrigger = 0, 230 .tvdetgp_int_start_stop_x = 0x00140001, 231 .tvdetgp_int_start_stop_y = 0x00010001, 232 .gen_ctrl = 0x00FB0000, 233 234 .llen = 864-1, 235 .flens = 625-1, 236 .cc_carr_wss_carr = 0x2F7625ED, 237 .c_phase = 0xDF, 238 .gain_u = 0x111, 239 .gain_v = 0x181, 240 .gain_y = 0x140, 241 .black_level = 0x3e, 242 .blank_level = 0x3e, 243 .m_control = 0<<2 | 1<<1, 244 .bstamp_wss_data = 0x42, 245 .s_carr = 0x2a098acb, 246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, 247 .savid__eavid = 0x06A70108, 248 .flen__fal = 23<<16 | 624<<0, 249 .lal__phase_reset = 2<<17 | 310<<0, 250 .hs_int_start_stop_x = 0x00920358, 251 .hs_ext_start_stop_x = 0x000F035F, 252 .vs_int_start_x = 0x1a7<<16, 253 .vs_int_stop_x__vs_int_start_y = 0x000601A7, 254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, 255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af, 256 .vs_ext_stop_y = 0x05, 257 .avid_start_stop_x = 0x03530082, 258 .avid_start_stop_y = 0x0270002E, 259 .fid_int_start_x__fid_int_start_y = 0x0005008A, 260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 }; 263 264 enum venc_videomode { 265 VENC_MODE_UNKNOWN, 266 VENC_MODE_PAL, 267 VENC_MODE_NTSC, 268 }; 269 270 static const struct videomode omap_dss_pal_vm = { 271 .hactive = 720, 272 .vactive = 574, 273 .pixelclock = 13500000, 274 .hsync_len = 64, 275 .hfront_porch = 12, 276 .hback_porch = 68, 277 .vsync_len = 5, 278 .vfront_porch = 5, 279 .vback_porch = 41, 280 281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 283 DISPLAY_FLAGS_PIXDATA_POSEDGE | 284 DISPLAY_FLAGS_SYNC_NEGEDGE, 285 }; 286 287 static const struct videomode omap_dss_ntsc_vm = { 288 .hactive = 720, 289 .vactive = 482, 290 .pixelclock = 13500000, 291 .hsync_len = 64, 292 .hfront_porch = 16, 293 .hback_porch = 58, 294 .vsync_len = 6, 295 .vfront_porch = 6, 296 .vback_porch = 31, 297 298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | 299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | 300 DISPLAY_FLAGS_PIXDATA_POSEDGE | 301 DISPLAY_FLAGS_SYNC_NEGEDGE, 302 }; 303 304 static enum venc_videomode venc_get_videomode(const struct videomode *vm) 305 { 306 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) 307 return VENC_MODE_UNKNOWN; 308 309 if (vm->pixelclock == omap_dss_pal_vm.pixelclock && 310 vm->hactive == omap_dss_pal_vm.hactive && 311 vm->vactive == omap_dss_pal_vm.vactive) 312 return VENC_MODE_PAL; 313 314 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && 315 vm->hactive == omap_dss_ntsc_vm.hactive && 316 vm->vactive == omap_dss_ntsc_vm.vactive) 317 return VENC_MODE_NTSC; 318 319 return VENC_MODE_UNKNOWN; 320 } 321 322 struct venc_device { 323 struct platform_device *pdev; 324 void __iomem *base; 325 struct mutex venc_lock; 326 struct regulator *vdda_dac_reg; 327 struct dss_device *dss; 328 329 struct dss_debugfs_entry *debugfs; 330 331 struct clk *tv_dac_clk; 332 333 struct videomode vm; 334 enum omap_dss_venc_type type; 335 bool invert_polarity; 336 bool requires_tv_dac_clk; 337 338 struct omap_dss_device output; 339 }; 340 341 #define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output) 342 343 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val) 344 { 345 __raw_writel(val, venc->base + idx); 346 } 347 348 static inline u32 venc_read_reg(struct venc_device *venc, int idx) 349 { 350 u32 l = __raw_readl(venc->base + idx); 351 return l; 352 } 353 354 static void venc_write_config(struct venc_device *venc, 355 const struct venc_config *config) 356 { 357 DSSDBG("write venc conf\n"); 358 359 venc_write_reg(venc, VENC_LLEN, config->llen); 360 venc_write_reg(venc, VENC_FLENS, config->flens); 361 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 362 venc_write_reg(venc, VENC_C_PHASE, config->c_phase); 363 venc_write_reg(venc, VENC_GAIN_U, config->gain_u); 364 venc_write_reg(venc, VENC_GAIN_V, config->gain_v); 365 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y); 366 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level); 367 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level); 368 venc_write_reg(venc, VENC_M_CONTROL, config->m_control); 369 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data); 370 venc_write_reg(venc, VENC_S_CARR, config->s_carr); 371 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl); 372 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid); 373 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal); 374 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset); 375 venc_write_reg(venc, VENC_HS_INT_START_STOP_X, 376 config->hs_int_start_stop_x); 377 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X, 378 config->hs_ext_start_stop_x); 379 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x); 380 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y, 381 config->vs_int_stop_x__vs_int_start_y); 382 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X, 383 config->vs_int_stop_y__vs_ext_start_x); 384 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 385 config->vs_ext_stop_x__vs_ext_start_y); 386 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 387 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x); 388 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 389 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y, 390 config->fid_int_start_x__fid_int_start_y); 391 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 392 config->fid_int_offset_y__fid_ext_start_x); 393 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 394 config->fid_ext_start_y__fid_ext_offset_y); 395 396 venc_write_reg(venc, VENC_DAC_B__DAC_C, 397 venc_read_reg(venc, VENC_DAC_B__DAC_C)); 398 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl); 399 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl); 400 venc_write_reg(venc, VENC_X_COLOR, config->x_color); 401 venc_write_reg(venc, VENC_LINE21, config->line21); 402 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel); 403 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 404 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X, 405 config->tvdetgp_int_start_stop_x); 406 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y, 407 config->tvdetgp_int_start_stop_y); 408 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl); 409 venc_write_reg(venc, VENC_F_CONTROL, config->f_control); 410 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl); 411 } 412 413 static void venc_reset(struct venc_device *venc) 414 { 415 int t = 1000; 416 417 venc_write_reg(venc, VENC_F_CONTROL, 1<<8); 418 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) { 419 if (--t == 0) { 420 DSSERR("Failed to reset venc\n"); 421 return; 422 } 423 } 424 425 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 426 /* the magical sleep that makes things work */ 427 /* XXX more info? What bug this circumvents? */ 428 msleep(20); 429 #endif 430 } 431 432 static int venc_runtime_get(struct venc_device *venc) 433 { 434 int r; 435 436 DSSDBG("venc_runtime_get\n"); 437 438 r = pm_runtime_get_sync(&venc->pdev->dev); 439 WARN_ON(r < 0); 440 return r < 0 ? r : 0; 441 } 442 443 static void venc_runtime_put(struct venc_device *venc) 444 { 445 int r; 446 447 DSSDBG("venc_runtime_put\n"); 448 449 r = pm_runtime_put_sync(&venc->pdev->dev); 450 WARN_ON(r < 0 && r != -ENOSYS); 451 } 452 453 static const struct venc_config *venc_timings_to_config(const struct videomode *vm) 454 { 455 switch (venc_get_videomode(vm)) { 456 default: 457 WARN_ON_ONCE(1); 458 case VENC_MODE_PAL: 459 return &venc_config_pal_trm; 460 case VENC_MODE_NTSC: 461 return &venc_config_ntsc_trm; 462 } 463 } 464 465 static int venc_power_on(struct venc_device *venc) 466 { 467 u32 l; 468 int r; 469 470 r = venc_runtime_get(venc); 471 if (r) 472 goto err0; 473 474 venc_reset(venc); 475 venc_write_config(venc, venc_timings_to_config(&venc->vm)); 476 477 dss_set_venc_output(venc->dss, venc->type); 478 dss_set_dac_pwrdn_bgz(venc->dss, 1); 479 480 l = 0; 481 482 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE) 483 l |= 1 << 1; 484 else /* S-Video */ 485 l |= (1 << 0) | (1 << 2); 486 487 if (venc->invert_polarity == false) 488 l |= 1 << 3; 489 490 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l); 491 492 r = regulator_enable(venc->vdda_dac_reg); 493 if (r) 494 goto err1; 495 496 r = dss_mgr_enable(&venc->output); 497 if (r) 498 goto err2; 499 500 return 0; 501 502 err2: 503 regulator_disable(venc->vdda_dac_reg); 504 err1: 505 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 506 dss_set_dac_pwrdn_bgz(venc->dss, 0); 507 508 venc_runtime_put(venc); 509 err0: 510 return r; 511 } 512 513 static void venc_power_off(struct venc_device *venc) 514 { 515 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0); 516 dss_set_dac_pwrdn_bgz(venc->dss, 0); 517 518 dss_mgr_disable(&venc->output); 519 520 regulator_disable(venc->vdda_dac_reg); 521 522 venc_runtime_put(venc); 523 } 524 525 static void venc_display_enable(struct omap_dss_device *dssdev) 526 { 527 struct venc_device *venc = dssdev_to_venc(dssdev); 528 529 DSSDBG("venc_display_enable\n"); 530 531 mutex_lock(&venc->venc_lock); 532 533 venc_power_on(venc); 534 535 mutex_unlock(&venc->venc_lock); 536 } 537 538 static void venc_display_disable(struct omap_dss_device *dssdev) 539 { 540 struct venc_device *venc = dssdev_to_venc(dssdev); 541 542 DSSDBG("venc_display_disable\n"); 543 544 mutex_lock(&venc->venc_lock); 545 546 venc_power_off(venc); 547 548 mutex_unlock(&venc->venc_lock); 549 } 550 551 static int venc_get_modes(struct omap_dss_device *dssdev, 552 struct drm_connector *connector) 553 { 554 static const struct videomode *modes[] = { 555 &omap_dss_pal_vm, 556 &omap_dss_ntsc_vm, 557 }; 558 unsigned int i; 559 560 for (i = 0; i < ARRAY_SIZE(modes); ++i) { 561 struct drm_display_mode *mode; 562 563 mode = drm_mode_create(connector->dev); 564 if (!mode) 565 return i; 566 567 drm_display_mode_from_videomode(modes[i], mode); 568 569 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 570 drm_mode_set_name(mode); 571 drm_mode_probed_add(connector, mode); 572 } 573 574 return ARRAY_SIZE(modes); 575 } 576 577 static void venc_set_timings(struct omap_dss_device *dssdev, 578 const struct videomode *vm) 579 { 580 struct venc_device *venc = dssdev_to_venc(dssdev); 581 582 DSSDBG("venc_set_timings\n"); 583 584 mutex_lock(&venc->venc_lock); 585 586 venc->vm = *vm; 587 588 dispc_set_tv_pclk(venc->dss->dispc, 13500000); 589 590 mutex_unlock(&venc->venc_lock); 591 } 592 593 static int venc_check_timings(struct omap_dss_device *dssdev, 594 struct videomode *vm) 595 { 596 DSSDBG("venc_check_timings\n"); 597 598 switch (venc_get_videomode(vm)) { 599 case VENC_MODE_PAL: 600 *vm = omap_dss_pal_vm; 601 return 0; 602 603 case VENC_MODE_NTSC: 604 *vm = omap_dss_ntsc_vm; 605 return 0; 606 607 default: 608 return -EINVAL; 609 } 610 } 611 612 static int venc_dump_regs(struct seq_file *s, void *p) 613 { 614 struct venc_device *venc = s->private; 615 616 #define DUMPREG(venc, r) \ 617 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r)) 618 619 if (venc_runtime_get(venc)) 620 return 0; 621 622 DUMPREG(venc, VENC_F_CONTROL); 623 DUMPREG(venc, VENC_VIDOUT_CTRL); 624 DUMPREG(venc, VENC_SYNC_CTRL); 625 DUMPREG(venc, VENC_LLEN); 626 DUMPREG(venc, VENC_FLENS); 627 DUMPREG(venc, VENC_HFLTR_CTRL); 628 DUMPREG(venc, VENC_CC_CARR_WSS_CARR); 629 DUMPREG(venc, VENC_C_PHASE); 630 DUMPREG(venc, VENC_GAIN_U); 631 DUMPREG(venc, VENC_GAIN_V); 632 DUMPREG(venc, VENC_GAIN_Y); 633 DUMPREG(venc, VENC_BLACK_LEVEL); 634 DUMPREG(venc, VENC_BLANK_LEVEL); 635 DUMPREG(venc, VENC_X_COLOR); 636 DUMPREG(venc, VENC_M_CONTROL); 637 DUMPREG(venc, VENC_BSTAMP_WSS_DATA); 638 DUMPREG(venc, VENC_S_CARR); 639 DUMPREG(venc, VENC_LINE21); 640 DUMPREG(venc, VENC_LN_SEL); 641 DUMPREG(venc, VENC_L21__WC_CTL); 642 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER); 643 DUMPREG(venc, VENC_SAVID__EAVID); 644 DUMPREG(venc, VENC_FLEN__FAL); 645 DUMPREG(venc, VENC_LAL__PHASE_RESET); 646 DUMPREG(venc, VENC_HS_INT_START_STOP_X); 647 DUMPREG(venc, VENC_HS_EXT_START_STOP_X); 648 DUMPREG(venc, VENC_VS_INT_START_X); 649 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y); 650 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X); 651 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 652 DUMPREG(venc, VENC_VS_EXT_STOP_Y); 653 DUMPREG(venc, VENC_AVID_START_STOP_X); 654 DUMPREG(venc, VENC_AVID_START_STOP_Y); 655 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y); 656 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 657 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 658 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X); 659 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y); 660 DUMPREG(venc, VENC_GEN_CTRL); 661 DUMPREG(venc, VENC_OUTPUT_CONTROL); 662 DUMPREG(venc, VENC_OUTPUT_TEST); 663 664 venc_runtime_put(venc); 665 666 #undef DUMPREG 667 return 0; 668 } 669 670 static int venc_get_clocks(struct venc_device *venc) 671 { 672 struct clk *clk; 673 674 if (venc->requires_tv_dac_clk) { 675 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk"); 676 if (IS_ERR(clk)) { 677 DSSERR("can't get tv_dac_clk\n"); 678 return PTR_ERR(clk); 679 } 680 } else { 681 clk = NULL; 682 } 683 684 venc->tv_dac_clk = clk; 685 686 return 0; 687 } 688 689 static int venc_connect(struct omap_dss_device *src, 690 struct omap_dss_device *dst) 691 { 692 return omapdss_device_connect(dst->dss, dst, dst->next); 693 } 694 695 static void venc_disconnect(struct omap_dss_device *src, 696 struct omap_dss_device *dst) 697 { 698 omapdss_device_disconnect(dst, dst->next); 699 } 700 701 static const struct omap_dss_device_ops venc_ops = { 702 .connect = venc_connect, 703 .disconnect = venc_disconnect, 704 705 .enable = venc_display_enable, 706 .disable = venc_display_disable, 707 708 .check_timings = venc_check_timings, 709 .set_timings = venc_set_timings, 710 711 .get_modes = venc_get_modes, 712 }; 713 714 /* ----------------------------------------------------------------------------- 715 * Component Bind & Unbind 716 */ 717 718 static int venc_bind(struct device *dev, struct device *master, void *data) 719 { 720 struct dss_device *dss = dss_get_device(master); 721 struct venc_device *venc = dev_get_drvdata(dev); 722 u8 rev_id; 723 int r; 724 725 venc->dss = dss; 726 727 r = venc_runtime_get(venc); 728 if (r) 729 return r; 730 731 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff); 732 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id); 733 734 venc_runtime_put(venc); 735 736 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs, 737 venc); 738 739 return 0; 740 } 741 742 static void venc_unbind(struct device *dev, struct device *master, void *data) 743 { 744 struct venc_device *venc = dev_get_drvdata(dev); 745 746 dss_debugfs_remove_file(venc->debugfs); 747 } 748 749 static const struct component_ops venc_component_ops = { 750 .bind = venc_bind, 751 .unbind = venc_unbind, 752 }; 753 754 /* ----------------------------------------------------------------------------- 755 * Probe & Remove, Suspend & Resume 756 */ 757 758 static int venc_init_output(struct venc_device *venc) 759 { 760 struct omap_dss_device *out = &venc->output; 761 int r; 762 763 out->dev = &venc->pdev->dev; 764 out->id = OMAP_DSS_OUTPUT_VENC; 765 out->output_type = OMAP_DISPLAY_TYPE_VENC; 766 out->name = "venc.0"; 767 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 768 out->ops = &venc_ops; 769 out->owner = THIS_MODULE; 770 out->of_ports = BIT(0); 771 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES; 772 773 r = omapdss_device_init_output(out); 774 if (r < 0) 775 return r; 776 777 omapdss_device_register(out); 778 779 return 0; 780 } 781 782 static void venc_uninit_output(struct venc_device *venc) 783 { 784 omapdss_device_unregister(&venc->output); 785 omapdss_device_cleanup_output(&venc->output); 786 } 787 788 static int venc_probe_of(struct venc_device *venc) 789 { 790 struct device_node *node = venc->pdev->dev.of_node; 791 struct device_node *ep; 792 u32 channels; 793 int r; 794 795 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 796 if (!ep) 797 return 0; 798 799 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 800 801 r = of_property_read_u32(ep, "ti,channels", &channels); 802 if (r) { 803 dev_err(&venc->pdev->dev, 804 "failed to read property 'ti,channels': %d\n", r); 805 goto err; 806 } 807 808 switch (channels) { 809 case 1: 810 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE; 811 break; 812 case 2: 813 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO; 814 break; 815 default: 816 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n", 817 channels); 818 r = -EINVAL; 819 goto err; 820 } 821 822 of_node_put(ep); 823 824 return 0; 825 826 err: 827 of_node_put(ep); 828 return r; 829 } 830 831 static const struct soc_device_attribute venc_soc_devices[] = { 832 { .machine = "OMAP3[45]*" }, 833 { .machine = "AM35*" }, 834 { /* sentinel */ } 835 }; 836 837 static int venc_probe(struct platform_device *pdev) 838 { 839 struct venc_device *venc; 840 struct resource *venc_mem; 841 int r; 842 843 venc = kzalloc(sizeof(*venc), GFP_KERNEL); 844 if (!venc) 845 return -ENOMEM; 846 847 venc->pdev = pdev; 848 849 platform_set_drvdata(pdev, venc); 850 851 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 852 if (soc_device_match(venc_soc_devices)) 853 venc->requires_tv_dac_clk = true; 854 855 mutex_init(&venc->venc_lock); 856 857 venc->vm = omap_dss_pal_vm; 858 859 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0); 860 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem); 861 if (IS_ERR(venc->base)) { 862 r = PTR_ERR(venc->base); 863 goto err_free; 864 } 865 866 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda"); 867 if (IS_ERR(venc->vdda_dac_reg)) { 868 r = PTR_ERR(venc->vdda_dac_reg); 869 if (r != -EPROBE_DEFER) 870 DSSERR("can't get VDDA_DAC regulator\n"); 871 goto err_free; 872 } 873 874 r = venc_get_clocks(venc); 875 if (r) 876 goto err_free; 877 878 r = venc_probe_of(venc); 879 if (r) 880 goto err_free; 881 882 pm_runtime_enable(&pdev->dev); 883 884 r = venc_init_output(venc); 885 if (r) 886 goto err_pm_disable; 887 888 r = component_add(&pdev->dev, &venc_component_ops); 889 if (r) 890 goto err_uninit_output; 891 892 return 0; 893 894 err_uninit_output: 895 venc_uninit_output(venc); 896 err_pm_disable: 897 pm_runtime_disable(&pdev->dev); 898 err_free: 899 kfree(venc); 900 return r; 901 } 902 903 static int venc_remove(struct platform_device *pdev) 904 { 905 struct venc_device *venc = platform_get_drvdata(pdev); 906 907 component_del(&pdev->dev, &venc_component_ops); 908 909 venc_uninit_output(venc); 910 911 pm_runtime_disable(&pdev->dev); 912 913 kfree(venc); 914 return 0; 915 } 916 917 static int venc_runtime_suspend(struct device *dev) 918 { 919 struct venc_device *venc = dev_get_drvdata(dev); 920 921 if (venc->tv_dac_clk) 922 clk_disable_unprepare(venc->tv_dac_clk); 923 924 return 0; 925 } 926 927 static int venc_runtime_resume(struct device *dev) 928 { 929 struct venc_device *venc = dev_get_drvdata(dev); 930 931 if (venc->tv_dac_clk) 932 clk_prepare_enable(venc->tv_dac_clk); 933 934 return 0; 935 } 936 937 static const struct dev_pm_ops venc_pm_ops = { 938 .runtime_suspend = venc_runtime_suspend, 939 .runtime_resume = venc_runtime_resume, 940 }; 941 942 static const struct of_device_id venc_of_match[] = { 943 { .compatible = "ti,omap2-venc", }, 944 { .compatible = "ti,omap3-venc", }, 945 { .compatible = "ti,omap4-venc", }, 946 {}, 947 }; 948 949 struct platform_driver omap_venchw_driver = { 950 .probe = venc_probe, 951 .remove = venc_remove, 952 .driver = { 953 .name = "omapdss_venc", 954 .pm = &venc_pm_ops, 955 .of_match_table = venc_of_match, 956 .suppress_bind_attrs = true, 957 }, 958 }; 959