1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define DSS_SUBSYS_NAME "SDI" 19 20 #include <linux/kernel.h> 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/export.h> 25 #include <linux/platform_device.h> 26 #include <linux/string.h> 27 #include <linux/of.h> 28 29 #include "omapdss.h" 30 #include "dss.h" 31 32 struct sdi_device { 33 struct platform_device *pdev; 34 struct dss_device *dss; 35 36 bool update_enabled; 37 struct regulator *vdds_sdi_reg; 38 39 struct dss_lcd_mgr_config mgr_config; 40 struct videomode vm; 41 int datapairs; 42 43 struct omap_dss_device output; 44 }; 45 46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output) 47 48 struct sdi_clk_calc_ctx { 49 struct sdi_device *sdi; 50 unsigned long pck_min, pck_max; 51 52 unsigned long fck; 53 struct dispc_clock_info dispc_cinfo; 54 }; 55 56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 57 unsigned long pck, void *data) 58 { 59 struct sdi_clk_calc_ctx *ctx = data; 60 61 ctx->dispc_cinfo.lck_div = lckd; 62 ctx->dispc_cinfo.pck_div = pckd; 63 ctx->dispc_cinfo.lck = lck; 64 ctx->dispc_cinfo.pck = pck; 65 66 return true; 67 } 68 69 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 70 { 71 struct sdi_clk_calc_ctx *ctx = data; 72 73 ctx->fck = fck; 74 75 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 76 ctx->pck_min, ctx->pck_max, 77 dpi_calc_dispc_cb, ctx); 78 } 79 80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 81 unsigned long *fck, 82 struct dispc_clock_info *dispc_cinfo) 83 { 84 int i; 85 struct sdi_clk_calc_ctx ctx; 86 87 /* 88 * DSS fclk gives us very few possibilities, so finding a good pixel 89 * clock may not be possible. We try multiple times to find the clock, 90 * each time widening the pixel clock range we look for, up to 91 * +/- 1MHz. 92 */ 93 94 for (i = 0; i < 10; ++i) { 95 bool ok; 96 97 memset(&ctx, 0, sizeof(ctx)); 98 99 ctx.sdi = sdi; 100 101 if (pclk > 1000 * i * i * i) 102 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 103 else 104 ctx.pck_min = 0; 105 ctx.pck_max = pclk + 1000 * i * i * i; 106 107 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 108 dpi_calc_dss_cb, &ctx); 109 if (ok) { 110 *fck = ctx.fck; 111 *dispc_cinfo = ctx.dispc_cinfo; 112 return 0; 113 } 114 } 115 116 return -EINVAL; 117 } 118 119 static void sdi_config_lcd_manager(struct sdi_device *sdi) 120 { 121 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 122 123 sdi->mgr_config.stallmode = false; 124 sdi->mgr_config.fifohandcheck = false; 125 126 sdi->mgr_config.video_port_width = 24; 127 sdi->mgr_config.lcden_sig_polarity = 1; 128 129 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 130 } 131 132 static int sdi_display_enable(struct omap_dss_device *dssdev) 133 { 134 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 135 struct videomode *vm = &sdi->vm; 136 unsigned long fck; 137 struct dispc_clock_info dispc_cinfo; 138 unsigned long pck; 139 int r; 140 141 if (!sdi->output.dispc_channel_connected) { 142 DSSERR("failed to enable display: no output/manager\n"); 143 return -ENODEV; 144 } 145 146 r = regulator_enable(sdi->vdds_sdi_reg); 147 if (r) 148 goto err_reg_enable; 149 150 r = dispc_runtime_get(sdi->dss->dispc); 151 if (r) 152 goto err_get_dispc; 153 154 /* 15.5.9.1.2 */ 155 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; 156 157 r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); 158 if (r) 159 goto err_calc_clock_div; 160 161 sdi->mgr_config.clock_info = dispc_cinfo; 162 163 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 164 165 if (pck != vm->pixelclock) { 166 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 167 vm->pixelclock, pck); 168 169 vm->pixelclock = pck; 170 } 171 172 173 dss_mgr_set_timings(&sdi->output, vm); 174 175 r = dss_set_fck_rate(sdi->dss, fck); 176 if (r) 177 goto err_set_dss_clock_div; 178 179 sdi_config_lcd_manager(sdi); 180 181 /* 182 * LCLK and PCLK divisors are located in shadow registers, and we 183 * normally write them to DISPC registers when enabling the output. 184 * However, SDI uses pck-free as source clock for its PLL, and pck-free 185 * is affected by the divisors. And as we need the PLL before enabling 186 * the output, we need to write the divisors early. 187 * 188 * It seems just writing to the DISPC register is enough, and we don't 189 * need to care about the shadow register mechanism for pck-free. The 190 * exact reason for this is unknown. 191 */ 192 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 193 &sdi->mgr_config.clock_info); 194 195 dss_sdi_init(sdi->dss, sdi->datapairs); 196 r = dss_sdi_enable(sdi->dss); 197 if (r) 198 goto err_sdi_enable; 199 mdelay(2); 200 201 r = dss_mgr_enable(&sdi->output); 202 if (r) 203 goto err_mgr_enable; 204 205 return 0; 206 207 err_mgr_enable: 208 dss_sdi_disable(sdi->dss); 209 err_sdi_enable: 210 err_set_dss_clock_div: 211 err_calc_clock_div: 212 dispc_runtime_put(sdi->dss->dispc); 213 err_get_dispc: 214 regulator_disable(sdi->vdds_sdi_reg); 215 err_reg_enable: 216 return r; 217 } 218 219 static void sdi_display_disable(struct omap_dss_device *dssdev) 220 { 221 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 222 223 dss_mgr_disable(&sdi->output); 224 225 dss_sdi_disable(sdi->dss); 226 227 dispc_runtime_put(sdi->dss->dispc); 228 229 regulator_disable(sdi->vdds_sdi_reg); 230 } 231 232 static void sdi_set_timings(struct omap_dss_device *dssdev, 233 struct videomode *vm) 234 { 235 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 236 237 sdi->vm = *vm; 238 } 239 240 static void sdi_get_timings(struct omap_dss_device *dssdev, 241 struct videomode *vm) 242 { 243 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 244 245 *vm = sdi->vm; 246 } 247 248 static int sdi_check_timings(struct omap_dss_device *dssdev, 249 struct videomode *vm) 250 { 251 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 252 enum omap_channel channel = dssdev->dispc_channel; 253 254 if (!dispc_mgr_timings_ok(sdi->dss->dispc, channel, vm)) 255 return -EINVAL; 256 257 if (vm->pixelclock == 0) 258 return -EINVAL; 259 260 return 0; 261 } 262 263 static int sdi_init_regulator(struct sdi_device *sdi) 264 { 265 struct regulator *vdds_sdi; 266 267 if (sdi->vdds_sdi_reg) 268 return 0; 269 270 vdds_sdi = devm_regulator_get(&sdi->pdev->dev, "vdds_sdi"); 271 if (IS_ERR(vdds_sdi)) { 272 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) 273 DSSERR("can't get VDDS_SDI regulator\n"); 274 return PTR_ERR(vdds_sdi); 275 } 276 277 sdi->vdds_sdi_reg = vdds_sdi; 278 279 return 0; 280 } 281 282 static int sdi_connect(struct omap_dss_device *dssdev, 283 struct omap_dss_device *dst) 284 { 285 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 286 int r; 287 288 r = sdi_init_regulator(sdi); 289 if (r) 290 return r; 291 292 r = dss_mgr_connect(&sdi->output, dssdev); 293 if (r) 294 return r; 295 296 r = omapdss_output_set_device(dssdev, dst); 297 if (r) { 298 DSSERR("failed to connect output to new device: %s\n", 299 dst->name); 300 dss_mgr_disconnect(&sdi->output, dssdev); 301 return r; 302 } 303 304 return 0; 305 } 306 307 static void sdi_disconnect(struct omap_dss_device *dssdev, 308 struct omap_dss_device *dst) 309 { 310 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 311 312 WARN_ON(dst != dssdev->dst); 313 314 if (dst != dssdev->dst) 315 return; 316 317 omapdss_output_unset_device(dssdev); 318 319 dss_mgr_disconnect(&sdi->output, dssdev); 320 } 321 322 static const struct omapdss_sdi_ops sdi_ops = { 323 .connect = sdi_connect, 324 .disconnect = sdi_disconnect, 325 326 .enable = sdi_display_enable, 327 .disable = sdi_display_disable, 328 329 .check_timings = sdi_check_timings, 330 .set_timings = sdi_set_timings, 331 .get_timings = sdi_get_timings, 332 }; 333 334 static void sdi_init_output(struct sdi_device *sdi) 335 { 336 struct omap_dss_device *out = &sdi->output; 337 338 out->dev = &sdi->pdev->dev; 339 out->id = OMAP_DSS_OUTPUT_SDI; 340 out->output_type = OMAP_DISPLAY_TYPE_SDI; 341 out->name = "sdi.0"; 342 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 343 /* We have SDI only on OMAP3, where it's on port 1 */ 344 out->port_num = 1; 345 out->ops.sdi = &sdi_ops; 346 out->owner = THIS_MODULE; 347 348 omapdss_register_output(out); 349 } 350 351 static void sdi_uninit_output(struct sdi_device *sdi) 352 { 353 omapdss_unregister_output(&sdi->output); 354 } 355 356 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 357 struct device_node *port) 358 { 359 struct sdi_device *sdi; 360 struct device_node *ep; 361 u32 datapairs; 362 int r; 363 364 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL); 365 if (!sdi) 366 return -ENOMEM; 367 368 ep = of_get_next_child(port, NULL); 369 if (!ep) { 370 r = 0; 371 goto err_free; 372 } 373 374 r = of_property_read_u32(ep, "datapairs", &datapairs); 375 if (r) { 376 DSSERR("failed to parse datapairs\n"); 377 goto err_datapairs; 378 } 379 380 sdi->datapairs = datapairs; 381 sdi->dss = dss; 382 383 of_node_put(ep); 384 385 sdi->pdev = pdev; 386 port->data = sdi; 387 388 sdi_init_output(sdi); 389 390 return 0; 391 392 err_datapairs: 393 of_node_put(ep); 394 err_free: 395 kfree(sdi); 396 397 return r; 398 } 399 400 void sdi_uninit_port(struct device_node *port) 401 { 402 struct sdi_device *sdi = port->data; 403 404 if (!sdi) 405 return; 406 407 sdi_uninit_output(sdi); 408 kfree(sdi); 409 } 410