1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define DSS_SUBSYS_NAME "SDI" 19 20 #include <linux/kernel.h> 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/export.h> 25 #include <linux/platform_device.h> 26 #include <linux/string.h> 27 #include <linux/of.h> 28 29 #include "omapdss.h" 30 #include "dss.h" 31 32 struct sdi_device { 33 struct platform_device *pdev; 34 struct dss_device *dss; 35 36 bool update_enabled; 37 struct regulator *vdds_sdi_reg; 38 39 struct dss_lcd_mgr_config mgr_config; 40 unsigned long pixelclock; 41 int datapairs; 42 43 struct omap_dss_device output; 44 }; 45 46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output) 47 48 struct sdi_clk_calc_ctx { 49 struct sdi_device *sdi; 50 unsigned long pck_min, pck_max; 51 52 unsigned long fck; 53 struct dispc_clock_info dispc_cinfo; 54 }; 55 56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 57 unsigned long pck, void *data) 58 { 59 struct sdi_clk_calc_ctx *ctx = data; 60 61 ctx->dispc_cinfo.lck_div = lckd; 62 ctx->dispc_cinfo.pck_div = pckd; 63 ctx->dispc_cinfo.lck = lck; 64 ctx->dispc_cinfo.pck = pck; 65 66 return true; 67 } 68 69 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 70 { 71 struct sdi_clk_calc_ctx *ctx = data; 72 73 ctx->fck = fck; 74 75 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 76 ctx->pck_min, ctx->pck_max, 77 dpi_calc_dispc_cb, ctx); 78 } 79 80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 81 unsigned long *fck, 82 struct dispc_clock_info *dispc_cinfo) 83 { 84 int i; 85 struct sdi_clk_calc_ctx ctx; 86 87 /* 88 * DSS fclk gives us very few possibilities, so finding a good pixel 89 * clock may not be possible. We try multiple times to find the clock, 90 * each time widening the pixel clock range we look for, up to 91 * +/- 1MHz. 92 */ 93 94 for (i = 0; i < 10; ++i) { 95 bool ok; 96 97 memset(&ctx, 0, sizeof(ctx)); 98 99 ctx.sdi = sdi; 100 101 if (pclk > 1000 * i * i * i) 102 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 103 else 104 ctx.pck_min = 0; 105 ctx.pck_max = pclk + 1000 * i * i * i; 106 107 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 108 dpi_calc_dss_cb, &ctx); 109 if (ok) { 110 *fck = ctx.fck; 111 *dispc_cinfo = ctx.dispc_cinfo; 112 return 0; 113 } 114 } 115 116 return -EINVAL; 117 } 118 119 static void sdi_config_lcd_manager(struct sdi_device *sdi) 120 { 121 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 122 123 sdi->mgr_config.stallmode = false; 124 sdi->mgr_config.fifohandcheck = false; 125 126 sdi->mgr_config.video_port_width = 24; 127 sdi->mgr_config.lcden_sig_polarity = 1; 128 129 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 130 } 131 132 static void sdi_display_enable(struct omap_dss_device *dssdev) 133 { 134 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 135 struct dispc_clock_info dispc_cinfo; 136 unsigned long fck; 137 int r; 138 139 r = regulator_enable(sdi->vdds_sdi_reg); 140 if (r) 141 return; 142 143 r = dispc_runtime_get(sdi->dss->dispc); 144 if (r) 145 goto err_get_dispc; 146 147 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo); 148 if (r) 149 goto err_calc_clock_div; 150 151 sdi->mgr_config.clock_info = dispc_cinfo; 152 153 r = dss_set_fck_rate(sdi->dss, fck); 154 if (r) 155 goto err_set_dss_clock_div; 156 157 sdi_config_lcd_manager(sdi); 158 159 /* 160 * LCLK and PCLK divisors are located in shadow registers, and we 161 * normally write them to DISPC registers when enabling the output. 162 * However, SDI uses pck-free as source clock for its PLL, and pck-free 163 * is affected by the divisors. And as we need the PLL before enabling 164 * the output, we need to write the divisors early. 165 * 166 * It seems just writing to the DISPC register is enough, and we don't 167 * need to care about the shadow register mechanism for pck-free. The 168 * exact reason for this is unknown. 169 */ 170 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 171 &sdi->mgr_config.clock_info); 172 173 dss_sdi_init(sdi->dss, sdi->datapairs); 174 r = dss_sdi_enable(sdi->dss); 175 if (r) 176 goto err_sdi_enable; 177 mdelay(2); 178 179 r = dss_mgr_enable(&sdi->output); 180 if (r) 181 goto err_mgr_enable; 182 183 return; 184 185 err_mgr_enable: 186 dss_sdi_disable(sdi->dss); 187 err_sdi_enable: 188 err_set_dss_clock_div: 189 err_calc_clock_div: 190 dispc_runtime_put(sdi->dss->dispc); 191 err_get_dispc: 192 regulator_disable(sdi->vdds_sdi_reg); 193 } 194 195 static void sdi_display_disable(struct omap_dss_device *dssdev) 196 { 197 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 198 199 dss_mgr_disable(&sdi->output); 200 201 dss_sdi_disable(sdi->dss); 202 203 dispc_runtime_put(sdi->dss->dispc); 204 205 regulator_disable(sdi->vdds_sdi_reg); 206 } 207 208 static void sdi_set_timings(struct omap_dss_device *dssdev, 209 const struct drm_display_mode *mode) 210 { 211 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 212 213 sdi->pixelclock = mode->clock * 1000; 214 } 215 216 static int sdi_check_timings(struct omap_dss_device *dssdev, 217 struct drm_display_mode *mode) 218 { 219 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 220 struct dispc_clock_info dispc_cinfo; 221 unsigned long pixelclock = mode->clock * 1000; 222 unsigned long fck; 223 unsigned long pck; 224 int r; 225 226 if (pixelclock == 0) 227 return -EINVAL; 228 229 r = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); 230 if (r) 231 return r; 232 233 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 234 235 if (pck != pixelclock) { 236 DSSWARN("Pixel clock adjusted from %lu Hz to %lu Hz\n", 237 pixelclock, pck); 238 239 mode->clock = pck / 1000; 240 } 241 242 return 0; 243 } 244 245 static int sdi_connect(struct omap_dss_device *src, 246 struct omap_dss_device *dst) 247 { 248 return omapdss_device_connect(dst->dss, dst, dst->next); 249 } 250 251 static void sdi_disconnect(struct omap_dss_device *src, 252 struct omap_dss_device *dst) 253 { 254 omapdss_device_disconnect(dst, dst->next); 255 } 256 257 static const struct omap_dss_device_ops sdi_ops = { 258 .connect = sdi_connect, 259 .disconnect = sdi_disconnect, 260 261 .enable = sdi_display_enable, 262 .disable = sdi_display_disable, 263 264 .check_timings = sdi_check_timings, 265 .set_timings = sdi_set_timings, 266 }; 267 268 static int sdi_init_output(struct sdi_device *sdi) 269 { 270 struct omap_dss_device *out = &sdi->output; 271 int r; 272 273 out->dev = &sdi->pdev->dev; 274 out->id = OMAP_DSS_OUTPUT_SDI; 275 out->type = OMAP_DISPLAY_TYPE_SDI; 276 out->name = "sdi.0"; 277 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 278 /* We have SDI only on OMAP3, where it's on port 1 */ 279 out->of_ports = BIT(1); 280 out->ops = &sdi_ops; 281 out->owner = THIS_MODULE; 282 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */ 283 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE; 284 285 r = omapdss_device_init_output(out); 286 if (r < 0) 287 return r; 288 289 omapdss_device_register(out); 290 291 return 0; 292 } 293 294 static void sdi_uninit_output(struct sdi_device *sdi) 295 { 296 omapdss_device_unregister(&sdi->output); 297 omapdss_device_cleanup_output(&sdi->output); 298 } 299 300 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 301 struct device_node *port) 302 { 303 struct sdi_device *sdi; 304 struct device_node *ep; 305 u32 datapairs; 306 int r; 307 308 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL); 309 if (!sdi) 310 return -ENOMEM; 311 312 ep = of_get_next_child(port, NULL); 313 if (!ep) { 314 r = 0; 315 goto err_free; 316 } 317 318 r = of_property_read_u32(ep, "datapairs", &datapairs); 319 of_node_put(ep); 320 if (r) { 321 DSSERR("failed to parse datapairs\n"); 322 goto err_free; 323 } 324 325 sdi->datapairs = datapairs; 326 sdi->dss = dss; 327 328 sdi->pdev = pdev; 329 port->data = sdi; 330 331 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi"); 332 if (IS_ERR(sdi->vdds_sdi_reg)) { 333 r = PTR_ERR(sdi->vdds_sdi_reg); 334 if (r != -EPROBE_DEFER) 335 DSSERR("can't get VDDS_SDI regulator\n"); 336 goto err_free; 337 } 338 339 r = sdi_init_output(sdi); 340 if (r) 341 goto err_free; 342 343 return 0; 344 345 err_free: 346 kfree(sdi); 347 348 return r; 349 } 350 351 void sdi_uninit_port(struct device_node *port) 352 { 353 struct sdi_device *sdi = port->data; 354 355 if (!sdi) 356 return; 357 358 sdi_uninit_output(sdi); 359 kfree(sdi); 360 } 361