1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define DSS_SUBSYS_NAME "SDI" 19 20 #include <linux/kernel.h> 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/export.h> 25 #include <linux/platform_device.h> 26 #include <linux/string.h> 27 #include <linux/of.h> 28 29 #include "omapdss.h" 30 #include "dss.h" 31 32 struct sdi_device { 33 struct platform_device *pdev; 34 struct dss_device *dss; 35 36 bool update_enabled; 37 struct regulator *vdds_sdi_reg; 38 39 struct dss_lcd_mgr_config mgr_config; 40 struct videomode vm; 41 int datapairs; 42 43 struct omap_dss_device output; 44 }; 45 46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output) 47 48 struct sdi_clk_calc_ctx { 49 struct sdi_device *sdi; 50 unsigned long pck_min, pck_max; 51 52 unsigned long fck; 53 struct dispc_clock_info dispc_cinfo; 54 }; 55 56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 57 unsigned long pck, void *data) 58 { 59 struct sdi_clk_calc_ctx *ctx = data; 60 61 ctx->dispc_cinfo.lck_div = lckd; 62 ctx->dispc_cinfo.pck_div = pckd; 63 ctx->dispc_cinfo.lck = lck; 64 ctx->dispc_cinfo.pck = pck; 65 66 return true; 67 } 68 69 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 70 { 71 struct sdi_clk_calc_ctx *ctx = data; 72 73 ctx->fck = fck; 74 75 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 76 ctx->pck_min, ctx->pck_max, 77 dpi_calc_dispc_cb, ctx); 78 } 79 80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 81 unsigned long *fck, 82 struct dispc_clock_info *dispc_cinfo) 83 { 84 int i; 85 struct sdi_clk_calc_ctx ctx; 86 87 /* 88 * DSS fclk gives us very few possibilities, so finding a good pixel 89 * clock may not be possible. We try multiple times to find the clock, 90 * each time widening the pixel clock range we look for, up to 91 * +/- 1MHz. 92 */ 93 94 for (i = 0; i < 10; ++i) { 95 bool ok; 96 97 memset(&ctx, 0, sizeof(ctx)); 98 99 ctx.sdi = sdi; 100 101 if (pclk > 1000 * i * i * i) 102 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 103 else 104 ctx.pck_min = 0; 105 ctx.pck_max = pclk + 1000 * i * i * i; 106 107 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 108 dpi_calc_dss_cb, &ctx); 109 if (ok) { 110 *fck = ctx.fck; 111 *dispc_cinfo = ctx.dispc_cinfo; 112 return 0; 113 } 114 } 115 116 return -EINVAL; 117 } 118 119 static void sdi_config_lcd_manager(struct sdi_device *sdi) 120 { 121 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 122 123 sdi->mgr_config.stallmode = false; 124 sdi->mgr_config.fifohandcheck = false; 125 126 sdi->mgr_config.video_port_width = 24; 127 sdi->mgr_config.lcden_sig_polarity = 1; 128 129 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 130 } 131 132 static int sdi_display_enable(struct omap_dss_device *dssdev) 133 { 134 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 135 struct dispc_clock_info dispc_cinfo; 136 unsigned long fck; 137 int r; 138 139 if (!sdi->output.dispc_channel_connected) { 140 DSSERR("failed to enable display: no output/manager\n"); 141 return -ENODEV; 142 } 143 144 r = regulator_enable(sdi->vdds_sdi_reg); 145 if (r) 146 goto err_reg_enable; 147 148 r = dispc_runtime_get(sdi->dss->dispc); 149 if (r) 150 goto err_get_dispc; 151 152 r = sdi_calc_clock_div(sdi, sdi->vm.pixelclock, &fck, &dispc_cinfo); 153 if (r) 154 goto err_calc_clock_div; 155 156 sdi->mgr_config.clock_info = dispc_cinfo; 157 158 r = dss_set_fck_rate(sdi->dss, fck); 159 if (r) 160 goto err_set_dss_clock_div; 161 162 sdi_config_lcd_manager(sdi); 163 164 /* 165 * LCLK and PCLK divisors are located in shadow registers, and we 166 * normally write them to DISPC registers when enabling the output. 167 * However, SDI uses pck-free as source clock for its PLL, and pck-free 168 * is affected by the divisors. And as we need the PLL before enabling 169 * the output, we need to write the divisors early. 170 * 171 * It seems just writing to the DISPC register is enough, and we don't 172 * need to care about the shadow register mechanism for pck-free. The 173 * exact reason for this is unknown. 174 */ 175 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 176 &sdi->mgr_config.clock_info); 177 178 dss_sdi_init(sdi->dss, sdi->datapairs); 179 r = dss_sdi_enable(sdi->dss); 180 if (r) 181 goto err_sdi_enable; 182 mdelay(2); 183 184 r = dss_mgr_enable(&sdi->output); 185 if (r) 186 goto err_mgr_enable; 187 188 return 0; 189 190 err_mgr_enable: 191 dss_sdi_disable(sdi->dss); 192 err_sdi_enable: 193 err_set_dss_clock_div: 194 err_calc_clock_div: 195 dispc_runtime_put(sdi->dss->dispc); 196 err_get_dispc: 197 regulator_disable(sdi->vdds_sdi_reg); 198 err_reg_enable: 199 return r; 200 } 201 202 static void sdi_display_disable(struct omap_dss_device *dssdev) 203 { 204 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 205 206 dss_mgr_disable(&sdi->output); 207 208 dss_sdi_disable(sdi->dss); 209 210 dispc_runtime_put(sdi->dss->dispc); 211 212 regulator_disable(sdi->vdds_sdi_reg); 213 } 214 215 static void sdi_set_timings(struct omap_dss_device *dssdev, 216 const struct videomode *vm) 217 { 218 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 219 220 sdi->vm = *vm; 221 } 222 223 static int sdi_check_timings(struct omap_dss_device *dssdev, 224 struct videomode *vm) 225 { 226 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 227 struct dispc_clock_info dispc_cinfo; 228 unsigned long fck; 229 unsigned long pck; 230 int r; 231 232 if (vm->pixelclock == 0) 233 return -EINVAL; 234 235 r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); 236 if (r) 237 return r; 238 239 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 240 241 if (pck != vm->pixelclock) { 242 DSSWARN("Pixel clock adjusted from %lu Hz to %lu Hz\n", 243 vm->pixelclock, pck); 244 245 vm->pixelclock = pck; 246 } 247 248 return 0; 249 } 250 251 static int sdi_connect(struct omap_dss_device *src, 252 struct omap_dss_device *dst) 253 { 254 int r; 255 256 r = omapdss_device_connect(dst->dss, dst, dst->next); 257 if (r) 258 return r; 259 260 dst->dispc_channel_connected = true; 261 return 0; 262 } 263 264 static void sdi_disconnect(struct omap_dss_device *src, 265 struct omap_dss_device *dst) 266 { 267 dst->dispc_channel_connected = false; 268 269 omapdss_device_disconnect(dst, dst->next); 270 } 271 272 static const struct omap_dss_device_ops sdi_ops = { 273 .connect = sdi_connect, 274 .disconnect = sdi_disconnect, 275 276 .enable = sdi_display_enable, 277 .disable = sdi_display_disable, 278 279 .check_timings = sdi_check_timings, 280 .set_timings = sdi_set_timings, 281 }; 282 283 static int sdi_init_output(struct sdi_device *sdi) 284 { 285 struct omap_dss_device *out = &sdi->output; 286 int r; 287 288 out->dev = &sdi->pdev->dev; 289 out->id = OMAP_DSS_OUTPUT_SDI; 290 out->output_type = OMAP_DISPLAY_TYPE_SDI; 291 out->name = "sdi.0"; 292 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 293 /* We have SDI only on OMAP3, where it's on port 1 */ 294 out->of_ports = BIT(1); 295 out->ops = &sdi_ops; 296 out->owner = THIS_MODULE; 297 out->bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE /* 15.5.9.1.2 */ 298 | DRM_BUS_FLAG_SYNC_POSEDGE; 299 300 out->next = omapdss_of_find_connected_device(out->dev->of_node, 1); 301 if (IS_ERR(out->next)) { 302 if (PTR_ERR(out->next) != -EPROBE_DEFER) 303 dev_err(out->dev, "failed to find video sink\n"); 304 return PTR_ERR(out->next); 305 } 306 307 r = omapdss_output_validate(out); 308 if (r) { 309 omapdss_device_put(out->next); 310 out->next = NULL; 311 return r; 312 } 313 314 omapdss_device_register(out); 315 316 return 0; 317 } 318 319 static void sdi_uninit_output(struct sdi_device *sdi) 320 { 321 if (sdi->output.next) 322 omapdss_device_put(sdi->output.next); 323 omapdss_device_unregister(&sdi->output); 324 } 325 326 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 327 struct device_node *port) 328 { 329 struct sdi_device *sdi; 330 struct device_node *ep; 331 u32 datapairs; 332 int r; 333 334 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL); 335 if (!sdi) 336 return -ENOMEM; 337 338 ep = of_get_next_child(port, NULL); 339 if (!ep) { 340 r = 0; 341 goto err_free; 342 } 343 344 r = of_property_read_u32(ep, "datapairs", &datapairs); 345 of_node_put(ep); 346 if (r) { 347 DSSERR("failed to parse datapairs\n"); 348 goto err_free; 349 } 350 351 sdi->datapairs = datapairs; 352 sdi->dss = dss; 353 354 sdi->pdev = pdev; 355 port->data = sdi; 356 357 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi"); 358 if (IS_ERR(sdi->vdds_sdi_reg)) { 359 r = PTR_ERR(sdi->vdds_sdi_reg); 360 if (r != -EPROBE_DEFER) 361 DSSERR("can't get VDDS_SDI regulator\n"); 362 goto err_free; 363 } 364 365 r = sdi_init_output(sdi); 366 if (r) 367 goto err_free; 368 369 return 0; 370 371 err_free: 372 kfree(sdi); 373 374 return r; 375 } 376 377 void sdi_uninit_port(struct device_node *port) 378 { 379 struct sdi_device *sdi = port->data; 380 381 if (!sdi) 382 return; 383 384 sdi_uninit_output(sdi); 385 kfree(sdi); 386 } 387