1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define DSS_SUBSYS_NAME "SDI" 19 20 #include <linux/kernel.h> 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/export.h> 25 #include <linux/platform_device.h> 26 #include <linux/string.h> 27 #include <linux/of.h> 28 29 #include "omapdss.h" 30 #include "dss.h" 31 32 struct sdi_device { 33 struct platform_device *pdev; 34 struct dss_device *dss; 35 36 bool update_enabled; 37 struct regulator *vdds_sdi_reg; 38 39 struct dss_lcd_mgr_config mgr_config; 40 struct videomode vm; 41 int datapairs; 42 43 struct omap_dss_device output; 44 }; 45 46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output) 47 48 struct sdi_clk_calc_ctx { 49 struct sdi_device *sdi; 50 unsigned long pck_min, pck_max; 51 52 unsigned long fck; 53 struct dispc_clock_info dispc_cinfo; 54 }; 55 56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 57 unsigned long pck, void *data) 58 { 59 struct sdi_clk_calc_ctx *ctx = data; 60 61 ctx->dispc_cinfo.lck_div = lckd; 62 ctx->dispc_cinfo.pck_div = pckd; 63 ctx->dispc_cinfo.lck = lck; 64 ctx->dispc_cinfo.pck = pck; 65 66 return true; 67 } 68 69 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 70 { 71 struct sdi_clk_calc_ctx *ctx = data; 72 73 ctx->fck = fck; 74 75 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 76 ctx->pck_min, ctx->pck_max, 77 dpi_calc_dispc_cb, ctx); 78 } 79 80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 81 unsigned long *fck, 82 struct dispc_clock_info *dispc_cinfo) 83 { 84 int i; 85 struct sdi_clk_calc_ctx ctx = { .sdi = sdi }; 86 87 /* 88 * DSS fclk gives us very few possibilities, so finding a good pixel 89 * clock may not be possible. We try multiple times to find the clock, 90 * each time widening the pixel clock range we look for, up to 91 * +/- 1MHz. 92 */ 93 94 for (i = 0; i < 10; ++i) { 95 bool ok; 96 97 memset(&ctx, 0, sizeof(ctx)); 98 if (pclk > 1000 * i * i * i) 99 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 100 else 101 ctx.pck_min = 0; 102 ctx.pck_max = pclk + 1000 * i * i * i; 103 104 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 105 dpi_calc_dss_cb, &ctx); 106 if (ok) { 107 *fck = ctx.fck; 108 *dispc_cinfo = ctx.dispc_cinfo; 109 return 0; 110 } 111 } 112 113 return -EINVAL; 114 } 115 116 static void sdi_config_lcd_manager(struct sdi_device *sdi) 117 { 118 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 119 120 sdi->mgr_config.stallmode = false; 121 sdi->mgr_config.fifohandcheck = false; 122 123 sdi->mgr_config.video_port_width = 24; 124 sdi->mgr_config.lcden_sig_polarity = 1; 125 126 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 127 } 128 129 static int sdi_display_enable(struct omap_dss_device *dssdev) 130 { 131 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 132 struct videomode *vm = &sdi->vm; 133 unsigned long fck; 134 struct dispc_clock_info dispc_cinfo; 135 unsigned long pck; 136 int r; 137 138 if (!sdi->output.dispc_channel_connected) { 139 DSSERR("failed to enable display: no output/manager\n"); 140 return -ENODEV; 141 } 142 143 r = regulator_enable(sdi->vdds_sdi_reg); 144 if (r) 145 goto err_reg_enable; 146 147 r = dispc_runtime_get(sdi->dss->dispc); 148 if (r) 149 goto err_get_dispc; 150 151 /* 15.5.9.1.2 */ 152 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; 153 154 r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); 155 if (r) 156 goto err_calc_clock_div; 157 158 sdi->mgr_config.clock_info = dispc_cinfo; 159 160 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 161 162 if (pck != vm->pixelclock) { 163 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 164 vm->pixelclock, pck); 165 166 vm->pixelclock = pck; 167 } 168 169 170 dss_mgr_set_timings(&sdi->output, vm); 171 172 r = dss_set_fck_rate(sdi->dss, fck); 173 if (r) 174 goto err_set_dss_clock_div; 175 176 sdi_config_lcd_manager(sdi); 177 178 /* 179 * LCLK and PCLK divisors are located in shadow registers, and we 180 * normally write them to DISPC registers when enabling the output. 181 * However, SDI uses pck-free as source clock for its PLL, and pck-free 182 * is affected by the divisors. And as we need the PLL before enabling 183 * the output, we need to write the divisors early. 184 * 185 * It seems just writing to the DISPC register is enough, and we don't 186 * need to care about the shadow register mechanism for pck-free. The 187 * exact reason for this is unknown. 188 */ 189 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 190 &sdi->mgr_config.clock_info); 191 192 dss_sdi_init(sdi->dss, sdi->datapairs); 193 r = dss_sdi_enable(sdi->dss); 194 if (r) 195 goto err_sdi_enable; 196 mdelay(2); 197 198 r = dss_mgr_enable(&sdi->output); 199 if (r) 200 goto err_mgr_enable; 201 202 return 0; 203 204 err_mgr_enable: 205 dss_sdi_disable(sdi->dss); 206 err_sdi_enable: 207 err_set_dss_clock_div: 208 err_calc_clock_div: 209 dispc_runtime_put(sdi->dss->dispc); 210 err_get_dispc: 211 regulator_disable(sdi->vdds_sdi_reg); 212 err_reg_enable: 213 return r; 214 } 215 216 static void sdi_display_disable(struct omap_dss_device *dssdev) 217 { 218 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 219 220 dss_mgr_disable(&sdi->output); 221 222 dss_sdi_disable(sdi->dss); 223 224 dispc_runtime_put(sdi->dss->dispc); 225 226 regulator_disable(sdi->vdds_sdi_reg); 227 } 228 229 static void sdi_set_timings(struct omap_dss_device *dssdev, 230 struct videomode *vm) 231 { 232 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 233 234 sdi->vm = *vm; 235 } 236 237 static void sdi_get_timings(struct omap_dss_device *dssdev, 238 struct videomode *vm) 239 { 240 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 241 242 *vm = sdi->vm; 243 } 244 245 static int sdi_check_timings(struct omap_dss_device *dssdev, 246 struct videomode *vm) 247 { 248 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 249 enum omap_channel channel = dssdev->dispc_channel; 250 251 if (!dispc_mgr_timings_ok(sdi->dss->dispc, channel, vm)) 252 return -EINVAL; 253 254 if (vm->pixelclock == 0) 255 return -EINVAL; 256 257 return 0; 258 } 259 260 static int sdi_init_regulator(struct sdi_device *sdi) 261 { 262 struct regulator *vdds_sdi; 263 264 if (sdi->vdds_sdi_reg) 265 return 0; 266 267 vdds_sdi = devm_regulator_get(&sdi->pdev->dev, "vdds_sdi"); 268 if (IS_ERR(vdds_sdi)) { 269 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) 270 DSSERR("can't get VDDS_SDI regulator\n"); 271 return PTR_ERR(vdds_sdi); 272 } 273 274 sdi->vdds_sdi_reg = vdds_sdi; 275 276 return 0; 277 } 278 279 static int sdi_connect(struct omap_dss_device *dssdev, 280 struct omap_dss_device *dst) 281 { 282 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 283 int r; 284 285 r = sdi_init_regulator(sdi); 286 if (r) 287 return r; 288 289 r = dss_mgr_connect(&sdi->output, dssdev); 290 if (r) 291 return r; 292 293 r = omapdss_output_set_device(dssdev, dst); 294 if (r) { 295 DSSERR("failed to connect output to new device: %s\n", 296 dst->name); 297 dss_mgr_disconnect(&sdi->output, dssdev); 298 return r; 299 } 300 301 return 0; 302 } 303 304 static void sdi_disconnect(struct omap_dss_device *dssdev, 305 struct omap_dss_device *dst) 306 { 307 struct sdi_device *sdi = dssdev_to_sdi(dssdev); 308 309 WARN_ON(dst != dssdev->dst); 310 311 if (dst != dssdev->dst) 312 return; 313 314 omapdss_output_unset_device(dssdev); 315 316 dss_mgr_disconnect(&sdi->output, dssdev); 317 } 318 319 static const struct omapdss_sdi_ops sdi_ops = { 320 .connect = sdi_connect, 321 .disconnect = sdi_disconnect, 322 323 .enable = sdi_display_enable, 324 .disable = sdi_display_disable, 325 326 .check_timings = sdi_check_timings, 327 .set_timings = sdi_set_timings, 328 .get_timings = sdi_get_timings, 329 }; 330 331 static void sdi_init_output(struct sdi_device *sdi) 332 { 333 struct omap_dss_device *out = &sdi->output; 334 335 out->dev = &sdi->pdev->dev; 336 out->id = OMAP_DSS_OUTPUT_SDI; 337 out->output_type = OMAP_DISPLAY_TYPE_SDI; 338 out->name = "sdi.0"; 339 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 340 /* We have SDI only on OMAP3, where it's on port 1 */ 341 out->port_num = 1; 342 out->ops.sdi = &sdi_ops; 343 out->owner = THIS_MODULE; 344 345 omapdss_register_output(out); 346 } 347 348 static void sdi_uninit_output(struct sdi_device *sdi) 349 { 350 omapdss_unregister_output(&sdi->output); 351 } 352 353 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 354 struct device_node *port) 355 { 356 struct sdi_device *sdi; 357 struct device_node *ep; 358 u32 datapairs; 359 int r; 360 361 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL); 362 if (!sdi) 363 return -ENOMEM; 364 365 ep = of_get_next_child(port, NULL); 366 if (!ep) { 367 r = 0; 368 goto err_free; 369 } 370 371 r = of_property_read_u32(ep, "datapairs", &datapairs); 372 if (r) { 373 DSSERR("failed to parse datapairs\n"); 374 goto err_datapairs; 375 } 376 377 sdi->datapairs = datapairs; 378 sdi->dss = dss; 379 380 of_node_put(ep); 381 382 sdi->pdev = pdev; 383 port->data = sdi; 384 385 sdi_init_output(sdi); 386 387 return 0; 388 389 err_datapairs: 390 of_node_put(ep); 391 err_free: 392 kfree(sdi); 393 394 return r; 395 } 396 397 void sdi_uninit_port(struct device_node *port) 398 { 399 struct sdi_device *sdi = port->data; 400 401 if (!sdi) 402 return; 403 404 sdi_uninit_output(sdi); 405 kfree(sdi); 406 } 407