1 /* 2 * linux/drivers/video/omap2/dss/sdi.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "SDI" 21 22 #include <linux/kernel.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/export.h> 27 #include <linux/platform_device.h> 28 #include <linux/string.h> 29 #include <linux/of.h> 30 31 #include "omapdss.h" 32 #include "dss.h" 33 34 static struct { 35 struct platform_device *pdev; 36 37 bool update_enabled; 38 struct regulator *vdds_sdi_reg; 39 40 struct dss_lcd_mgr_config mgr_config; 41 struct videomode vm; 42 int datapairs; 43 44 struct omap_dss_device output; 45 46 bool port_initialized; 47 } sdi; 48 49 struct sdi_clk_calc_ctx { 50 unsigned long pck_min, pck_max; 51 52 unsigned long fck; 53 struct dispc_clock_info dispc_cinfo; 54 }; 55 56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 57 unsigned long pck, void *data) 58 { 59 struct sdi_clk_calc_ctx *ctx = data; 60 61 ctx->dispc_cinfo.lck_div = lckd; 62 ctx->dispc_cinfo.pck_div = pckd; 63 ctx->dispc_cinfo.lck = lck; 64 ctx->dispc_cinfo.pck = pck; 65 66 return true; 67 } 68 69 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 70 { 71 struct sdi_clk_calc_ctx *ctx = data; 72 73 ctx->fck = fck; 74 75 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, 76 dpi_calc_dispc_cb, ctx); 77 } 78 79 static int sdi_calc_clock_div(unsigned long pclk, 80 unsigned long *fck, 81 struct dispc_clock_info *dispc_cinfo) 82 { 83 int i; 84 struct sdi_clk_calc_ctx ctx; 85 86 /* 87 * DSS fclk gives us very few possibilities, so finding a good pixel 88 * clock may not be possible. We try multiple times to find the clock, 89 * each time widening the pixel clock range we look for, up to 90 * +/- 1MHz. 91 */ 92 93 for (i = 0; i < 10; ++i) { 94 bool ok; 95 96 memset(&ctx, 0, sizeof(ctx)); 97 if (pclk > 1000 * i * i * i) 98 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 99 else 100 ctx.pck_min = 0; 101 ctx.pck_max = pclk + 1000 * i * i * i; 102 103 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx); 104 if (ok) { 105 *fck = ctx.fck; 106 *dispc_cinfo = ctx.dispc_cinfo; 107 return 0; 108 } 109 } 110 111 return -EINVAL; 112 } 113 114 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev) 115 { 116 enum omap_channel channel = dssdev->dispc_channel; 117 118 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 119 120 sdi.mgr_config.stallmode = false; 121 sdi.mgr_config.fifohandcheck = false; 122 123 sdi.mgr_config.video_port_width = 24; 124 sdi.mgr_config.lcden_sig_polarity = 1; 125 126 dss_mgr_set_lcd_config(channel, &sdi.mgr_config); 127 } 128 129 static int sdi_display_enable(struct omap_dss_device *dssdev) 130 { 131 struct omap_dss_device *out = &sdi.output; 132 enum omap_channel channel = dssdev->dispc_channel; 133 struct videomode *vm = &sdi.vm; 134 unsigned long fck; 135 struct dispc_clock_info dispc_cinfo; 136 unsigned long pck; 137 int r; 138 139 if (!out->dispc_channel_connected) { 140 DSSERR("failed to enable display: no output/manager\n"); 141 return -ENODEV; 142 } 143 144 r = regulator_enable(sdi.vdds_sdi_reg); 145 if (r) 146 goto err_reg_enable; 147 148 r = dispc_runtime_get(); 149 if (r) 150 goto err_get_dispc; 151 152 /* 15.5.9.1.2 */ 153 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; 154 155 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo); 156 if (r) 157 goto err_calc_clock_div; 158 159 sdi.mgr_config.clock_info = dispc_cinfo; 160 161 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 162 163 if (pck != vm->pixelclock) { 164 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 165 vm->pixelclock, pck); 166 167 vm->pixelclock = pck; 168 } 169 170 171 dss_mgr_set_timings(channel, vm); 172 173 r = dss_set_fck_rate(fck); 174 if (r) 175 goto err_set_dss_clock_div; 176 177 sdi_config_lcd_manager(dssdev); 178 179 /* 180 * LCLK and PCLK divisors are located in shadow registers, and we 181 * normally write them to DISPC registers when enabling the output. 182 * However, SDI uses pck-free as source clock for its PLL, and pck-free 183 * is affected by the divisors. And as we need the PLL before enabling 184 * the output, we need to write the divisors early. 185 * 186 * It seems just writing to the DISPC register is enough, and we don't 187 * need to care about the shadow register mechanism for pck-free. The 188 * exact reason for this is unknown. 189 */ 190 dispc_mgr_set_clock_div(channel, &sdi.mgr_config.clock_info); 191 192 dss_sdi_init(sdi.datapairs); 193 r = dss_sdi_enable(); 194 if (r) 195 goto err_sdi_enable; 196 mdelay(2); 197 198 r = dss_mgr_enable(channel); 199 if (r) 200 goto err_mgr_enable; 201 202 return 0; 203 204 err_mgr_enable: 205 dss_sdi_disable(); 206 err_sdi_enable: 207 err_set_dss_clock_div: 208 err_calc_clock_div: 209 dispc_runtime_put(); 210 err_get_dispc: 211 regulator_disable(sdi.vdds_sdi_reg); 212 err_reg_enable: 213 return r; 214 } 215 216 static void sdi_display_disable(struct omap_dss_device *dssdev) 217 { 218 enum omap_channel channel = dssdev->dispc_channel; 219 220 dss_mgr_disable(channel); 221 222 dss_sdi_disable(); 223 224 dispc_runtime_put(); 225 226 regulator_disable(sdi.vdds_sdi_reg); 227 } 228 229 static void sdi_set_timings(struct omap_dss_device *dssdev, 230 struct videomode *vm) 231 { 232 sdi.vm = *vm; 233 } 234 235 static void sdi_get_timings(struct omap_dss_device *dssdev, 236 struct videomode *vm) 237 { 238 *vm = sdi.vm; 239 } 240 241 static int sdi_check_timings(struct omap_dss_device *dssdev, 242 struct videomode *vm) 243 { 244 enum omap_channel channel = dssdev->dispc_channel; 245 246 if (!dispc_mgr_timings_ok(channel, vm)) 247 return -EINVAL; 248 249 if (vm->pixelclock == 0) 250 return -EINVAL; 251 252 return 0; 253 } 254 255 static int sdi_init_regulator(void) 256 { 257 struct regulator *vdds_sdi; 258 259 if (sdi.vdds_sdi_reg) 260 return 0; 261 262 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi"); 263 if (IS_ERR(vdds_sdi)) { 264 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) 265 DSSERR("can't get VDDS_SDI regulator\n"); 266 return PTR_ERR(vdds_sdi); 267 } 268 269 sdi.vdds_sdi_reg = vdds_sdi; 270 271 return 0; 272 } 273 274 static int sdi_connect(struct omap_dss_device *dssdev, 275 struct omap_dss_device *dst) 276 { 277 enum omap_channel channel = dssdev->dispc_channel; 278 int r; 279 280 r = sdi_init_regulator(); 281 if (r) 282 return r; 283 284 r = dss_mgr_connect(channel, dssdev); 285 if (r) 286 return r; 287 288 r = omapdss_output_set_device(dssdev, dst); 289 if (r) { 290 DSSERR("failed to connect output to new device: %s\n", 291 dst->name); 292 dss_mgr_disconnect(channel, dssdev); 293 return r; 294 } 295 296 return 0; 297 } 298 299 static void sdi_disconnect(struct omap_dss_device *dssdev, 300 struct omap_dss_device *dst) 301 { 302 enum omap_channel channel = dssdev->dispc_channel; 303 304 WARN_ON(dst != dssdev->dst); 305 306 if (dst != dssdev->dst) 307 return; 308 309 omapdss_output_unset_device(dssdev); 310 311 dss_mgr_disconnect(channel, dssdev); 312 } 313 314 static const struct omapdss_sdi_ops sdi_ops = { 315 .connect = sdi_connect, 316 .disconnect = sdi_disconnect, 317 318 .enable = sdi_display_enable, 319 .disable = sdi_display_disable, 320 321 .check_timings = sdi_check_timings, 322 .set_timings = sdi_set_timings, 323 .get_timings = sdi_get_timings, 324 }; 325 326 static void sdi_init_output(struct platform_device *pdev) 327 { 328 struct omap_dss_device *out = &sdi.output; 329 330 out->dev = &pdev->dev; 331 out->id = OMAP_DSS_OUTPUT_SDI; 332 out->output_type = OMAP_DISPLAY_TYPE_SDI; 333 out->name = "sdi.0"; 334 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 335 /* We have SDI only on OMAP3, where it's on port 1 */ 336 out->port_num = 1; 337 out->ops.sdi = &sdi_ops; 338 out->owner = THIS_MODULE; 339 340 omapdss_register_output(out); 341 } 342 343 static void sdi_uninit_output(struct platform_device *pdev) 344 { 345 struct omap_dss_device *out = &sdi.output; 346 347 omapdss_unregister_output(out); 348 } 349 350 int sdi_init_port(struct platform_device *pdev, struct device_node *port) 351 { 352 struct device_node *ep; 353 u32 datapairs; 354 int r; 355 356 ep = of_get_next_child(port, NULL); 357 if (!ep) 358 return 0; 359 360 r = of_property_read_u32(ep, "datapairs", &datapairs); 361 if (r) { 362 DSSERR("failed to parse datapairs\n"); 363 goto err_datapairs; 364 } 365 366 sdi.datapairs = datapairs; 367 368 of_node_put(ep); 369 370 sdi.pdev = pdev; 371 372 sdi_init_output(pdev); 373 374 sdi.port_initialized = true; 375 376 return 0; 377 378 err_datapairs: 379 of_node_put(ep); 380 381 return r; 382 } 383 384 void sdi_uninit_port(struct device_node *port) 385 { 386 if (!sdi.port_initialized) 387 return; 388 389 sdi_uninit_output(sdi.pdev); 390 } 391