1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #define DSS_SUBSYS_NAME "PLL" 18 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/sched.h> 24 25 #include "omapdss.h" 26 #include "dss.h" 27 28 #define PLL_CONTROL 0x0000 29 #define PLL_STATUS 0x0004 30 #define PLL_GO 0x0008 31 #define PLL_CONFIGURATION1 0x000C 32 #define PLL_CONFIGURATION2 0x0010 33 #define PLL_CONFIGURATION3 0x0014 34 #define PLL_SSC_CONFIGURATION1 0x0018 35 #define PLL_SSC_CONFIGURATION2 0x001C 36 #define PLL_CONFIGURATION4 0x0020 37 38 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) 39 { 40 int i; 41 42 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { 43 if (!dss->plls[i]) { 44 dss->plls[i] = pll; 45 pll->dss = dss; 46 return 0; 47 } 48 } 49 50 return -EBUSY; 51 } 52 53 void dss_pll_unregister(struct dss_pll *pll) 54 { 55 struct dss_device *dss = pll->dss; 56 int i; 57 58 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { 59 if (dss->plls[i] == pll) { 60 dss->plls[i] = NULL; 61 pll->dss = NULL; 62 return; 63 } 64 } 65 } 66 67 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name) 68 { 69 int i; 70 71 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { 72 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) 73 return dss->plls[i]; 74 } 75 76 return NULL; 77 } 78 79 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss, 80 enum dss_clk_source src) 81 { 82 struct dss_pll *pll; 83 84 switch (src) { 85 default: 86 case DSS_CLK_SRC_FCK: 87 return NULL; 88 89 case DSS_CLK_SRC_HDMI_PLL: 90 return dss_pll_find(dss, "hdmi"); 91 92 case DSS_CLK_SRC_PLL1_1: 93 case DSS_CLK_SRC_PLL1_2: 94 case DSS_CLK_SRC_PLL1_3: 95 pll = dss_pll_find(dss, "dsi0"); 96 if (!pll) 97 pll = dss_pll_find(dss, "video0"); 98 return pll; 99 100 case DSS_CLK_SRC_PLL2_1: 101 case DSS_CLK_SRC_PLL2_2: 102 case DSS_CLK_SRC_PLL2_3: 103 pll = dss_pll_find(dss, "dsi1"); 104 if (!pll) 105 pll = dss_pll_find(dss, "video1"); 106 return pll; 107 } 108 } 109 110 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src) 111 { 112 switch (src) { 113 case DSS_CLK_SRC_HDMI_PLL: 114 return 0; 115 116 case DSS_CLK_SRC_PLL1_1: 117 case DSS_CLK_SRC_PLL2_1: 118 return 0; 119 120 case DSS_CLK_SRC_PLL1_2: 121 case DSS_CLK_SRC_PLL2_2: 122 return 1; 123 124 case DSS_CLK_SRC_PLL1_3: 125 case DSS_CLK_SRC_PLL2_3: 126 return 2; 127 128 default: 129 return 0; 130 } 131 } 132 133 int dss_pll_enable(struct dss_pll *pll) 134 { 135 int r; 136 137 r = clk_prepare_enable(pll->clkin); 138 if (r) 139 return r; 140 141 if (pll->regulator) { 142 r = regulator_enable(pll->regulator); 143 if (r) 144 goto err_reg; 145 } 146 147 r = pll->ops->enable(pll); 148 if (r) 149 goto err_enable; 150 151 return 0; 152 153 err_enable: 154 if (pll->regulator) 155 regulator_disable(pll->regulator); 156 err_reg: 157 clk_disable_unprepare(pll->clkin); 158 return r; 159 } 160 161 void dss_pll_disable(struct dss_pll *pll) 162 { 163 pll->ops->disable(pll); 164 165 if (pll->regulator) 166 regulator_disable(pll->regulator); 167 168 clk_disable_unprepare(pll->clkin); 169 170 memset(&pll->cinfo, 0, sizeof(pll->cinfo)); 171 } 172 173 int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) 174 { 175 int r; 176 177 r = pll->ops->set_config(pll, cinfo); 178 if (r) 179 return r; 180 181 pll->cinfo = *cinfo; 182 183 return 0; 184 } 185 186 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 187 unsigned long out_min, unsigned long out_max, 188 dss_hsdiv_calc_func func, void *data) 189 { 190 const struct dss_pll_hw *hw = pll->hw; 191 int m, m_start, m_stop; 192 unsigned long out; 193 194 out_min = out_min ? out_min : 1; 195 out_max = out_max ? out_max : ULONG_MAX; 196 197 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul); 198 199 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max); 200 201 for (m = m_start; m <= m_stop; ++m) { 202 out = clkdco / m; 203 204 if (func(m, out, data)) 205 return true; 206 } 207 208 return false; 209 } 210 211 /* 212 * clkdco = clkin / n * m * 2 213 * clkoutX = clkdco / mX 214 */ 215 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 216 unsigned long pll_min, unsigned long pll_max, 217 dss_pll_calc_func func, void *data) 218 { 219 const struct dss_pll_hw *hw = pll->hw; 220 int n, n_start, n_stop, n_inc; 221 int m, m_start, m_stop, m_inc; 222 unsigned long fint, clkdco; 223 unsigned long pll_hw_max; 224 unsigned long fint_hw_min, fint_hw_max; 225 226 pll_hw_max = hw->clkdco_max; 227 228 fint_hw_min = hw->fint_min; 229 fint_hw_max = hw->fint_max; 230 231 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); 232 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); 233 n_inc = 1; 234 235 if (hw->errata_i886) { 236 swap(n_start, n_stop); 237 n_inc = -1; 238 } 239 240 pll_max = pll_max ? pll_max : ULONG_MAX; 241 242 for (n = n_start; n != n_stop; n += n_inc) { 243 fint = clkin / n; 244 245 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), 246 1ul); 247 m_stop = min3((unsigned)(pll_max / fint / 2), 248 (unsigned)(pll_hw_max / fint / 2), 249 hw->m_max); 250 m_inc = 1; 251 252 if (hw->errata_i886) { 253 swap(m_start, m_stop); 254 m_inc = -1; 255 } 256 257 for (m = m_start; m != m_stop; m += m_inc) { 258 clkdco = 2 * m * fint; 259 260 if (func(n, m, fint, clkdco, data)) 261 return true; 262 } 263 } 264 265 return false; 266 } 267 268 /* 269 * This calculates a PLL config that will provide the target_clkout rate 270 * for clkout. Additionally clkdco rate will be the same as clkout rate 271 * when clkout rate is >= min_clkdco. 272 * 273 * clkdco = clkin / n * m + clkin / n * mf / 262144 274 * clkout = clkdco / m2 275 */ 276 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 277 unsigned long target_clkout, struct dss_pll_clock_info *cinfo) 278 { 279 unsigned long fint, clkdco, clkout; 280 unsigned long target_clkdco; 281 unsigned long min_dco; 282 unsigned int n, m, mf, m2, sd; 283 const struct dss_pll_hw *hw = pll->hw; 284 285 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout); 286 287 /* Fint */ 288 n = DIV_ROUND_UP(clkin, hw->fint_max); 289 fint = clkin / n; 290 291 /* adjust m2 so that the clkdco will be high enough */ 292 min_dco = roundup(hw->clkdco_min, fint); 293 m2 = DIV_ROUND_UP(min_dco, target_clkout); 294 if (m2 == 0) 295 m2 = 1; 296 297 target_clkdco = target_clkout * m2; 298 m = target_clkdco / fint; 299 300 clkdco = fint * m; 301 302 /* adjust clkdco with fractional mf */ 303 if (WARN_ON(target_clkdco - clkdco > fint)) 304 mf = 0; 305 else 306 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); 307 308 if (mf > 0) 309 clkdco += (u32)div_u64((u64)mf * fint, 262144); 310 311 clkout = clkdco / m2; 312 313 /* sigma-delta */ 314 sd = DIV_ROUND_UP(fint * m, 250000000); 315 316 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", 317 n, m, mf, m2, sd); 318 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); 319 320 cinfo->n = n; 321 cinfo->m = m; 322 cinfo->mf = mf; 323 cinfo->mX[0] = m2; 324 cinfo->sd = sd; 325 326 cinfo->fint = fint; 327 cinfo->clkdco = clkdco; 328 cinfo->clkout[0] = clkout; 329 330 return true; 331 } 332 333 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value) 334 { 335 unsigned long timeout; 336 ktime_t wait; 337 int t; 338 339 /* first busyloop to see if the bit changes right away */ 340 t = 100; 341 while (t-- > 0) { 342 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) 343 return value; 344 } 345 346 /* then loop for 500ms, sleeping for 1ms in between */ 347 timeout = jiffies + msecs_to_jiffies(500); 348 while (time_before(jiffies, timeout)) { 349 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) 350 return value; 351 352 wait = ns_to_ktime(1000 * 1000); 353 set_current_state(TASK_UNINTERRUPTIBLE); 354 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 355 } 356 357 return !value; 358 } 359 360 int dss_pll_wait_reset_done(struct dss_pll *pll) 361 { 362 void __iomem *base = pll->base; 363 364 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) 365 return -ETIMEDOUT; 366 else 367 return 0; 368 } 369 370 static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) 371 { 372 int t = 100; 373 374 while (t-- > 0) { 375 u32 v = readl_relaxed(pll->base + PLL_STATUS); 376 v &= hsdiv_ack_mask; 377 if (v == hsdiv_ack_mask) 378 return 0; 379 } 380 381 return -ETIMEDOUT; 382 } 383 384 int dss_pll_write_config_type_a(struct dss_pll *pll, 385 const struct dss_pll_clock_info *cinfo) 386 { 387 const struct dss_pll_hw *hw = pll->hw; 388 void __iomem *base = pll->base; 389 int r = 0; 390 u32 l; 391 392 l = 0; 393 if (hw->has_stopmode) 394 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ 395 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */ 396 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */ 397 /* M4 */ 398 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, 399 hw->mX_msb[0], hw->mX_lsb[0]); 400 /* M5 */ 401 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, 402 hw->mX_msb[1], hw->mX_lsb[1]); 403 writel_relaxed(l, base + PLL_CONFIGURATION1); 404 405 l = 0; 406 /* M6 */ 407 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, 408 hw->mX_msb[2], hw->mX_lsb[2]); 409 /* M7 */ 410 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, 411 hw->mX_msb[3], hw->mX_lsb[3]); 412 writel_relaxed(l, base + PLL_CONFIGURATION3); 413 414 l = readl_relaxed(base + PLL_CONFIGURATION2); 415 if (hw->has_freqsel) { 416 u32 f = cinfo->fint < 1000000 ? 0x3 : 417 cinfo->fint < 1250000 ? 0x4 : 418 cinfo->fint < 1500000 ? 0x5 : 419 cinfo->fint < 1750000 ? 0x6 : 420 0x7; 421 422 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ 423 } else if (hw->has_selfreqdco) { 424 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4; 425 426 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ 427 } 428 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ 429 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */ 430 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */ 431 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */ 432 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */ 433 if (hw->has_refsel) 434 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */ 435 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */ 436 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */ 437 writel_relaxed(l, base + PLL_CONFIGURATION2); 438 439 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ 440 441 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { 442 DSSERR("DSS DPLL GO bit not going down.\n"); 443 r = -EIO; 444 goto err; 445 } 446 447 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { 448 DSSERR("cannot lock DSS DPLL\n"); 449 r = -EIO; 450 goto err; 451 } 452 453 l = readl_relaxed(base + PLL_CONFIGURATION2); 454 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */ 455 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */ 456 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */ 457 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */ 458 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */ 459 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */ 460 writel_relaxed(l, base + PLL_CONFIGURATION2); 461 462 r = dss_wait_hsdiv_ack(pll, 463 (cinfo->mX[0] ? BIT(7) : 0) | 464 (cinfo->mX[1] ? BIT(8) : 0) | 465 (cinfo->mX[2] ? BIT(10) : 0) | 466 (cinfo->mX[3] ? BIT(11) : 0)); 467 if (r) { 468 DSSERR("failed to enable HSDIV clocks\n"); 469 goto err; 470 } 471 472 err: 473 return r; 474 } 475 476 int dss_pll_write_config_type_b(struct dss_pll *pll, 477 const struct dss_pll_clock_info *cinfo) 478 { 479 const struct dss_pll_hw *hw = pll->hw; 480 void __iomem *base = pll->base; 481 u32 l; 482 483 l = 0; 484 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */ 485 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */ 486 writel_relaxed(l, base + PLL_CONFIGURATION1); 487 488 l = readl_relaxed(base + PLL_CONFIGURATION2); 489 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ 490 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */ 491 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */ 492 if (hw->has_refsel) 493 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */ 494 495 /* PLL_SELFREQDCO */ 496 if (cinfo->clkdco > hw->clkdco_low) 497 l = FLD_MOD(l, 0x4, 3, 1); 498 else 499 l = FLD_MOD(l, 0x2, 3, 1); 500 writel_relaxed(l, base + PLL_CONFIGURATION2); 501 502 l = readl_relaxed(base + PLL_CONFIGURATION3); 503 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */ 504 writel_relaxed(l, base + PLL_CONFIGURATION3); 505 506 l = readl_relaxed(base + PLL_CONFIGURATION4); 507 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */ 508 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */ 509 writel_relaxed(l, base + PLL_CONFIGURATION4); 510 511 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ 512 513 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { 514 DSSERR("DSS DPLL GO bit not going down.\n"); 515 return -EIO; 516 } 517 518 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { 519 DSSERR("cannot lock DSS DPLL\n"); 520 return -ETIMEDOUT; 521 } 522 523 return 0; 524 } 525