1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #define DSS_SUBSYS_NAME "PLL" 18 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/sched.h> 24 25 #include <video/omapdss.h> 26 27 #include "dss.h" 28 29 #define PLL_CONTROL 0x0000 30 #define PLL_STATUS 0x0004 31 #define PLL_GO 0x0008 32 #define PLL_CONFIGURATION1 0x000C 33 #define PLL_CONFIGURATION2 0x0010 34 #define PLL_CONFIGURATION3 0x0014 35 #define PLL_SSC_CONFIGURATION1 0x0018 36 #define PLL_SSC_CONFIGURATION2 0x001C 37 #define PLL_CONFIGURATION4 0x0020 38 39 static struct dss_pll *dss_plls[4]; 40 41 int dss_pll_register(struct dss_pll *pll) 42 { 43 int i; 44 45 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 46 if (!dss_plls[i]) { 47 dss_plls[i] = pll; 48 return 0; 49 } 50 } 51 52 return -EBUSY; 53 } 54 55 void dss_pll_unregister(struct dss_pll *pll) 56 { 57 int i; 58 59 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 60 if (dss_plls[i] == pll) { 61 dss_plls[i] = NULL; 62 return; 63 } 64 } 65 } 66 67 struct dss_pll *dss_pll_find(const char *name) 68 { 69 int i; 70 71 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 72 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) 73 return dss_plls[i]; 74 } 75 76 return NULL; 77 } 78 79 int dss_pll_enable(struct dss_pll *pll) 80 { 81 int r; 82 83 r = clk_prepare_enable(pll->clkin); 84 if (r) 85 return r; 86 87 if (pll->regulator) { 88 r = regulator_enable(pll->regulator); 89 if (r) 90 goto err_reg; 91 } 92 93 r = pll->ops->enable(pll); 94 if (r) 95 goto err_enable; 96 97 return 0; 98 99 err_enable: 100 if (pll->regulator) 101 regulator_disable(pll->regulator); 102 err_reg: 103 clk_disable_unprepare(pll->clkin); 104 return r; 105 } 106 107 void dss_pll_disable(struct dss_pll *pll) 108 { 109 pll->ops->disable(pll); 110 111 if (pll->regulator) 112 regulator_disable(pll->regulator); 113 114 clk_disable_unprepare(pll->clkin); 115 116 memset(&pll->cinfo, 0, sizeof(pll->cinfo)); 117 } 118 119 int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) 120 { 121 int r; 122 123 r = pll->ops->set_config(pll, cinfo); 124 if (r) 125 return r; 126 127 pll->cinfo = *cinfo; 128 129 return 0; 130 } 131 132 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, 133 unsigned long out_min, unsigned long out_max, 134 dss_hsdiv_calc_func func, void *data) 135 { 136 const struct dss_pll_hw *hw = pll->hw; 137 int m, m_start, m_stop; 138 unsigned long out; 139 140 out_min = out_min ? out_min : 1; 141 out_max = out_max ? out_max : ULONG_MAX; 142 143 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul); 144 145 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max); 146 147 for (m = m_start; m <= m_stop; ++m) { 148 out = clkdco / m; 149 150 if (func(m, out, data)) 151 return true; 152 } 153 154 return false; 155 } 156 157 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, 158 unsigned long pll_min, unsigned long pll_max, 159 dss_pll_calc_func func, void *data) 160 { 161 const struct dss_pll_hw *hw = pll->hw; 162 int n, n_start, n_stop; 163 int m, m_start, m_stop; 164 unsigned long fint, clkdco; 165 unsigned long pll_hw_max; 166 unsigned long fint_hw_min, fint_hw_max; 167 168 pll_hw_max = hw->clkdco_max; 169 170 fint_hw_min = hw->fint_min; 171 fint_hw_max = hw->fint_max; 172 173 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); 174 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); 175 176 pll_max = pll_max ? pll_max : ULONG_MAX; 177 178 for (n = n_start; n <= n_stop; ++n) { 179 fint = clkin / n; 180 181 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), 182 1ul); 183 m_stop = min3((unsigned)(pll_max / fint / 2), 184 (unsigned)(pll_hw_max / fint / 2), 185 hw->m_max); 186 187 for (m = m_start; m <= m_stop; ++m) { 188 clkdco = 2 * m * fint; 189 190 if (func(n, m, fint, clkdco, data)) 191 return true; 192 } 193 } 194 195 return false; 196 } 197 198 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value) 199 { 200 unsigned long timeout; 201 ktime_t wait; 202 int t; 203 204 /* first busyloop to see if the bit changes right away */ 205 t = 100; 206 while (t-- > 0) { 207 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) 208 return value; 209 } 210 211 /* then loop for 500ms, sleeping for 1ms in between */ 212 timeout = jiffies + msecs_to_jiffies(500); 213 while (time_before(jiffies, timeout)) { 214 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) 215 return value; 216 217 wait = ns_to_ktime(1000 * 1000); 218 set_current_state(TASK_UNINTERRUPTIBLE); 219 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 220 } 221 222 return !value; 223 } 224 225 int dss_pll_wait_reset_done(struct dss_pll *pll) 226 { 227 void __iomem *base = pll->base; 228 229 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) 230 return -ETIMEDOUT; 231 else 232 return 0; 233 } 234 235 static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) 236 { 237 int t = 100; 238 239 while (t-- > 0) { 240 u32 v = readl_relaxed(pll->base + PLL_STATUS); 241 v &= hsdiv_ack_mask; 242 if (v == hsdiv_ack_mask) 243 return 0; 244 } 245 246 return -ETIMEDOUT; 247 } 248 249 int dss_pll_write_config_type_a(struct dss_pll *pll, 250 const struct dss_pll_clock_info *cinfo) 251 { 252 const struct dss_pll_hw *hw = pll->hw; 253 void __iomem *base = pll->base; 254 int r = 0; 255 u32 l; 256 257 l = 0; 258 if (hw->has_stopmode) 259 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ 260 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */ 261 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */ 262 /* M4 */ 263 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, 264 hw->mX_msb[0], hw->mX_lsb[0]); 265 /* M5 */ 266 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, 267 hw->mX_msb[1], hw->mX_lsb[1]); 268 writel_relaxed(l, base + PLL_CONFIGURATION1); 269 270 l = 0; 271 /* M6 */ 272 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, 273 hw->mX_msb[2], hw->mX_lsb[2]); 274 /* M7 */ 275 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, 276 hw->mX_msb[3], hw->mX_lsb[3]); 277 writel_relaxed(l, base + PLL_CONFIGURATION3); 278 279 l = readl_relaxed(base + PLL_CONFIGURATION2); 280 if (hw->has_freqsel) { 281 u32 f = cinfo->fint < 1000000 ? 0x3 : 282 cinfo->fint < 1250000 ? 0x4 : 283 cinfo->fint < 1500000 ? 0x5 : 284 cinfo->fint < 1750000 ? 0x6 : 285 0x7; 286 287 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ 288 } else if (hw->has_selfreqdco) { 289 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4; 290 291 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ 292 } 293 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ 294 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */ 295 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */ 296 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */ 297 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */ 298 if (hw->has_refsel) 299 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */ 300 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */ 301 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */ 302 writel_relaxed(l, base + PLL_CONFIGURATION2); 303 304 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ 305 306 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { 307 DSSERR("DSS DPLL GO bit not going down.\n"); 308 r = -EIO; 309 goto err; 310 } 311 312 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { 313 DSSERR("cannot lock DSS DPLL\n"); 314 r = -EIO; 315 goto err; 316 } 317 318 l = readl_relaxed(base + PLL_CONFIGURATION2); 319 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */ 320 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */ 321 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */ 322 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */ 323 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */ 324 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */ 325 writel_relaxed(l, base + PLL_CONFIGURATION2); 326 327 r = dss_wait_hsdiv_ack(pll, 328 (cinfo->mX[0] ? BIT(7) : 0) | 329 (cinfo->mX[1] ? BIT(8) : 0) | 330 (cinfo->mX[2] ? BIT(10) : 0) | 331 (cinfo->mX[3] ? BIT(11) : 0)); 332 if (r) { 333 DSSERR("failed to enable HSDIV clocks\n"); 334 goto err; 335 } 336 337 err: 338 return r; 339 } 340 341 int dss_pll_write_config_type_b(struct dss_pll *pll, 342 const struct dss_pll_clock_info *cinfo) 343 { 344 const struct dss_pll_hw *hw = pll->hw; 345 void __iomem *base = pll->base; 346 u32 l; 347 348 l = 0; 349 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */ 350 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */ 351 writel_relaxed(l, base + PLL_CONFIGURATION1); 352 353 l = readl_relaxed(base + PLL_CONFIGURATION2); 354 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ 355 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */ 356 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */ 357 if (hw->has_refsel) 358 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */ 359 360 /* PLL_SELFREQDCO */ 361 if (cinfo->clkdco > hw->clkdco_low) 362 l = FLD_MOD(l, 0x4, 3, 1); 363 else 364 l = FLD_MOD(l, 0x2, 3, 1); 365 writel_relaxed(l, base + PLL_CONFIGURATION2); 366 367 l = readl_relaxed(base + PLL_CONFIGURATION3); 368 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */ 369 writel_relaxed(l, base + PLL_CONFIGURATION3); 370 371 l = readl_relaxed(base + PLL_CONFIGURATION4); 372 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */ 373 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */ 374 writel_relaxed(l, base + PLL_CONFIGURATION4); 375 376 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ 377 378 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { 379 DSSERR("DSS DPLL GO bit not going down.\n"); 380 return -EIO; 381 } 382 383 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { 384 DSSERR("cannot lock DSS DPLL\n"); 385 return -ETIMEDOUT; 386 } 387 388 return 0; 389 } 390