1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #ifndef __OMAP_DRM_DSS_H 8 #define __OMAP_DRM_DSS_H 9 10 #include <linux/list.h> 11 #include <linux/device.h> 12 #include <linux/interrupt.h> 13 #include <video/videomode.h> 14 #include <linux/platform_data/omapdss.h> 15 #include <uapi/drm/drm_mode.h> 16 #include <drm/drm_crtc.h> 17 18 #define DISPC_IRQ_FRAMEDONE (1 << 0) 19 #define DISPC_IRQ_VSYNC (1 << 1) 20 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 21 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 22 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 23 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 24 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 25 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 26 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 27 #define DISPC_IRQ_OCP_ERR (1 << 9) 28 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 29 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 30 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 31 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 32 #define DISPC_IRQ_SYNC_LOST (1 << 14) 33 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 34 #define DISPC_IRQ_WAKEUP (1 << 16) 35 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 36 #define DISPC_IRQ_VSYNC2 (1 << 18) 37 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 38 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 39 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 40 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 41 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 42 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 43 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 44 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) 45 #define DISPC_IRQ_SYNC_LOST3 (1 << 27) 46 #define DISPC_IRQ_VSYNC3 (1 << 28) 47 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) 48 #define DISPC_IRQ_FRAMEDONE3 (1 << 30) 49 50 struct dss_device; 51 struct omap_drm_private; 52 struct omap_dss_device; 53 struct dispc_device; 54 struct dss_device; 55 struct dss_lcd_mgr_config; 56 struct snd_aes_iec958; 57 struct snd_cea_861_aud_if; 58 struct hdmi_avi_infoframe; 59 struct drm_connector; 60 61 enum omap_display_type { 62 OMAP_DISPLAY_TYPE_NONE = 0, 63 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 64 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 65 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 66 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 67 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 68 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 69 OMAP_DISPLAY_TYPE_DVI = 1 << 6, 70 }; 71 72 enum omap_plane_id { 73 OMAP_DSS_GFX = 0, 74 OMAP_DSS_VIDEO1 = 1, 75 OMAP_DSS_VIDEO2 = 2, 76 OMAP_DSS_VIDEO3 = 3, 77 OMAP_DSS_WB = 4, 78 }; 79 80 enum omap_channel { 81 OMAP_DSS_CHANNEL_LCD = 0, 82 OMAP_DSS_CHANNEL_DIGIT = 1, 83 OMAP_DSS_CHANNEL_LCD2 = 2, 84 OMAP_DSS_CHANNEL_LCD3 = 3, 85 OMAP_DSS_CHANNEL_WB = 4, 86 }; 87 88 enum omap_color_mode { 89 _UNUSED_, 90 }; 91 92 enum omap_dss_load_mode { 93 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 94 OMAP_DSS_LOAD_CLUT_ONLY = 1, 95 OMAP_DSS_LOAD_FRAME_ONLY = 2, 96 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 97 }; 98 99 enum omap_dss_trans_key_type { 100 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 101 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 102 }; 103 104 enum omap_dss_signal_level { 105 OMAPDSS_SIG_ACTIVE_LOW, 106 OMAPDSS_SIG_ACTIVE_HIGH, 107 }; 108 109 enum omap_dss_signal_edge { 110 OMAPDSS_DRIVE_SIG_FALLING_EDGE, 111 OMAPDSS_DRIVE_SIG_RISING_EDGE, 112 }; 113 114 enum omap_dss_venc_type { 115 OMAP_DSS_VENC_TYPE_COMPOSITE, 116 OMAP_DSS_VENC_TYPE_SVIDEO, 117 }; 118 119 enum omap_dss_dsi_pixel_format { 120 OMAP_DSS_DSI_FMT_RGB888, 121 OMAP_DSS_DSI_FMT_RGB666, 122 OMAP_DSS_DSI_FMT_RGB666_PACKED, 123 OMAP_DSS_DSI_FMT_RGB565, 124 }; 125 126 enum omap_dss_dsi_mode { 127 OMAP_DSS_DSI_CMD_MODE = 0, 128 OMAP_DSS_DSI_VIDEO_MODE, 129 }; 130 131 enum omap_display_caps { 132 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 133 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 134 }; 135 136 enum omap_dss_display_state { 137 OMAP_DSS_DISPLAY_DISABLED = 0, 138 OMAP_DSS_DISPLAY_ACTIVE, 139 }; 140 141 enum omap_dss_rotation_type { 142 OMAP_DSS_ROT_NONE = 0, 143 OMAP_DSS_ROT_TILER = 1 << 0, 144 }; 145 146 enum omap_overlay_caps { 147 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 148 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 149 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 150 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 151 OMAP_DSS_OVL_CAP_POS = 1 << 4, 152 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 153 }; 154 155 enum omap_dss_output_id { 156 OMAP_DSS_OUTPUT_DPI = 1 << 0, 157 OMAP_DSS_OUTPUT_DBI = 1 << 1, 158 OMAP_DSS_OUTPUT_SDI = 1 << 2, 159 OMAP_DSS_OUTPUT_DSI1 = 1 << 3, 160 OMAP_DSS_OUTPUT_DSI2 = 1 << 4, 161 OMAP_DSS_OUTPUT_VENC = 1 << 5, 162 OMAP_DSS_OUTPUT_HDMI = 1 << 6, 163 }; 164 165 /* DSI */ 166 167 enum omap_dss_dsi_trans_mode { 168 /* Sync Pulses: both sync start and end packets sent */ 169 OMAP_DSS_DSI_PULSE_MODE, 170 /* Sync Events: only sync start packets sent */ 171 OMAP_DSS_DSI_EVENT_MODE, 172 /* Burst: only sync start packets sent, pixels are time compressed */ 173 OMAP_DSS_DSI_BURST_MODE, 174 }; 175 176 struct omap_dss_dsi_videomode_timings { 177 unsigned long hsclk; 178 179 unsigned int ndl; 180 unsigned int bitspp; 181 182 /* pixels */ 183 u16 hact; 184 /* lines */ 185 u16 vact; 186 187 /* DSI video mode blanking data */ 188 /* Unit: byte clock cycles */ 189 u16 hss; 190 u16 hsa; 191 u16 hse; 192 u16 hfp; 193 u16 hbp; 194 /* Unit: line clocks */ 195 u16 vsa; 196 u16 vfp; 197 u16 vbp; 198 199 /* DSI blanking modes */ 200 int blanking_mode; 201 int hsa_blanking_mode; 202 int hbp_blanking_mode; 203 int hfp_blanking_mode; 204 205 enum omap_dss_dsi_trans_mode trans_mode; 206 207 bool ddr_clk_always_on; 208 int window_sync; 209 }; 210 211 struct omap_dss_dsi_config { 212 enum omap_dss_dsi_mode mode; 213 enum omap_dss_dsi_pixel_format pixel_format; 214 const struct videomode *vm; 215 216 unsigned long hs_clk_min, hs_clk_max; 217 unsigned long lp_clk_min, lp_clk_max; 218 219 bool ddr_clk_always_on; 220 enum omap_dss_dsi_trans_mode trans_mode; 221 }; 222 223 struct omap_dss_cpr_coefs { 224 s16 rr, rg, rb; 225 s16 gr, gg, gb; 226 s16 br, bg, bb; 227 }; 228 229 struct omap_overlay_info { 230 dma_addr_t paddr; 231 dma_addr_t p_uv_addr; /* for NV12 format */ 232 u16 screen_width; 233 u16 width; 234 u16 height; 235 u32 fourcc; 236 u8 rotation; 237 enum omap_dss_rotation_type rotation_type; 238 239 u16 pos_x; 240 u16 pos_y; 241 u16 out_width; /* if 0, out_width == width */ 242 u16 out_height; /* if 0, out_height == height */ 243 u8 global_alpha; 244 u8 pre_mult_alpha; 245 u8 zorder; 246 }; 247 248 struct omap_overlay_manager_info { 249 u32 default_color; 250 251 enum omap_dss_trans_key_type trans_key_type; 252 u32 trans_key; 253 bool trans_enabled; 254 255 bool partial_alpha_enabled; 256 257 bool cpr_enable; 258 struct omap_dss_cpr_coefs cpr_coefs; 259 }; 260 261 /* 22 pins means 1 clk lane and 10 data lanes */ 262 #define OMAP_DSS_MAX_DSI_PINS 22 263 264 struct omap_dsi_pin_config { 265 int num_pins; 266 /* 267 * pin numbers in the following order: 268 * clk+, clk- 269 * data1+, data1- 270 * data2+, data2- 271 * ... 272 */ 273 int pins[OMAP_DSS_MAX_DSI_PINS]; 274 }; 275 276 struct omap_dss_writeback_info { 277 u32 paddr; 278 u32 p_uv_addr; 279 u16 buf_width; 280 u16 width; 281 u16 height; 282 u32 fourcc; 283 u8 rotation; 284 enum omap_dss_rotation_type rotation_type; 285 u8 pre_mult_alpha; 286 }; 287 288 struct omapdss_hdmi_ops { 289 void (*lost_hotplug)(struct omap_dss_device *dssdev); 290 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); 291 int (*set_infoframe)(struct omap_dss_device *dssdev, 292 const struct hdmi_avi_infoframe *avi); 293 }; 294 295 struct omapdss_dsi_ops { 296 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, 297 bool enter_ulps); 298 299 /* bus configuration */ 300 int (*set_config)(struct omap_dss_device *dssdev, 301 const struct omap_dss_dsi_config *cfg); 302 int (*configure_pins)(struct omap_dss_device *dssdev, 303 const struct omap_dsi_pin_config *pin_cfg); 304 305 void (*enable_hs)(struct omap_dss_device *dssdev, int channel, 306 bool enable); 307 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 308 309 int (*update)(struct omap_dss_device *dssdev, int channel, 310 void (*callback)(int, void *), void *data); 311 312 void (*bus_lock)(struct omap_dss_device *dssdev); 313 void (*bus_unlock)(struct omap_dss_device *dssdev); 314 315 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); 316 void (*disable_video_output)(struct omap_dss_device *dssdev, 317 int channel); 318 319 int (*request_vc)(struct omap_dss_device *dssdev, int *channel); 320 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, 321 int vc_id); 322 void (*release_vc)(struct omap_dss_device *dssdev, int channel); 323 324 /* data transfer */ 325 int (*dcs_write)(struct omap_dss_device *dssdev, int channel, 326 u8 *data, int len); 327 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, 328 u8 *data, int len); 329 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 330 u8 *data, int len); 331 332 int (*gen_write)(struct omap_dss_device *dssdev, int channel, 333 u8 *data, int len); 334 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, 335 u8 *data, int len); 336 int (*gen_read)(struct omap_dss_device *dssdev, int channel, 337 u8 *reqdata, int reqlen, 338 u8 *data, int len); 339 340 int (*bta_sync)(struct omap_dss_device *dssdev, int channel); 341 342 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, 343 int channel, u16 plen); 344 }; 345 346 struct omap_dss_device_ops { 347 int (*connect)(struct omap_dss_device *dssdev, 348 struct omap_dss_device *dst); 349 void (*disconnect)(struct omap_dss_device *dssdev, 350 struct omap_dss_device *dst); 351 352 void (*pre_enable)(struct omap_dss_device *dssdev); 353 void (*enable)(struct omap_dss_device *dssdev); 354 void (*disable)(struct omap_dss_device *dssdev); 355 void (*post_disable)(struct omap_dss_device *dssdev); 356 357 int (*check_timings)(struct omap_dss_device *dssdev, 358 struct drm_display_mode *mode); 359 void (*set_timings)(struct omap_dss_device *dssdev, 360 const struct drm_display_mode *mode); 361 362 bool (*detect)(struct omap_dss_device *dssdev); 363 364 void (*register_hpd_cb)(struct omap_dss_device *dssdev, 365 void (*cb)(void *cb_data, 366 enum drm_connector_status status), 367 void *cb_data); 368 void (*unregister_hpd_cb)(struct omap_dss_device *dssdev); 369 370 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 371 372 int (*get_modes)(struct omap_dss_device *dssdev, 373 struct drm_connector *connector); 374 375 union { 376 const struct omapdss_hdmi_ops hdmi; 377 const struct omapdss_dsi_ops dsi; 378 }; 379 }; 380 381 /** 382 * enum omap_dss_device_ops_flag - Indicates which device ops are supported 383 * @OMAP_DSS_DEVICE_OP_DETECT: The device supports output connection detection 384 * @OMAP_DSS_DEVICE_OP_HPD: The device supports all hot-plug-related operations 385 * @OMAP_DSS_DEVICE_OP_EDID: The device supports reading EDID 386 * @OMAP_DSS_DEVICE_OP_MODES: The device supports reading modes 387 */ 388 enum omap_dss_device_ops_flag { 389 OMAP_DSS_DEVICE_OP_DETECT = BIT(0), 390 OMAP_DSS_DEVICE_OP_HPD = BIT(1), 391 OMAP_DSS_DEVICE_OP_EDID = BIT(2), 392 OMAP_DSS_DEVICE_OP_MODES = BIT(3), 393 }; 394 395 struct omap_dss_device { 396 struct device *dev; 397 398 struct module *owner; 399 400 struct dss_device *dss; 401 struct omap_dss_device *next; 402 struct drm_bridge *bridge; 403 struct drm_panel *panel; 404 405 struct list_head list; 406 407 /* 408 * DSS type that this device generates (for DSS internal devices) or 409 * requires (for external encoders, connectors and panels). Must be a 410 * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value. 411 */ 412 enum omap_display_type type; 413 414 /* 415 * True if the device is a display (panel or connector) at the end of 416 * the pipeline, false otherwise. 417 */ 418 bool display; 419 420 const char *name; 421 422 const struct omap_dss_driver *driver; 423 const struct omap_dss_device_ops *ops; 424 unsigned long ops_flags; 425 u32 bus_flags; 426 427 enum omap_display_caps caps; 428 429 enum omap_dss_display_state state; 430 431 /* OMAP DSS output specific fields */ 432 433 /* DISPC channel for this output */ 434 enum omap_channel dispc_channel; 435 436 /* output instance */ 437 enum omap_dss_output_id id; 438 439 /* bitmask of port numbers in DT */ 440 unsigned int of_ports; 441 }; 442 443 struct omap_dss_driver { 444 int (*update)(struct omap_dss_device *dssdev, 445 u16 x, u16 y, u16 w, u16 h); 446 int (*sync)(struct omap_dss_device *dssdev); 447 448 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 449 int (*get_te)(struct omap_dss_device *dssdev); 450 451 int (*memory_read)(struct omap_dss_device *dssdev, 452 void *buf, size_t size, 453 u16 x, u16 y, u16 w, u16 h); 454 }; 455 456 struct dss_device *omapdss_get_dss(void); 457 void omapdss_set_dss(struct dss_device *dss); 458 static inline bool omapdss_is_initialized(void) 459 { 460 return !!omapdss_get_dss(); 461 } 462 463 void omapdss_display_init(struct omap_dss_device *dssdev); 464 struct omap_dss_device *omapdss_display_get(struct omap_dss_device *output); 465 int omapdss_display_get_modes(struct drm_connector *connector, 466 const struct videomode *vm); 467 468 void omapdss_device_register(struct omap_dss_device *dssdev); 469 void omapdss_device_unregister(struct omap_dss_device *dssdev); 470 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev); 471 void omapdss_device_put(struct omap_dss_device *dssdev); 472 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node); 473 int omapdss_device_connect(struct dss_device *dss, 474 struct omap_dss_device *src, 475 struct omap_dss_device *dst); 476 void omapdss_device_disconnect(struct omap_dss_device *src, 477 struct omap_dss_device *dst); 478 void omapdss_device_pre_enable(struct omap_dss_device *dssdev); 479 void omapdss_device_enable(struct omap_dss_device *dssdev); 480 void omapdss_device_disable(struct omap_dss_device *dssdev); 481 void omapdss_device_post_disable(struct omap_dss_device *dssdev); 482 483 int omap_dss_get_num_overlay_managers(void); 484 485 int omap_dss_get_num_overlays(void); 486 487 #define for_each_dss_output(d) \ 488 while ((d = omapdss_device_next_output(d)) != NULL) 489 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from); 490 int omapdss_device_init_output(struct omap_dss_device *out); 491 void omapdss_device_cleanup_output(struct omap_dss_device *out); 492 493 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 494 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 495 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 496 497 int omapdss_compat_init(void); 498 void omapdss_compat_uninit(void); 499 500 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) 501 { 502 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; 503 } 504 505 struct omap_dss_device * 506 omapdss_of_find_connected_device(struct device_node *node, unsigned int port); 507 508 enum dss_writeback_channel { 509 DSS_WB_LCD1_MGR = 0, 510 DSS_WB_LCD2_MGR = 1, 511 DSS_WB_TV_MGR = 2, 512 DSS_WB_OVL0 = 3, 513 DSS_WB_OVL1 = 4, 514 DSS_WB_OVL2 = 5, 515 DSS_WB_OVL3 = 6, 516 DSS_WB_LCD3_MGR = 7, 517 }; 518 519 struct dss_mgr_ops { 520 void (*start_update)(struct omap_drm_private *priv, 521 enum omap_channel channel); 522 int (*enable)(struct omap_drm_private *priv, 523 enum omap_channel channel); 524 void (*disable)(struct omap_drm_private *priv, 525 enum omap_channel channel); 526 void (*set_timings)(struct omap_drm_private *priv, 527 enum omap_channel channel, 528 const struct videomode *vm); 529 void (*set_lcd_config)(struct omap_drm_private *priv, 530 enum omap_channel channel, 531 const struct dss_lcd_mgr_config *config); 532 int (*register_framedone_handler)(struct omap_drm_private *priv, 533 enum omap_channel channel, 534 void (*handler)(void *), void *data); 535 void (*unregister_framedone_handler)(struct omap_drm_private *priv, 536 enum omap_channel channel, 537 void (*handler)(void *), void *data); 538 }; 539 540 int dss_install_mgr_ops(struct dss_device *dss, 541 const struct dss_mgr_ops *mgr_ops, 542 struct omap_drm_private *priv); 543 void dss_uninstall_mgr_ops(struct dss_device *dss); 544 545 void dss_mgr_set_timings(struct omap_dss_device *dssdev, 546 const struct videomode *vm); 547 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev, 548 const struct dss_lcd_mgr_config *config); 549 int dss_mgr_enable(struct omap_dss_device *dssdev); 550 void dss_mgr_disable(struct omap_dss_device *dssdev); 551 void dss_mgr_start_update(struct omap_dss_device *dssdev); 552 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev, 553 void (*handler)(void *), void *data); 554 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev, 555 void (*handler)(void *), void *data); 556 557 /* dispc ops */ 558 559 struct dispc_ops { 560 u32 (*read_irqstatus)(struct dispc_device *dispc); 561 void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask); 562 void (*write_irqenable)(struct dispc_device *dispc, u32 mask); 563 564 int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler, 565 void *dev_id); 566 void (*free_irq)(struct dispc_device *dispc, void *dev_id); 567 568 int (*runtime_get)(struct dispc_device *dispc); 569 void (*runtime_put)(struct dispc_device *dispc); 570 571 int (*get_num_ovls)(struct dispc_device *dispc); 572 int (*get_num_mgrs)(struct dispc_device *dispc); 573 574 u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc); 575 576 void (*mgr_enable)(struct dispc_device *dispc, 577 enum omap_channel channel, bool enable); 578 bool (*mgr_is_enabled)(struct dispc_device *dispc, 579 enum omap_channel channel); 580 u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc, 581 enum omap_channel channel); 582 u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc, 583 enum omap_channel channel); 584 u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc, 585 enum omap_channel channel); 586 bool (*mgr_go_busy)(struct dispc_device *dispc, 587 enum omap_channel channel); 588 void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel); 589 void (*mgr_set_lcd_config)(struct dispc_device *dispc, 590 enum omap_channel channel, 591 const struct dss_lcd_mgr_config *config); 592 int (*mgr_check_timings)(struct dispc_device *dispc, 593 enum omap_channel channel, 594 const struct videomode *vm); 595 void (*mgr_set_timings)(struct dispc_device *dispc, 596 enum omap_channel channel, 597 const struct videomode *vm); 598 void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel, 599 const struct omap_overlay_manager_info *info); 600 u32 (*mgr_gamma_size)(struct dispc_device *dispc, 601 enum omap_channel channel); 602 void (*mgr_set_gamma)(struct dispc_device *dispc, 603 enum omap_channel channel, 604 const struct drm_color_lut *lut, 605 unsigned int length); 606 607 int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane, 608 bool enable); 609 int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane, 610 const struct omap_overlay_info *oi, 611 const struct videomode *vm, bool mem_to_mem, 612 enum omap_channel channel); 613 614 const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc, 615 enum omap_plane_id plane); 616 617 u32 (*wb_get_framedone_irq)(struct dispc_device *dispc); 618 int (*wb_setup)(struct dispc_device *dispc, 619 const struct omap_dss_writeback_info *wi, 620 bool mem_to_mem, const struct videomode *vm, 621 enum dss_writeback_channel channel_in); 622 bool (*has_writeback)(struct dispc_device *dispc); 623 bool (*wb_go_busy)(struct dispc_device *dispc); 624 void (*wb_go)(struct dispc_device *dispc); 625 }; 626 627 struct dispc_device *dispc_get_dispc(struct dss_device *dss); 628 const struct dispc_ops *dispc_get_ops(struct dss_device *dss); 629 630 bool omapdss_stack_is_ready(void); 631 void omapdss_gather_components(struct device *dev); 632 633 #endif /* __OMAP_DRM_DSS_H */ 634