1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #ifndef __OMAP_DRM_DSS_H 8 #define __OMAP_DRM_DSS_H 9 10 #include <drm/drm_color_mgmt.h> 11 #include <drm/drm_crtc.h> 12 #include <drm/drm_mode.h> 13 #include <linux/device.h> 14 #include <linux/interrupt.h> 15 #include <linux/list.h> 16 #include <linux/platform_data/omapdss.h> 17 #include <video/videomode.h> 18 19 #define DISPC_IRQ_FRAMEDONE (1 << 0) 20 #define DISPC_IRQ_VSYNC (1 << 1) 21 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 22 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 23 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 24 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 25 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 26 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 27 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 28 #define DISPC_IRQ_OCP_ERR (1 << 9) 29 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 30 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 31 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 32 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 33 #define DISPC_IRQ_SYNC_LOST (1 << 14) 34 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 35 #define DISPC_IRQ_WAKEUP (1 << 16) 36 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 37 #define DISPC_IRQ_VSYNC2 (1 << 18) 38 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 39 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 40 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 41 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 42 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 43 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 44 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 45 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) 46 #define DISPC_IRQ_SYNC_LOST3 (1 << 27) 47 #define DISPC_IRQ_VSYNC3 (1 << 28) 48 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) 49 #define DISPC_IRQ_FRAMEDONE3 (1 << 30) 50 51 struct dss_device; 52 struct omap_drm_private; 53 struct omap_dss_device; 54 struct dispc_device; 55 struct dss_device; 56 struct dss_lcd_mgr_config; 57 struct snd_aes_iec958; 58 struct snd_cea_861_aud_if; 59 struct hdmi_avi_infoframe; 60 struct drm_connector; 61 62 enum omap_display_type { 63 OMAP_DISPLAY_TYPE_NONE = 0, 64 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 65 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 66 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 67 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 68 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 69 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 70 OMAP_DISPLAY_TYPE_DVI = 1 << 6, 71 }; 72 73 enum omap_plane_id { 74 OMAP_DSS_GFX = 0, 75 OMAP_DSS_VIDEO1 = 1, 76 OMAP_DSS_VIDEO2 = 2, 77 OMAP_DSS_VIDEO3 = 3, 78 OMAP_DSS_WB = 4, 79 }; 80 81 enum omap_channel { 82 OMAP_DSS_CHANNEL_LCD = 0, 83 OMAP_DSS_CHANNEL_DIGIT = 1, 84 OMAP_DSS_CHANNEL_LCD2 = 2, 85 OMAP_DSS_CHANNEL_LCD3 = 3, 86 OMAP_DSS_CHANNEL_WB = 4, 87 }; 88 89 enum omap_color_mode { 90 _UNUSED_, 91 }; 92 93 enum omap_dss_load_mode { 94 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 95 OMAP_DSS_LOAD_CLUT_ONLY = 1, 96 OMAP_DSS_LOAD_FRAME_ONLY = 2, 97 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 98 }; 99 100 enum omap_dss_trans_key_type { 101 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 102 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 103 }; 104 105 enum omap_dss_signal_level { 106 OMAPDSS_SIG_ACTIVE_LOW, 107 OMAPDSS_SIG_ACTIVE_HIGH, 108 }; 109 110 enum omap_dss_signal_edge { 111 OMAPDSS_DRIVE_SIG_FALLING_EDGE, 112 OMAPDSS_DRIVE_SIG_RISING_EDGE, 113 }; 114 115 enum omap_dss_venc_type { 116 OMAP_DSS_VENC_TYPE_COMPOSITE, 117 OMAP_DSS_VENC_TYPE_SVIDEO, 118 }; 119 120 enum omap_dss_rotation_type { 121 OMAP_DSS_ROT_NONE = 0, 122 OMAP_DSS_ROT_TILER = 1 << 0, 123 }; 124 125 enum omap_overlay_caps { 126 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 127 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 128 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 129 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 130 OMAP_DSS_OVL_CAP_POS = 1 << 4, 131 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 132 }; 133 134 enum omap_dss_output_id { 135 OMAP_DSS_OUTPUT_DPI = 1 << 0, 136 OMAP_DSS_OUTPUT_DBI = 1 << 1, 137 OMAP_DSS_OUTPUT_SDI = 1 << 2, 138 OMAP_DSS_OUTPUT_DSI1 = 1 << 3, 139 OMAP_DSS_OUTPUT_DSI2 = 1 << 4, 140 OMAP_DSS_OUTPUT_VENC = 1 << 5, 141 OMAP_DSS_OUTPUT_HDMI = 1 << 6, 142 }; 143 144 struct omap_dss_cpr_coefs { 145 s16 rr, rg, rb; 146 s16 gr, gg, gb; 147 s16 br, bg, bb; 148 }; 149 150 struct omap_overlay_info { 151 dma_addr_t paddr; 152 dma_addr_t p_uv_addr; /* for NV12 format */ 153 u16 screen_width; 154 u16 width; 155 u16 height; 156 u32 fourcc; 157 u8 rotation; 158 enum omap_dss_rotation_type rotation_type; 159 160 u16 pos_x; 161 u16 pos_y; 162 u16 out_width; /* if 0, out_width == width */ 163 u16 out_height; /* if 0, out_height == height */ 164 u8 global_alpha; 165 u8 pre_mult_alpha; 166 u8 zorder; 167 168 enum drm_color_encoding color_encoding; 169 enum drm_color_range color_range; 170 }; 171 172 struct omap_overlay_manager_info { 173 u32 default_color; 174 175 enum omap_dss_trans_key_type trans_key_type; 176 u32 trans_key; 177 bool trans_enabled; 178 179 bool partial_alpha_enabled; 180 181 bool cpr_enable; 182 struct omap_dss_cpr_coefs cpr_coefs; 183 }; 184 185 struct omap_dss_writeback_info { 186 u32 paddr; 187 u32 p_uv_addr; 188 u16 buf_width; 189 u16 width; 190 u16 height; 191 u32 fourcc; 192 u8 rotation; 193 enum omap_dss_rotation_type rotation_type; 194 u8 pre_mult_alpha; 195 }; 196 197 struct omapdss_dsi_ops { 198 int (*update)(struct omap_dss_device *dssdev); 199 bool (*is_video_mode)(struct omap_dss_device *dssdev); 200 }; 201 202 struct omap_dss_device { 203 struct device *dev; 204 205 struct dss_device *dss; 206 struct drm_bridge *bridge; 207 struct drm_bridge *next_bridge; 208 struct drm_panel *panel; 209 210 struct list_head list; 211 212 /* 213 * DSS type that this device generates (for DSS internal devices) or 214 * requires (for external encoders, connectors and panels). Must be a 215 * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value. 216 */ 217 enum omap_display_type type; 218 219 const char *name; 220 221 const struct omapdss_dsi_ops *dsi_ops; 222 u32 bus_flags; 223 224 /* OMAP DSS output specific fields */ 225 226 /* DISPC channel for this output */ 227 enum omap_channel dispc_channel; 228 229 /* output instance */ 230 enum omap_dss_output_id id; 231 232 /* port number in DT */ 233 unsigned int of_port; 234 }; 235 236 struct dss_pdata { 237 struct dss_device *dss; 238 }; 239 240 void omapdss_device_register(struct omap_dss_device *dssdev); 241 void omapdss_device_unregister(struct omap_dss_device *dssdev); 242 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev); 243 void omapdss_device_put(struct omap_dss_device *dssdev); 244 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node); 245 int omapdss_device_connect(struct dss_device *dss, 246 struct omap_dss_device *src, 247 struct omap_dss_device *dst); 248 void omapdss_device_disconnect(struct omap_dss_device *src, 249 struct omap_dss_device *dst); 250 251 int omap_dss_get_num_overlay_managers(void); 252 253 int omap_dss_get_num_overlays(void); 254 255 #define for_each_dss_output(d) \ 256 while ((d = omapdss_device_next_output(d)) != NULL) 257 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from); 258 int omapdss_device_init_output(struct omap_dss_device *out, 259 struct drm_bridge *local_bridge); 260 void omapdss_device_cleanup_output(struct omap_dss_device *out); 261 262 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 263 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 264 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 265 266 int omapdss_compat_init(void); 267 void omapdss_compat_uninit(void); 268 269 enum dss_writeback_channel { 270 DSS_WB_LCD1_MGR = 0, 271 DSS_WB_LCD2_MGR = 1, 272 DSS_WB_TV_MGR = 2, 273 DSS_WB_OVL0 = 3, 274 DSS_WB_OVL1 = 4, 275 DSS_WB_OVL2 = 5, 276 DSS_WB_OVL3 = 6, 277 DSS_WB_LCD3_MGR = 7, 278 }; 279 280 void omap_crtc_dss_start_update(struct omap_drm_private *priv, 281 enum omap_channel channel); 282 void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable); 283 int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel); 284 void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel); 285 void omap_crtc_dss_set_timings(struct omap_drm_private *priv, 286 enum omap_channel channel, 287 const struct videomode *vm); 288 void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv, 289 enum omap_channel channel, 290 const struct dss_lcd_mgr_config *config); 291 int omap_crtc_dss_register_framedone( 292 struct omap_drm_private *priv, enum omap_channel channel, 293 void (*handler)(void *), void *data); 294 void omap_crtc_dss_unregister_framedone( 295 struct omap_drm_private *priv, enum omap_channel channel, 296 void (*handler)(void *), void *data); 297 298 void dss_mgr_set_timings(struct omap_dss_device *dssdev, 299 const struct videomode *vm); 300 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev, 301 const struct dss_lcd_mgr_config *config); 302 int dss_mgr_enable(struct omap_dss_device *dssdev); 303 void dss_mgr_disable(struct omap_dss_device *dssdev); 304 void dss_mgr_start_update(struct omap_dss_device *dssdev); 305 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev, 306 void (*handler)(void *), void *data); 307 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev, 308 void (*handler)(void *), void *data); 309 310 struct dispc_device *dispc_get_dispc(struct dss_device *dss); 311 312 bool omapdss_stack_is_ready(void); 313 void omapdss_gather_components(struct device *dev); 314 315 int omap_dss_init(void); 316 void omap_dss_exit(void); 317 318 #endif /* __OMAP_DRM_DSS_H */ 319