1 /* 2 * Copyright (C) 2016 Texas Instruments 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __OMAP_DRM_DSS_H 19 #define __OMAP_DRM_DSS_H 20 21 #include <linux/list.h> 22 #include <linux/kobject.h> 23 #include <linux/device.h> 24 #include <linux/interrupt.h> 25 #include <video/videomode.h> 26 #include <linux/platform_data/omapdss.h> 27 #include <uapi/drm/drm_mode.h> 28 29 #define DISPC_IRQ_FRAMEDONE (1 << 0) 30 #define DISPC_IRQ_VSYNC (1 << 1) 31 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 32 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 33 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 34 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 35 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 36 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 37 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 38 #define DISPC_IRQ_OCP_ERR (1 << 9) 39 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 40 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 41 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 42 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 43 #define DISPC_IRQ_SYNC_LOST (1 << 14) 44 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 45 #define DISPC_IRQ_WAKEUP (1 << 16) 46 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 47 #define DISPC_IRQ_VSYNC2 (1 << 18) 48 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 49 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 50 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 51 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 52 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 53 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 54 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 55 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) 56 #define DISPC_IRQ_SYNC_LOST3 (1 << 27) 57 #define DISPC_IRQ_VSYNC3 (1 << 28) 58 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) 59 #define DISPC_IRQ_FRAMEDONE3 (1 << 30) 60 61 struct omap_dss_device; 62 struct omap_overlay_manager; 63 struct dss_lcd_mgr_config; 64 struct snd_aes_iec958; 65 struct snd_cea_861_aud_if; 66 struct hdmi_avi_infoframe; 67 68 enum omap_display_type { 69 OMAP_DISPLAY_TYPE_NONE = 0, 70 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 71 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 72 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 73 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 74 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 75 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 76 OMAP_DISPLAY_TYPE_DVI = 1 << 6, 77 }; 78 79 enum omap_plane { 80 OMAP_DSS_GFX = 0, 81 OMAP_DSS_VIDEO1 = 1, 82 OMAP_DSS_VIDEO2 = 2, 83 OMAP_DSS_VIDEO3 = 3, 84 OMAP_DSS_WB = 4, 85 }; 86 87 enum omap_channel { 88 OMAP_DSS_CHANNEL_LCD = 0, 89 OMAP_DSS_CHANNEL_DIGIT = 1, 90 OMAP_DSS_CHANNEL_LCD2 = 2, 91 OMAP_DSS_CHANNEL_LCD3 = 3, 92 OMAP_DSS_CHANNEL_WB = 4, 93 }; 94 95 enum omap_color_mode { 96 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ 97 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ 98 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ 99 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ 100 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ 101 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ 102 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ 103 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ 104 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ 105 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ 106 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ 107 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ 108 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ 109 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ 110 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ 111 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ 112 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ 113 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ 114 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ 115 }; 116 117 enum omap_dss_load_mode { 118 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 119 OMAP_DSS_LOAD_CLUT_ONLY = 1, 120 OMAP_DSS_LOAD_FRAME_ONLY = 2, 121 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 122 }; 123 124 enum omap_dss_trans_key_type { 125 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 126 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 127 }; 128 129 enum omap_rfbi_te_mode { 130 OMAP_DSS_RFBI_TE_MODE_1 = 1, 131 OMAP_DSS_RFBI_TE_MODE_2 = 2, 132 }; 133 134 enum omap_dss_signal_level { 135 OMAPDSS_SIG_ACTIVE_LOW, 136 OMAPDSS_SIG_ACTIVE_HIGH, 137 }; 138 139 enum omap_dss_signal_edge { 140 OMAPDSS_DRIVE_SIG_FALLING_EDGE, 141 OMAPDSS_DRIVE_SIG_RISING_EDGE, 142 }; 143 144 enum omap_dss_venc_type { 145 OMAP_DSS_VENC_TYPE_COMPOSITE, 146 OMAP_DSS_VENC_TYPE_SVIDEO, 147 }; 148 149 enum omap_dss_dsi_pixel_format { 150 OMAP_DSS_DSI_FMT_RGB888, 151 OMAP_DSS_DSI_FMT_RGB666, 152 OMAP_DSS_DSI_FMT_RGB666_PACKED, 153 OMAP_DSS_DSI_FMT_RGB565, 154 }; 155 156 enum omap_dss_dsi_mode { 157 OMAP_DSS_DSI_CMD_MODE = 0, 158 OMAP_DSS_DSI_VIDEO_MODE, 159 }; 160 161 enum omap_display_caps { 162 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 163 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 164 }; 165 166 enum omap_dss_display_state { 167 OMAP_DSS_DISPLAY_DISABLED = 0, 168 OMAP_DSS_DISPLAY_ACTIVE, 169 }; 170 171 enum omap_dss_rotation_type { 172 OMAP_DSS_ROT_DMA = 1 << 0, 173 OMAP_DSS_ROT_VRFB = 1 << 1, 174 OMAP_DSS_ROT_TILER = 1 << 2, 175 }; 176 177 /* clockwise rotation angle */ 178 enum omap_dss_rotation_angle { 179 OMAP_DSS_ROT_0 = 0, 180 OMAP_DSS_ROT_90 = 1, 181 OMAP_DSS_ROT_180 = 2, 182 OMAP_DSS_ROT_270 = 3, 183 }; 184 185 enum omap_overlay_caps { 186 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 187 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 188 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 189 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 190 OMAP_DSS_OVL_CAP_POS = 1 << 4, 191 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 192 }; 193 194 enum omap_overlay_manager_caps { 195 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ 196 }; 197 198 enum omap_dss_clk_source { 199 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 200 * OMAP4: DSS_FCLK */ 201 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 202 * OMAP4: PLL1_CLK1 */ 203 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 204 * OMAP4: PLL1_CLK2 */ 205 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 207 }; 208 209 enum omap_hdmi_flags { 210 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 211 }; 212 213 enum omap_dss_output_id { 214 OMAP_DSS_OUTPUT_DPI = 1 << 0, 215 OMAP_DSS_OUTPUT_DBI = 1 << 1, 216 OMAP_DSS_OUTPUT_SDI = 1 << 2, 217 OMAP_DSS_OUTPUT_DSI1 = 1 << 3, 218 OMAP_DSS_OUTPUT_DSI2 = 1 << 4, 219 OMAP_DSS_OUTPUT_VENC = 1 << 5, 220 OMAP_DSS_OUTPUT_HDMI = 1 << 6, 221 }; 222 223 /* RFBI */ 224 225 struct rfbi_timings { 226 int cs_on_time; 227 int cs_off_time; 228 int we_on_time; 229 int we_off_time; 230 int re_on_time; 231 int re_off_time; 232 int we_cycle_time; 233 int re_cycle_time; 234 int cs_pulse_width; 235 int access_time; 236 237 int clk_div; 238 239 u32 tim[5]; /* set by rfbi_convert_timings() */ 240 241 int converted; 242 }; 243 244 /* DSI */ 245 246 enum omap_dss_dsi_trans_mode { 247 /* Sync Pulses: both sync start and end packets sent */ 248 OMAP_DSS_DSI_PULSE_MODE, 249 /* Sync Events: only sync start packets sent */ 250 OMAP_DSS_DSI_EVENT_MODE, 251 /* Burst: only sync start packets sent, pixels are time compressed */ 252 OMAP_DSS_DSI_BURST_MODE, 253 }; 254 255 struct omap_dss_dsi_videomode_timings { 256 unsigned long hsclk; 257 258 unsigned ndl; 259 unsigned bitspp; 260 261 /* pixels */ 262 u16 hact; 263 /* lines */ 264 u16 vact; 265 266 /* DSI video mode blanking data */ 267 /* Unit: byte clock cycles */ 268 u16 hss; 269 u16 hsa; 270 u16 hse; 271 u16 hfp; 272 u16 hbp; 273 /* Unit: line clocks */ 274 u16 vsa; 275 u16 vfp; 276 u16 vbp; 277 278 /* DSI blanking modes */ 279 int blanking_mode; 280 int hsa_blanking_mode; 281 int hbp_blanking_mode; 282 int hfp_blanking_mode; 283 284 enum omap_dss_dsi_trans_mode trans_mode; 285 286 bool ddr_clk_always_on; 287 int window_sync; 288 }; 289 290 struct omap_dss_dsi_config { 291 enum omap_dss_dsi_mode mode; 292 enum omap_dss_dsi_pixel_format pixel_format; 293 const struct omap_video_timings *timings; 294 295 unsigned long hs_clk_min, hs_clk_max; 296 unsigned long lp_clk_min, lp_clk_max; 297 298 bool ddr_clk_always_on; 299 enum omap_dss_dsi_trans_mode trans_mode; 300 }; 301 302 struct omap_video_timings { 303 /* Unit: pixels */ 304 u16 x_res; 305 /* Unit: pixels */ 306 u16 y_res; 307 /* Unit: Hz */ 308 u32 pixelclock; 309 /* Unit: pixel clocks */ 310 u16 hsw; /* Horizontal synchronization pulse width */ 311 /* Unit: pixel clocks */ 312 u16 hfp; /* Horizontal front porch */ 313 /* Unit: pixel clocks */ 314 u16 hbp; /* Horizontal back porch */ 315 /* Unit: line clocks */ 316 u16 vsw; /* Vertical synchronization pulse width */ 317 /* Unit: line clocks */ 318 u16 vfp; /* Vertical front porch */ 319 /* Unit: line clocks */ 320 u16 vbp; /* Vertical back porch */ 321 322 /* Vsync logic level */ 323 enum omap_dss_signal_level vsync_level; 324 /* Hsync logic level */ 325 enum omap_dss_signal_level hsync_level; 326 /* Interlaced or Progressive timings */ 327 bool interlace; 328 /* Pixel clock edge to drive LCD data */ 329 enum omap_dss_signal_edge data_pclk_edge; 330 /* Data enable logic level */ 331 enum omap_dss_signal_level de_level; 332 /* Pixel clock edges to drive HSYNC and VSYNC signals */ 333 enum omap_dss_signal_edge sync_pclk_edge; 334 335 bool double_pixel; 336 }; 337 338 /* Hardcoded timings for tv modes. Venc only uses these to 339 * identify the mode, and does not actually use the configs 340 * itself. However, the configs should be something that 341 * a normal monitor can also show */ 342 extern const struct omap_video_timings omap_dss_pal_timings; 343 extern const struct omap_video_timings omap_dss_ntsc_timings; 344 345 struct omap_dss_cpr_coefs { 346 s16 rr, rg, rb; 347 s16 gr, gg, gb; 348 s16 br, bg, bb; 349 }; 350 351 struct omap_overlay_info { 352 dma_addr_t paddr; 353 dma_addr_t p_uv_addr; /* for NV12 format */ 354 u16 screen_width; 355 u16 width; 356 u16 height; 357 enum omap_color_mode color_mode; 358 u8 rotation; 359 enum omap_dss_rotation_type rotation_type; 360 bool mirror; 361 362 u16 pos_x; 363 u16 pos_y; 364 u16 out_width; /* if 0, out_width == width */ 365 u16 out_height; /* if 0, out_height == height */ 366 u8 global_alpha; 367 u8 pre_mult_alpha; 368 u8 zorder; 369 }; 370 371 struct omap_overlay { 372 struct kobject kobj; 373 struct list_head list; 374 375 /* static fields */ 376 const char *name; 377 enum omap_plane id; 378 enum omap_color_mode supported_modes; 379 enum omap_overlay_caps caps; 380 381 /* dynamic fields */ 382 struct omap_overlay_manager *manager; 383 384 /* 385 * The following functions do not block: 386 * 387 * is_enabled 388 * set_overlay_info 389 * get_overlay_info 390 * 391 * The rest of the functions may block and cannot be called from 392 * interrupt context 393 */ 394 395 int (*enable)(struct omap_overlay *ovl); 396 int (*disable)(struct omap_overlay *ovl); 397 bool (*is_enabled)(struct omap_overlay *ovl); 398 399 int (*set_manager)(struct omap_overlay *ovl, 400 struct omap_overlay_manager *mgr); 401 int (*unset_manager)(struct omap_overlay *ovl); 402 403 int (*set_overlay_info)(struct omap_overlay *ovl, 404 struct omap_overlay_info *info); 405 void (*get_overlay_info)(struct omap_overlay *ovl, 406 struct omap_overlay_info *info); 407 408 int (*wait_for_go)(struct omap_overlay *ovl); 409 410 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); 411 }; 412 413 struct omap_overlay_manager_info { 414 u32 default_color; 415 416 enum omap_dss_trans_key_type trans_key_type; 417 u32 trans_key; 418 bool trans_enabled; 419 420 bool partial_alpha_enabled; 421 422 bool cpr_enable; 423 struct omap_dss_cpr_coefs cpr_coefs; 424 }; 425 426 struct omap_overlay_manager { 427 struct kobject kobj; 428 429 /* static fields */ 430 const char *name; 431 enum omap_channel id; 432 enum omap_overlay_manager_caps caps; 433 struct list_head overlays; 434 enum omap_display_type supported_displays; 435 enum omap_dss_output_id supported_outputs; 436 437 /* dynamic fields */ 438 struct omap_dss_device *output; 439 440 /* 441 * The following functions do not block: 442 * 443 * set_manager_info 444 * get_manager_info 445 * apply 446 * 447 * The rest of the functions may block and cannot be called from 448 * interrupt context 449 */ 450 451 int (*set_output)(struct omap_overlay_manager *mgr, 452 struct omap_dss_device *output); 453 int (*unset_output)(struct omap_overlay_manager *mgr); 454 455 int (*set_manager_info)(struct omap_overlay_manager *mgr, 456 struct omap_overlay_manager_info *info); 457 void (*get_manager_info)(struct omap_overlay_manager *mgr, 458 struct omap_overlay_manager_info *info); 459 460 int (*apply)(struct omap_overlay_manager *mgr); 461 int (*wait_for_go)(struct omap_overlay_manager *mgr); 462 int (*wait_for_vsync)(struct omap_overlay_manager *mgr); 463 464 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); 465 }; 466 467 /* 22 pins means 1 clk lane and 10 data lanes */ 468 #define OMAP_DSS_MAX_DSI_PINS 22 469 470 struct omap_dsi_pin_config { 471 int num_pins; 472 /* 473 * pin numbers in the following order: 474 * clk+, clk- 475 * data1+, data1- 476 * data2+, data2- 477 * ... 478 */ 479 int pins[OMAP_DSS_MAX_DSI_PINS]; 480 }; 481 482 struct omap_dss_writeback_info { 483 u32 paddr; 484 u32 p_uv_addr; 485 u16 buf_width; 486 u16 width; 487 u16 height; 488 enum omap_color_mode color_mode; 489 u8 rotation; 490 enum omap_dss_rotation_type rotation_type; 491 bool mirror; 492 u8 pre_mult_alpha; 493 }; 494 495 struct omapdss_dpi_ops { 496 int (*connect)(struct omap_dss_device *dssdev, 497 struct omap_dss_device *dst); 498 void (*disconnect)(struct omap_dss_device *dssdev, 499 struct omap_dss_device *dst); 500 501 int (*enable)(struct omap_dss_device *dssdev); 502 void (*disable)(struct omap_dss_device *dssdev); 503 504 int (*check_timings)(struct omap_dss_device *dssdev, 505 struct omap_video_timings *timings); 506 void (*set_timings)(struct omap_dss_device *dssdev, 507 struct omap_video_timings *timings); 508 void (*get_timings)(struct omap_dss_device *dssdev, 509 struct omap_video_timings *timings); 510 511 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); 512 }; 513 514 struct omapdss_sdi_ops { 515 int (*connect)(struct omap_dss_device *dssdev, 516 struct omap_dss_device *dst); 517 void (*disconnect)(struct omap_dss_device *dssdev, 518 struct omap_dss_device *dst); 519 520 int (*enable)(struct omap_dss_device *dssdev); 521 void (*disable)(struct omap_dss_device *dssdev); 522 523 int (*check_timings)(struct omap_dss_device *dssdev, 524 struct omap_video_timings *timings); 525 void (*set_timings)(struct omap_dss_device *dssdev, 526 struct omap_video_timings *timings); 527 void (*get_timings)(struct omap_dss_device *dssdev, 528 struct omap_video_timings *timings); 529 530 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); 531 }; 532 533 struct omapdss_dvi_ops { 534 int (*connect)(struct omap_dss_device *dssdev, 535 struct omap_dss_device *dst); 536 void (*disconnect)(struct omap_dss_device *dssdev, 537 struct omap_dss_device *dst); 538 539 int (*enable)(struct omap_dss_device *dssdev); 540 void (*disable)(struct omap_dss_device *dssdev); 541 542 int (*check_timings)(struct omap_dss_device *dssdev, 543 struct omap_video_timings *timings); 544 void (*set_timings)(struct omap_dss_device *dssdev, 545 struct omap_video_timings *timings); 546 void (*get_timings)(struct omap_dss_device *dssdev, 547 struct omap_video_timings *timings); 548 }; 549 550 struct omapdss_atv_ops { 551 int (*connect)(struct omap_dss_device *dssdev, 552 struct omap_dss_device *dst); 553 void (*disconnect)(struct omap_dss_device *dssdev, 554 struct omap_dss_device *dst); 555 556 int (*enable)(struct omap_dss_device *dssdev); 557 void (*disable)(struct omap_dss_device *dssdev); 558 559 int (*check_timings)(struct omap_dss_device *dssdev, 560 struct omap_video_timings *timings); 561 void (*set_timings)(struct omap_dss_device *dssdev, 562 struct omap_video_timings *timings); 563 void (*get_timings)(struct omap_dss_device *dssdev, 564 struct omap_video_timings *timings); 565 566 void (*set_type)(struct omap_dss_device *dssdev, 567 enum omap_dss_venc_type type); 568 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev, 569 bool invert_polarity); 570 571 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 572 u32 (*get_wss)(struct omap_dss_device *dssdev); 573 }; 574 575 struct omapdss_hdmi_ops { 576 int (*connect)(struct omap_dss_device *dssdev, 577 struct omap_dss_device *dst); 578 void (*disconnect)(struct omap_dss_device *dssdev, 579 struct omap_dss_device *dst); 580 581 int (*enable)(struct omap_dss_device *dssdev); 582 void (*disable)(struct omap_dss_device *dssdev); 583 584 int (*check_timings)(struct omap_dss_device *dssdev, 585 struct omap_video_timings *timings); 586 void (*set_timings)(struct omap_dss_device *dssdev, 587 struct omap_video_timings *timings); 588 void (*get_timings)(struct omap_dss_device *dssdev, 589 struct omap_video_timings *timings); 590 591 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 592 bool (*detect)(struct omap_dss_device *dssdev); 593 594 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); 595 int (*set_infoframe)(struct omap_dss_device *dssdev, 596 const struct hdmi_avi_infoframe *avi); 597 }; 598 599 struct omapdss_dsi_ops { 600 int (*connect)(struct omap_dss_device *dssdev, 601 struct omap_dss_device *dst); 602 void (*disconnect)(struct omap_dss_device *dssdev, 603 struct omap_dss_device *dst); 604 605 int (*enable)(struct omap_dss_device *dssdev); 606 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, 607 bool enter_ulps); 608 609 /* bus configuration */ 610 int (*set_config)(struct omap_dss_device *dssdev, 611 const struct omap_dss_dsi_config *cfg); 612 int (*configure_pins)(struct omap_dss_device *dssdev, 613 const struct omap_dsi_pin_config *pin_cfg); 614 615 void (*enable_hs)(struct omap_dss_device *dssdev, int channel, 616 bool enable); 617 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 618 619 int (*update)(struct omap_dss_device *dssdev, int channel, 620 void (*callback)(int, void *), void *data); 621 622 void (*bus_lock)(struct omap_dss_device *dssdev); 623 void (*bus_unlock)(struct omap_dss_device *dssdev); 624 625 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); 626 void (*disable_video_output)(struct omap_dss_device *dssdev, 627 int channel); 628 629 int (*request_vc)(struct omap_dss_device *dssdev, int *channel); 630 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, 631 int vc_id); 632 void (*release_vc)(struct omap_dss_device *dssdev, int channel); 633 634 /* data transfer */ 635 int (*dcs_write)(struct omap_dss_device *dssdev, int channel, 636 u8 *data, int len); 637 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, 638 u8 *data, int len); 639 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 640 u8 *data, int len); 641 642 int (*gen_write)(struct omap_dss_device *dssdev, int channel, 643 u8 *data, int len); 644 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, 645 u8 *data, int len); 646 int (*gen_read)(struct omap_dss_device *dssdev, int channel, 647 u8 *reqdata, int reqlen, 648 u8 *data, int len); 649 650 int (*bta_sync)(struct omap_dss_device *dssdev, int channel); 651 652 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, 653 int channel, u16 plen); 654 }; 655 656 struct omap_dss_device { 657 struct kobject kobj; 658 struct device *dev; 659 660 struct module *owner; 661 662 struct list_head panel_list; 663 664 /* alias in the form of "display%d" */ 665 char alias[16]; 666 667 enum omap_display_type type; 668 enum omap_display_type output_type; 669 670 union { 671 struct { 672 u8 data_lines; 673 } dpi; 674 675 struct { 676 u8 channel; 677 u8 data_lines; 678 } rfbi; 679 680 struct { 681 u8 datapairs; 682 } sdi; 683 684 struct { 685 int module; 686 } dsi; 687 688 struct { 689 enum omap_dss_venc_type type; 690 bool invert_polarity; 691 } venc; 692 } phy; 693 694 struct { 695 struct omap_video_timings timings; 696 697 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 698 enum omap_dss_dsi_mode dsi_mode; 699 } panel; 700 701 struct { 702 u8 pixel_size; 703 struct rfbi_timings rfbi_timings; 704 } ctrl; 705 706 const char *name; 707 708 /* used to match device to driver */ 709 const char *driver_name; 710 711 void *data; 712 713 struct omap_dss_driver *driver; 714 715 union { 716 const struct omapdss_dpi_ops *dpi; 717 const struct omapdss_sdi_ops *sdi; 718 const struct omapdss_dvi_ops *dvi; 719 const struct omapdss_hdmi_ops *hdmi; 720 const struct omapdss_atv_ops *atv; 721 const struct omapdss_dsi_ops *dsi; 722 } ops; 723 724 /* helper variable for driver suspend/resume */ 725 bool activate_after_resume; 726 727 enum omap_display_caps caps; 728 729 struct omap_dss_device *src; 730 731 enum omap_dss_display_state state; 732 733 /* OMAP DSS output specific fields */ 734 735 struct list_head list; 736 737 /* DISPC channel for this output */ 738 enum omap_channel dispc_channel; 739 bool dispc_channel_connected; 740 741 /* output instance */ 742 enum omap_dss_output_id id; 743 744 /* the port number in the DT node */ 745 int port_num; 746 747 /* dynamic fields */ 748 struct omap_overlay_manager *manager; 749 750 struct omap_dss_device *dst; 751 }; 752 753 struct omap_dss_driver { 754 int (*probe)(struct omap_dss_device *); 755 void (*remove)(struct omap_dss_device *); 756 757 int (*connect)(struct omap_dss_device *dssdev); 758 void (*disconnect)(struct omap_dss_device *dssdev); 759 760 int (*enable)(struct omap_dss_device *display); 761 void (*disable)(struct omap_dss_device *display); 762 int (*run_test)(struct omap_dss_device *display, int test); 763 764 int (*update)(struct omap_dss_device *dssdev, 765 u16 x, u16 y, u16 w, u16 h); 766 int (*sync)(struct omap_dss_device *dssdev); 767 768 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 769 int (*get_te)(struct omap_dss_device *dssdev); 770 771 u8 (*get_rotate)(struct omap_dss_device *dssdev); 772 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); 773 774 bool (*get_mirror)(struct omap_dss_device *dssdev); 775 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); 776 777 int (*memory_read)(struct omap_dss_device *dssdev, 778 void *buf, size_t size, 779 u16 x, u16 y, u16 w, u16 h); 780 781 void (*get_resolution)(struct omap_dss_device *dssdev, 782 u16 *xres, u16 *yres); 783 void (*get_dimensions)(struct omap_dss_device *dssdev, 784 u32 *width, u32 *height); 785 int (*get_recommended_bpp)(struct omap_dss_device *dssdev); 786 787 int (*check_timings)(struct omap_dss_device *dssdev, 788 struct omap_video_timings *timings); 789 void (*set_timings)(struct omap_dss_device *dssdev, 790 struct omap_video_timings *timings); 791 void (*get_timings)(struct omap_dss_device *dssdev, 792 struct omap_video_timings *timings); 793 794 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 795 u32 (*get_wss)(struct omap_dss_device *dssdev); 796 797 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 798 bool (*detect)(struct omap_dss_device *dssdev); 799 800 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); 801 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev, 802 const struct hdmi_avi_infoframe *avi); 803 }; 804 805 enum omapdss_version omapdss_get_version(void); 806 bool omapdss_is_initialized(void); 807 808 int omap_dss_register_driver(struct omap_dss_driver *); 809 void omap_dss_unregister_driver(struct omap_dss_driver *); 810 811 int omapdss_register_display(struct omap_dss_device *dssdev); 812 void omapdss_unregister_display(struct omap_dss_device *dssdev); 813 814 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev); 815 void omap_dss_put_device(struct omap_dss_device *dssdev); 816 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) 817 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); 818 struct omap_dss_device *omap_dss_find_device(void *data, 819 int (*match)(struct omap_dss_device *dssdev, void *data)); 820 const char *omapdss_get_default_display_name(void); 821 822 void videomode_to_omap_video_timings(const struct videomode *vm, 823 struct omap_video_timings *ovt); 824 void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, 825 struct videomode *vm); 826 827 int dss_feat_get_num_mgrs(void); 828 int dss_feat_get_num_ovls(void); 829 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); 830 831 832 833 int omap_dss_get_num_overlay_managers(void); 834 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); 835 836 int omap_dss_get_num_overlays(void); 837 struct omap_overlay *omap_dss_get_overlay(int num); 838 839 int omapdss_register_output(struct omap_dss_device *output); 840 void omapdss_unregister_output(struct omap_dss_device *output); 841 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); 842 struct omap_dss_device *omap_dss_find_output(const char *name); 843 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port); 844 int omapdss_output_set_device(struct omap_dss_device *out, 845 struct omap_dss_device *dssdev); 846 int omapdss_output_unset_device(struct omap_dss_device *out); 847 848 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); 849 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); 850 851 void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 852 u16 *xres, u16 *yres); 853 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 854 void omapdss_default_get_timings(struct omap_dss_device *dssdev, 855 struct omap_video_timings *timings); 856 857 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 858 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 859 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 860 861 int omapdss_compat_init(void); 862 void omapdss_compat_uninit(void); 863 864 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) 865 { 866 return dssdev->src; 867 } 868 869 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) 870 { 871 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; 872 } 873 874 struct device_node * 875 omapdss_of_get_next_port(const struct device_node *parent, 876 struct device_node *prev); 877 878 struct device_node * 879 omapdss_of_get_next_endpoint(const struct device_node *parent, 880 struct device_node *prev); 881 882 struct device_node * 883 omapdss_of_get_first_endpoint(const struct device_node *parent); 884 885 struct omap_dss_device * 886 omapdss_of_find_source_for_first_ep(struct device_node *node); 887 888 u32 dispc_read_irqstatus(void); 889 void dispc_clear_irqstatus(u32 mask); 890 u32 dispc_read_irqenable(void); 891 void dispc_write_irqenable(u32 mask); 892 893 int dispc_request_irq(irq_handler_t handler, void *dev_id); 894 void dispc_free_irq(void *dev_id); 895 896 int dispc_runtime_get(void); 897 void dispc_runtime_put(void); 898 899 void dispc_mgr_enable(enum omap_channel channel, bool enable); 900 bool dispc_mgr_is_enabled(enum omap_channel channel); 901 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); 902 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); 903 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); 904 bool dispc_mgr_go_busy(enum omap_channel channel); 905 void dispc_mgr_go(enum omap_channel channel); 906 void dispc_mgr_set_lcd_config(enum omap_channel channel, 907 const struct dss_lcd_mgr_config *config); 908 void dispc_mgr_set_timings(enum omap_channel channel, 909 const struct omap_video_timings *timings); 910 void dispc_mgr_setup(enum omap_channel channel, 911 const struct omap_overlay_manager_info *info); 912 u32 dispc_mgr_gamma_size(enum omap_channel channel); 913 void dispc_mgr_set_gamma(enum omap_channel channel, 914 const struct drm_color_lut *lut, 915 unsigned int length); 916 917 int dispc_ovl_enable(enum omap_plane plane, bool enable); 918 bool dispc_ovl_enabled(enum omap_plane plane); 919 void dispc_ovl_set_channel_out(enum omap_plane plane, 920 enum omap_channel channel); 921 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 922 bool replication, const struct omap_video_timings *mgr_timings, 923 bool mem_to_mem); 924 925 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); 926 927 struct dss_mgr_ops { 928 int (*connect)(enum omap_channel channel, 929 struct omap_dss_device *dst); 930 void (*disconnect)(enum omap_channel channel, 931 struct omap_dss_device *dst); 932 933 void (*start_update)(enum omap_channel channel); 934 int (*enable)(enum omap_channel channel); 935 void (*disable)(enum omap_channel channel); 936 void (*set_timings)(enum omap_channel channel, 937 const struct omap_video_timings *timings); 938 void (*set_lcd_config)(enum omap_channel channel, 939 const struct dss_lcd_mgr_config *config); 940 int (*register_framedone_handler)(enum omap_channel channel, 941 void (*handler)(void *), void *data); 942 void (*unregister_framedone_handler)(enum omap_channel channel, 943 void (*handler)(void *), void *data); 944 }; 945 946 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); 947 void dss_uninstall_mgr_ops(void); 948 949 int dss_mgr_connect(enum omap_channel channel, 950 struct omap_dss_device *dst); 951 void dss_mgr_disconnect(enum omap_channel channel, 952 struct omap_dss_device *dst); 953 void dss_mgr_set_timings(enum omap_channel channel, 954 const struct omap_video_timings *timings); 955 void dss_mgr_set_lcd_config(enum omap_channel channel, 956 const struct dss_lcd_mgr_config *config); 957 int dss_mgr_enable(enum omap_channel channel); 958 void dss_mgr_disable(enum omap_channel channel); 959 void dss_mgr_start_update(enum omap_channel channel); 960 int dss_mgr_register_framedone_handler(enum omap_channel channel, 961 void (*handler)(void *), void *data); 962 void dss_mgr_unregister_framedone_handler(enum omap_channel channel, 963 void (*handler)(void *), void *data); 964 965 #endif /* __OMAP_DRM_DSS_H */ 966