xref: /openbmc/linux/drivers/gpu/drm/omapdrm/dss/omapdss.h (revision 23c2b932)
1 /*
2  * Copyright (C) 2016 Texas Instruments
3  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published by
7  * the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17 
18 #ifndef __OMAP_DRM_DSS_H
19 #define __OMAP_DRM_DSS_H
20 
21 #include <video/omapdss.h>
22 
23 u32 dispc_read_irqstatus(void);
24 void dispc_clear_irqstatus(u32 mask);
25 u32 dispc_read_irqenable(void);
26 void dispc_write_irqenable(u32 mask);
27 
28 int dispc_request_irq(irq_handler_t handler, void *dev_id);
29 void dispc_free_irq(void *dev_id);
30 
31 int dispc_runtime_get(void);
32 void dispc_runtime_put(void);
33 
34 void dispc_mgr_enable(enum omap_channel channel, bool enable);
35 bool dispc_mgr_is_enabled(enum omap_channel channel);
36 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
37 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
38 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
39 bool dispc_mgr_go_busy(enum omap_channel channel);
40 void dispc_mgr_go(enum omap_channel channel);
41 void dispc_mgr_set_lcd_config(enum omap_channel channel,
42 		const struct dss_lcd_mgr_config *config);
43 void dispc_mgr_set_timings(enum omap_channel channel,
44 		const struct omap_video_timings *timings);
45 void dispc_mgr_setup(enum omap_channel channel,
46 		const struct omap_overlay_manager_info *info);
47 
48 int dispc_ovl_enable(enum omap_plane plane, bool enable);
49 bool dispc_ovl_enabled(enum omap_plane plane);
50 void dispc_ovl_set_channel_out(enum omap_plane plane,
51 		enum omap_channel channel);
52 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
53 		bool replication, const struct omap_video_timings *mgr_timings,
54 		bool mem_to_mem);
55 
56 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
57 
58 struct dss_mgr_ops {
59 	int (*connect)(enum omap_channel channel,
60 		struct omap_dss_device *dst);
61 	void (*disconnect)(enum omap_channel channel,
62 		struct omap_dss_device *dst);
63 
64 	void (*start_update)(enum omap_channel channel);
65 	int (*enable)(enum omap_channel channel);
66 	void (*disable)(enum omap_channel channel);
67 	void (*set_timings)(enum omap_channel channel,
68 			const struct omap_video_timings *timings);
69 	void (*set_lcd_config)(enum omap_channel channel,
70 			const struct dss_lcd_mgr_config *config);
71 	int (*register_framedone_handler)(enum omap_channel channel,
72 			void (*handler)(void *), void *data);
73 	void (*unregister_framedone_handler)(enum omap_channel channel,
74 			void (*handler)(void *), void *data);
75 };
76 
77 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
78 void dss_uninstall_mgr_ops(void);
79 
80 int dss_mgr_connect(enum omap_channel channel,
81 		struct omap_dss_device *dst);
82 void dss_mgr_disconnect(enum omap_channel channel,
83 		struct omap_dss_device *dst);
84 void dss_mgr_set_timings(enum omap_channel channel,
85 		const struct omap_video_timings *timings);
86 void dss_mgr_set_lcd_config(enum omap_channel channel,
87 		const struct dss_lcd_mgr_config *config);
88 int dss_mgr_enable(enum omap_channel channel);
89 void dss_mgr_disable(enum omap_channel channel);
90 void dss_mgr_start_update(enum omap_channel channel);
91 int dss_mgr_register_framedone_handler(enum omap_channel channel,
92 		void (*handler)(void *), void *data);
93 void dss_mgr_unregister_framedone_handler(enum omap_channel channel,
94 		void (*handler)(void *), void *data);
95 
96 #endif /* __OMAP_DRM_DSS_H */
97