1 /* 2 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * Authors: Yong Zhi 6 * Mythri pk <mythripk@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "HDMICORE" 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/interrupt.h> 28 #include <linux/mutex.h> 29 #include <linux/delay.h> 30 #include <linux/platform_device.h> 31 #include <linux/string.h> 32 #include <linux/seq_file.h> 33 #include <linux/sys_soc.h> 34 #include <sound/asound.h> 35 #include <sound/asoundef.h> 36 37 #include "hdmi4_core.h" 38 39 #define HDMI_CORE_AV 0x500 40 41 static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) 42 { 43 return core->base + HDMI_CORE_AV; 44 } 45 46 static int hdmi_core_ddc_init(struct hdmi_core_data *core) 47 { 48 void __iomem *base = core->base; 49 50 /* Turn on CLK for DDC */ 51 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); 52 53 /* IN_PROG */ 54 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { 55 /* Abort transaction */ 56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); 57 /* IN_PROG */ 58 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 59 4, 4, 0) != 0) { 60 DSSERR("Timeout aborting DDC transaction\n"); 61 return -ETIMEDOUT; 62 } 63 } 64 65 /* Clk SCL Devices */ 66 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); 67 68 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 69 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 70 4, 4, 0) != 0) { 71 DSSERR("Timeout starting SCL clock\n"); 72 return -ETIMEDOUT; 73 } 74 75 /* Clear FIFO */ 76 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); 77 78 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 79 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 80 4, 4, 0) != 0) { 81 DSSERR("Timeout clearing DDC fifo\n"); 82 return -ETIMEDOUT; 83 } 84 85 return 0; 86 } 87 88 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, 89 u8 *pedid, int ext) 90 { 91 void __iomem *base = core->base; 92 u32 i; 93 char checksum; 94 u32 offset = 0; 95 96 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 97 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 98 4, 4, 0) != 0) { 99 DSSERR("Timeout waiting DDC to be ready\n"); 100 return -ETIMEDOUT; 101 } 102 103 if (ext % 2 != 0) 104 offset = 0x80; 105 106 /* Load Segment Address Register */ 107 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); 108 109 /* Load Slave Address Register */ 110 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 111 112 /* Load Offset Address Register */ 113 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); 114 115 /* Load Byte Count */ 116 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 117 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 118 119 /* Set DDC_CMD */ 120 if (ext) 121 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); 122 else 123 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); 124 125 /* HDMI_CORE_DDC_STATUS_BUS_LOW */ 126 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { 127 DSSERR("I2C Bus Low?\n"); 128 return -EIO; 129 } 130 /* HDMI_CORE_DDC_STATUS_NO_ACK */ 131 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { 132 DSSERR("I2C No Ack\n"); 133 return -EIO; 134 } 135 136 for (i = 0; i < 0x80; ++i) { 137 int t; 138 139 /* IN_PROG */ 140 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { 141 DSSERR("operation stopped when reading edid\n"); 142 return -EIO; 143 } 144 145 t = 0; 146 /* FIFO_EMPTY */ 147 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { 148 if (t++ > 10000) { 149 DSSERR("timeout reading edid\n"); 150 return -ETIMEDOUT; 151 } 152 udelay(1); 153 } 154 155 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); 156 } 157 158 checksum = 0; 159 for (i = 0; i < 0x80; ++i) 160 checksum += pedid[i]; 161 162 if (checksum != 0) { 163 DSSERR("E-EDID checksum failed!!\n"); 164 return -EIO; 165 } 166 167 return 0; 168 } 169 170 int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 171 { 172 int r, l; 173 174 if (len < 128) 175 return -EINVAL; 176 177 r = hdmi_core_ddc_init(core); 178 if (r) 179 return r; 180 181 r = hdmi_core_ddc_edid(core, edid, 0); 182 if (r) 183 return r; 184 185 l = 128; 186 187 if (len >= 128 * 2 && edid[0x7e] > 0) { 188 r = hdmi_core_ddc_edid(core, edid + 0x80, 1); 189 if (r) 190 return r; 191 l += 128; 192 } 193 194 return l; 195 } 196 197 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg) 198 { 199 DSSDBG("Enter hdmi_core_init\n"); 200 201 /* video core */ 202 video_cfg->ip_bus_width = HDMI_INPUT_8BIT; 203 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; 204 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; 205 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; 206 video_cfg->hdmi_dvi = HDMI_DVI; 207 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; 208 } 209 210 void hdmi4_core_powerdown_disable(struct hdmi_core_data *core) 211 { 212 DSSDBG("Enter hdmi4_core_powerdown_disable\n"); 213 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0); 214 } 215 216 static void hdmi_core_swreset_release(struct hdmi_core_data *core) 217 { 218 DSSDBG("Enter hdmi_core_swreset_release\n"); 219 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); 220 } 221 222 static void hdmi_core_swreset_assert(struct hdmi_core_data *core) 223 { 224 DSSDBG("Enter hdmi_core_swreset_assert\n"); 225 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); 226 } 227 228 /* HDMI_CORE_VIDEO_CONFIG */ 229 static void hdmi_core_video_config(struct hdmi_core_data *core, 230 struct hdmi_core_video_config *cfg) 231 { 232 u32 r = 0; 233 void __iomem *core_sys_base = core->base; 234 void __iomem *core_av_base = hdmi_av_base(core); 235 236 /* sys_ctrl1 default configuration not tunable */ 237 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); 238 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); 239 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); 240 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); 241 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); 242 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); 243 244 REG_FLD_MOD(core_sys_base, 245 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); 246 247 /* Vid_Mode */ 248 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); 249 250 /* dither truncation configuration */ 251 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { 252 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); 253 r = FLD_MOD(r, 1, 5, 5); 254 } else { 255 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); 256 r = FLD_MOD(r, 0, 5, 5); 257 } 258 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); 259 260 /* HDMI_Ctrl */ 261 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); 262 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); 263 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); 264 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); 265 hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); 266 267 /* TMDS_CTRL */ 268 REG_FLD_MOD(core_sys_base, 269 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); 270 } 271 272 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 273 struct hdmi_avi_infoframe *frame) 274 { 275 void __iomem *av_base = hdmi_av_base(core); 276 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 277 int i; 278 279 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 280 281 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 282 HDMI_INFOFRAME_SIZE(AVI), false); 283 284 for (i = 0; i < sizeof(data); ++i) { 285 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, 286 data[i]); 287 } 288 } 289 290 static void hdmi_core_av_packet_config(struct hdmi_core_data *core, 291 struct hdmi_core_packet_enable_repeat repeat_cfg) 292 { 293 /* enable/repeat the infoframe */ 294 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, 295 (repeat_cfg.audio_pkt << 5) | 296 (repeat_cfg.audio_pkt_repeat << 4) | 297 (repeat_cfg.avi_infoframe << 1) | 298 (repeat_cfg.avi_infoframe_repeat)); 299 300 /* enable/repeat the packet */ 301 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, 302 (repeat_cfg.gen_cntrl_pkt << 3) | 303 (repeat_cfg.gen_cntrl_pkt_repeat << 2) | 304 (repeat_cfg.generic_pkt << 1) | 305 (repeat_cfg.generic_pkt_repeat)); 306 } 307 308 void hdmi4_configure(struct hdmi_core_data *core, 309 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 310 { 311 /* HDMI */ 312 struct videomode vm; 313 struct hdmi_video_format video_format; 314 /* HDMI core */ 315 struct hdmi_core_video_config v_core_cfg; 316 struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 }; 317 318 hdmi_core_init(&v_core_cfg); 319 320 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg); 321 322 hdmi_wp_video_config_timing(wp, &vm); 323 324 /* video config */ 325 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 326 327 hdmi_wp_video_config_format(wp, &video_format); 328 329 hdmi_wp_video_config_interface(wp, &vm); 330 331 /* 332 * configure core video part 333 * set software reset in the core 334 */ 335 hdmi_core_swreset_assert(core); 336 337 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; 338 v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode; 339 340 hdmi_core_video_config(core, &v_core_cfg); 341 342 /* release software reset in the core */ 343 hdmi_core_swreset_release(core); 344 345 if (cfg->hdmi_dvi_mode == HDMI_HDMI) { 346 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 347 348 /* enable/repeat the infoframe */ 349 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; 350 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; 351 /* wakeup */ 352 repeat_cfg.audio_pkt = HDMI_PACKETENABLE; 353 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; 354 } 355 356 hdmi_core_av_packet_config(core, repeat_cfg); 357 } 358 359 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) 360 { 361 int i; 362 363 #define CORE_REG(i, name) name(i) 364 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 365 hdmi_read_reg(core->base, r)) 366 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ 367 hdmi_read_reg(hdmi_av_base(core), r)) 368 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ 369 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ 370 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) 371 372 DUMPCORE(HDMI_CORE_SYS_VND_IDL); 373 DUMPCORE(HDMI_CORE_SYS_DEV_IDL); 374 DUMPCORE(HDMI_CORE_SYS_DEV_IDH); 375 DUMPCORE(HDMI_CORE_SYS_DEV_REV); 376 DUMPCORE(HDMI_CORE_SYS_SRST); 377 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); 378 DUMPCORE(HDMI_CORE_SYS_SYS_STAT); 379 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); 380 DUMPCORE(HDMI_CORE_SYS_DE_DLY); 381 DUMPCORE(HDMI_CORE_SYS_DE_CTRL); 382 DUMPCORE(HDMI_CORE_SYS_DE_TOP); 383 DUMPCORE(HDMI_CORE_SYS_DE_CNTL); 384 DUMPCORE(HDMI_CORE_SYS_DE_CNTH); 385 DUMPCORE(HDMI_CORE_SYS_DE_LINL); 386 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); 387 DUMPCORE(HDMI_CORE_SYS_HRES_L); 388 DUMPCORE(HDMI_CORE_SYS_HRES_H); 389 DUMPCORE(HDMI_CORE_SYS_VRES_L); 390 DUMPCORE(HDMI_CORE_SYS_VRES_H); 391 DUMPCORE(HDMI_CORE_SYS_IADJUST); 392 DUMPCORE(HDMI_CORE_SYS_POLDETECT); 393 DUMPCORE(HDMI_CORE_SYS_HWIDTH1); 394 DUMPCORE(HDMI_CORE_SYS_HWIDTH2); 395 DUMPCORE(HDMI_CORE_SYS_VWIDTH); 396 DUMPCORE(HDMI_CORE_SYS_VID_CTRL); 397 DUMPCORE(HDMI_CORE_SYS_VID_ACEN); 398 DUMPCORE(HDMI_CORE_SYS_VID_MODE); 399 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 400 DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); 401 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 402 DUMPCORE(HDMI_CORE_SYS_DC_HEADER); 403 DUMPCORE(HDMI_CORE_SYS_VID_DITHER); 404 DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); 405 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); 406 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); 407 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); 408 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); 409 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); 410 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); 411 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); 412 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); 413 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); 414 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); 415 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); 416 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); 417 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); 418 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); 419 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); 420 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); 421 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); 422 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); 423 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); 424 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); 425 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); 426 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); 427 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); 428 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); 429 DUMPCORE(HDMI_CORE_SYS_INTR_STATE); 430 DUMPCORE(HDMI_CORE_SYS_INTR1); 431 DUMPCORE(HDMI_CORE_SYS_INTR2); 432 DUMPCORE(HDMI_CORE_SYS_INTR3); 433 DUMPCORE(HDMI_CORE_SYS_INTR4); 434 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); 435 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); 436 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); 437 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); 438 DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); 439 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); 440 441 DUMPCORE(HDMI_CORE_DDC_ADDR); 442 DUMPCORE(HDMI_CORE_DDC_SEGM); 443 DUMPCORE(HDMI_CORE_DDC_OFFSET); 444 DUMPCORE(HDMI_CORE_DDC_COUNT1); 445 DUMPCORE(HDMI_CORE_DDC_COUNT2); 446 DUMPCORE(HDMI_CORE_DDC_STATUS); 447 DUMPCORE(HDMI_CORE_DDC_CMD); 448 DUMPCORE(HDMI_CORE_DDC_DATA); 449 450 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); 451 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); 452 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); 453 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); 454 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); 455 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); 456 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); 457 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); 458 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); 459 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); 460 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); 461 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); 462 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); 463 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); 464 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); 465 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); 466 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); 467 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); 468 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); 469 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); 470 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); 471 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); 472 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); 473 DUMPCOREAV(HDMI_CORE_AV_ASRC); 474 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); 475 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); 476 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); 477 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); 478 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); 479 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); 480 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); 481 DUMPCOREAV(HDMI_CORE_AV_DPD); 482 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); 483 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); 484 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); 485 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); 486 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); 487 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); 488 489 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) 490 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); 491 492 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); 493 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); 494 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); 495 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); 496 497 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) 498 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); 499 500 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); 501 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); 502 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); 503 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); 504 505 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) 506 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); 507 508 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); 509 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); 510 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); 511 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); 512 513 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) 514 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); 515 516 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) 517 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); 518 519 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); 520 521 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) 522 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); 523 524 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); 525 } 526 527 static void hdmi_core_audio_config(struct hdmi_core_data *core, 528 struct hdmi_core_audio_config *cfg) 529 { 530 u32 r; 531 void __iomem *av_base = hdmi_av_base(core); 532 533 /* 534 * Parameters for generation of Audio Clock Recovery packets 535 */ 536 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); 537 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); 538 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); 539 540 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { 541 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); 542 REG_FLD_MOD(av_base, 543 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); 544 REG_FLD_MOD(av_base, 545 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); 546 } else { 547 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, 548 cfg->aud_par_busclk, 7, 0); 549 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, 550 (cfg->aud_par_busclk >> 8), 7, 0); 551 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, 552 (cfg->aud_par_busclk >> 16), 7, 0); 553 } 554 555 /* Set ACR clock divisor */ 556 REG_FLD_MOD(av_base, 557 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); 558 559 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); 560 /* 561 * Use TMDS clock for ACR packets. For devices that use 562 * the MCLK, this is the first part of the MCLK initialization. 563 */ 564 r = FLD_MOD(r, 0, 2, 2); 565 566 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); 567 r = FLD_MOD(r, cfg->cts_mode, 0, 0); 568 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); 569 570 /* For devices using MCLK, this completes its initialization. */ 571 if (cfg->use_mclk) 572 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); 573 574 /* Override of SPDIF sample frequency with value in I2S_CHST4 */ 575 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, 576 cfg->fs_override, 1, 1); 577 578 /* 579 * Set IEC-60958-3 channel status word. It is passed to the IP 580 * just as it is received. The user of the driver is responsible 581 * for its contents. 582 */ 583 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, 584 cfg->iec60958_cfg->status[0]); 585 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, 586 cfg->iec60958_cfg->status[1]); 587 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, 588 cfg->iec60958_cfg->status[2]); 589 /* yes, this is correct: status[3] goes to CHST4 register */ 590 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, 591 cfg->iec60958_cfg->status[3]); 592 /* yes, this is correct: status[4] goes to CHST5 register */ 593 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, 594 cfg->iec60958_cfg->status[4]); 595 596 /* set I2S parameters */ 597 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); 598 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); 599 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); 600 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); 601 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); 602 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); 603 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); 604 605 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, 606 cfg->i2s_cfg.in_length_bits, 3, 0); 607 608 /* Audio channels and mode parameters */ 609 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); 610 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); 611 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); 612 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); 613 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); 614 r = FLD_MOD(r, cfg->en_spdif, 1, 1); 615 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); 616 617 /* Audio channel mappings */ 618 /* TODO: Make channel mapping dynamic. For now, map channels 619 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as 620 * HDMI speaker order is different. See CEA-861 Section 6.6.2. 621 */ 622 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); 623 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); 624 } 625 626 static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, 627 struct snd_cea_861_aud_if *info_aud) 628 { 629 u8 sum = 0, checksum = 0; 630 void __iomem *av_base = hdmi_av_base(core); 631 632 /* 633 * Set audio info frame type, version and length as 634 * described in HDMI 1.4a Section 8.2.2 specification. 635 * Checksum calculation is defined in Section 5.3.5. 636 */ 637 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); 638 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); 639 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); 640 sum += 0x84 + 0x001 + 0x00a; 641 642 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), 643 info_aud->db1_ct_cc); 644 sum += info_aud->db1_ct_cc; 645 646 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), 647 info_aud->db2_sf_ss); 648 sum += info_aud->db2_sf_ss; 649 650 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); 651 sum += info_aud->db3; 652 653 /* 654 * The OMAP HDMI IP requires to use the 8-channel channel code when 655 * transmitting more than two channels. 656 */ 657 if (info_aud->db4_ca != 0x00) 658 info_aud->db4_ca = 0x13; 659 660 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); 661 sum += info_aud->db4_ca; 662 663 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), 664 info_aud->db5_dminh_lsv); 665 sum += info_aud->db5_dminh_lsv; 666 667 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); 668 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); 669 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); 670 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); 671 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); 672 673 checksum = 0x100 - sum; 674 hdmi_write_reg(av_base, 675 HDMI_CORE_AV_AUDIO_CHSUM, checksum); 676 677 /* 678 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing 679 * is available. 680 */ 681 } 682 683 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 684 struct omap_dss_audio *audio, u32 pclk) 685 { 686 struct hdmi_audio_format audio_format; 687 struct hdmi_audio_dma audio_dma; 688 struct hdmi_core_audio_config acore; 689 int err, n, cts, channel_count; 690 unsigned int fs_nr; 691 bool word_length_16b = false; 692 693 if (!audio || !audio->iec || !audio->cea || !core) 694 return -EINVAL; 695 696 acore.iec60958_cfg = audio->iec; 697 /* 698 * In the IEC-60958 status word, check if the audio sample word length 699 * is 16-bit as several optimizations can be performed in such case. 700 */ 701 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) 702 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) 703 word_length_16b = true; 704 705 /* I2S configuration. See Phillips' specification */ 706 if (word_length_16b) 707 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; 708 else 709 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 710 /* 711 * The I2S input word length is twice the lenght given in the IEC-60958 712 * status word. If the word size is greater than 713 * 20 bits, increment by one. 714 */ 715 acore.i2s_cfg.in_length_bits = audio->iec->status[4] 716 & IEC958_AES4_CON_WORDLEN; 717 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) 718 acore.i2s_cfg.in_length_bits++; 719 acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; 720 acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; 721 acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; 722 acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; 723 724 /* convert sample frequency to a number */ 725 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 726 case IEC958_AES3_CON_FS_32000: 727 fs_nr = 32000; 728 break; 729 case IEC958_AES3_CON_FS_44100: 730 fs_nr = 44100; 731 break; 732 case IEC958_AES3_CON_FS_48000: 733 fs_nr = 48000; 734 break; 735 case IEC958_AES3_CON_FS_88200: 736 fs_nr = 88200; 737 break; 738 case IEC958_AES3_CON_FS_96000: 739 fs_nr = 96000; 740 break; 741 case IEC958_AES3_CON_FS_176400: 742 fs_nr = 176400; 743 break; 744 case IEC958_AES3_CON_FS_192000: 745 fs_nr = 192000; 746 break; 747 default: 748 return -EINVAL; 749 } 750 751 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); 752 753 /* Audio clock regeneration settings */ 754 acore.n = n; 755 acore.cts = cts; 756 if (core->cts_swmode) { 757 acore.aud_par_busclk = 0; 758 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; 759 acore.use_mclk = core->audio_use_mclk; 760 } else { 761 acore.aud_par_busclk = (((128 * 31) - 1) << 8); 762 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; 763 acore.use_mclk = true; 764 } 765 766 if (acore.use_mclk) 767 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; 768 769 /* Audio channels settings */ 770 channel_count = (audio->cea->db1_ct_cc & 771 CEA861_AUDIO_INFOFRAME_DB1CC) + 1; 772 773 switch (channel_count) { 774 case 2: 775 audio_format.active_chnnls_msk = 0x03; 776 break; 777 case 3: 778 audio_format.active_chnnls_msk = 0x07; 779 break; 780 case 4: 781 audio_format.active_chnnls_msk = 0x0f; 782 break; 783 case 5: 784 audio_format.active_chnnls_msk = 0x1f; 785 break; 786 case 6: 787 audio_format.active_chnnls_msk = 0x3f; 788 break; 789 case 7: 790 audio_format.active_chnnls_msk = 0x7f; 791 break; 792 case 8: 793 audio_format.active_chnnls_msk = 0xff; 794 break; 795 default: 796 return -EINVAL; 797 } 798 799 /* 800 * the HDMI IP needs to enable four stereo channels when transmitting 801 * more than 2 audio channels. Similarly, the channel count in the 802 * Audio InfoFrame has to match the sample_present bits (some channels 803 * are padded with zeroes) 804 */ 805 if (channel_count == 2) { 806 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; 807 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; 808 acore.layout = HDMI_AUDIO_LAYOUT_2CH; 809 } else { 810 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; 811 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | 812 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | 813 HDMI_AUDIO_I2S_SD3_EN; 814 acore.layout = HDMI_AUDIO_LAYOUT_8CH; 815 audio->cea->db1_ct_cc = 7; 816 } 817 818 acore.en_spdif = false; 819 /* use sample frequency from channel status word */ 820 acore.fs_override = true; 821 /* enable ACR packets */ 822 acore.en_acr_pkt = true; 823 /* disable direct streaming digital audio */ 824 acore.en_dsd_audio = false; 825 /* use parallel audio interface */ 826 acore.en_parallel_aud_input = true; 827 828 /* DMA settings */ 829 if (word_length_16b) 830 audio_dma.transfer_size = 0x10; 831 else 832 audio_dma.transfer_size = 0x20; 833 audio_dma.block_size = 0xC0; 834 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 835 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 836 837 /* audio FIFO format settings */ 838 if (word_length_16b) { 839 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 840 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 841 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 842 } else { 843 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; 844 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; 845 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 846 } 847 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 848 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 849 /* disable start/stop signals of IEC 60958 blocks */ 850 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 851 852 /* configure DMA and audio FIFO format*/ 853 hdmi_wp_audio_config_dma(wp, &audio_dma); 854 hdmi_wp_audio_config_format(wp, &audio_format); 855 856 /* configure the core*/ 857 hdmi_core_audio_config(core, &acore); 858 859 /* configure CEA 861 audio infoframe*/ 860 hdmi_core_audio_infoframe_cfg(core, audio->cea); 861 862 return 0; 863 } 864 865 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 866 { 867 REG_FLD_MOD(hdmi_av_base(core), 868 HDMI_CORE_AV_AUD_MODE, true, 0, 0); 869 870 hdmi_wp_audio_core_req_enable(wp, true); 871 872 return 0; 873 } 874 875 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 876 { 877 REG_FLD_MOD(hdmi_av_base(core), 878 HDMI_CORE_AV_AUD_MODE, false, 0, 0); 879 880 hdmi_wp_audio_core_req_enable(wp, false); 881 } 882 883 struct hdmi4_features { 884 bool cts_swmode; 885 bool audio_use_mclk; 886 }; 887 888 static const struct hdmi4_features hdmi4430_es1_features = { 889 .cts_swmode = false, 890 .audio_use_mclk = false, 891 }; 892 893 static const struct hdmi4_features hdmi4430_es2_features = { 894 .cts_swmode = true, 895 .audio_use_mclk = false, 896 }; 897 898 static const struct hdmi4_features hdmi4_features = { 899 .cts_swmode = true, 900 .audio_use_mclk = true, 901 }; 902 903 static const struct soc_device_attribute hdmi4_soc_devices[] = { 904 { 905 .machine = "OMAP4430", 906 .revision = "ES1.?", 907 .data = &hdmi4430_es1_features, 908 }, 909 { 910 .machine = "OMAP4430", 911 .revision = "ES2.?", 912 .data = &hdmi4430_es2_features, 913 }, 914 { 915 .family = "OMAP4", 916 .data = &hdmi4_features, 917 }, 918 { /* sentinel */ } 919 }; 920 921 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 922 { 923 const struct hdmi4_features *features; 924 struct resource *res; 925 926 features = soc_device_match(hdmi4_soc_devices)->data; 927 core->cts_swmode = features->cts_swmode; 928 core->audio_use_mclk = features->audio_use_mclk; 929 930 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 931 core->base = devm_ioremap_resource(&pdev->dev, res); 932 if (IS_ERR(core->base)) 933 return PTR_ERR(core->base); 934 935 return 0; 936 } 937