1 /* 2 * HDMI driver definition for TI OMAP4 Processor. 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef _HDMI_H 20 #define _HDMI_H 21 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/platform_device.h> 25 #include <linux/hdmi.h> 26 #include <sound/omap-hdmi-audio.h> 27 #include <media/cec.h> 28 29 #include "omapdss.h" 30 #include "dss.h" 31 32 /* HDMI Wrapper */ 33 34 #define HDMI_WP_REVISION 0x0 35 #define HDMI_WP_SYSCONFIG 0x10 36 #define HDMI_WP_IRQSTATUS_RAW 0x24 37 #define HDMI_WP_IRQSTATUS 0x28 38 #define HDMI_WP_IRQENABLE_SET 0x2C 39 #define HDMI_WP_IRQENABLE_CLR 0x30 40 #define HDMI_WP_IRQWAKEEN 0x34 41 #define HDMI_WP_PWR_CTRL 0x40 42 #define HDMI_WP_DEBOUNCE 0x44 43 #define HDMI_WP_VIDEO_CFG 0x50 44 #define HDMI_WP_VIDEO_SIZE 0x60 45 #define HDMI_WP_VIDEO_TIMING_H 0x68 46 #define HDMI_WP_VIDEO_TIMING_V 0x6C 47 #define HDMI_WP_CLK 0x70 48 #define HDMI_WP_AUDIO_CFG 0x80 49 #define HDMI_WP_AUDIO_CFG2 0x84 50 #define HDMI_WP_AUDIO_CTRL 0x88 51 #define HDMI_WP_AUDIO_DATA 0x8C 52 53 /* HDMI WP IRQ flags */ 54 #define HDMI_IRQ_CORE (1 << 0) 55 #define HDMI_IRQ_OCP_TIMEOUT (1 << 4) 56 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) 57 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) 58 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10) 59 #define HDMI_IRQ_VIDEO_VSYNC (1 << 16) 60 #define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17) 61 #define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24) 62 #define HDMI_IRQ_LINK_CONNECT (1 << 25) 63 #define HDMI_IRQ_LINK_DISCONNECT (1 << 26) 64 #define HDMI_IRQ_PLL_LOCK (1 << 29) 65 #define HDMI_IRQ_PLL_UNLOCK (1 << 30) 66 #define HDMI_IRQ_PLL_RECAL (1 << 31) 67 68 /* HDMI PLL */ 69 70 #define PLLCTRL_PLL_CONTROL 0x0 71 #define PLLCTRL_PLL_STATUS 0x4 72 #define PLLCTRL_PLL_GO 0x8 73 #define PLLCTRL_CFG1 0xC 74 #define PLLCTRL_CFG2 0x10 75 #define PLLCTRL_CFG3 0x14 76 #define PLLCTRL_SSC_CFG1 0x18 77 #define PLLCTRL_SSC_CFG2 0x1C 78 #define PLLCTRL_CFG4 0x20 79 80 /* HDMI PHY */ 81 82 #define HDMI_TXPHY_TX_CTRL 0x0 83 #define HDMI_TXPHY_DIGITAL_CTRL 0x4 84 #define HDMI_TXPHY_POWER_CTRL 0x8 85 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC 86 #define HDMI_TXPHY_BIST_CONTROL 0x1C 87 88 enum hdmi_pll_pwr { 89 HDMI_PLLPWRCMD_ALLOFF = 0, 90 HDMI_PLLPWRCMD_PLLONLY = 1, 91 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, 92 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 93 }; 94 95 enum hdmi_phy_pwr { 96 HDMI_PHYPWRCMD_OFF = 0, 97 HDMI_PHYPWRCMD_LDOON = 1, 98 HDMI_PHYPWRCMD_TXON = 2 99 }; 100 101 enum hdmi_core_hdmi_dvi { 102 HDMI_DVI = 0, 103 HDMI_HDMI = 1 104 }; 105 106 enum hdmi_packing_mode { 107 HDMI_PACK_10b_RGB_YUV444 = 0, 108 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, 109 HDMI_PACK_20b_YUV422 = 2, 110 HDMI_PACK_ALREADYPACKED = 7 111 }; 112 113 enum hdmi_stereo_channels { 114 HDMI_AUDIO_STEREO_NOCHANNELS = 0, 115 HDMI_AUDIO_STEREO_ONECHANNEL = 1, 116 HDMI_AUDIO_STEREO_TWOCHANNELS = 2, 117 HDMI_AUDIO_STEREO_THREECHANNELS = 3, 118 HDMI_AUDIO_STEREO_FOURCHANNELS = 4 119 }; 120 121 enum hdmi_audio_type { 122 HDMI_AUDIO_TYPE_LPCM = 0, 123 HDMI_AUDIO_TYPE_IEC = 1 124 }; 125 126 enum hdmi_audio_justify { 127 HDMI_AUDIO_JUSTIFY_LEFT = 0, 128 HDMI_AUDIO_JUSTIFY_RIGHT = 1 129 }; 130 131 enum hdmi_audio_sample_order { 132 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, 133 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 134 }; 135 136 enum hdmi_audio_samples_perword { 137 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, 138 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 139 }; 140 141 enum hdmi_audio_sample_size_omap { 142 HDMI_AUDIO_SAMPLE_16BITS = 0, 143 HDMI_AUDIO_SAMPLE_24BITS = 1 144 }; 145 146 enum hdmi_audio_transf_mode { 147 HDMI_AUDIO_TRANSF_DMA = 0, 148 HDMI_AUDIO_TRANSF_IRQ = 1 149 }; 150 151 enum hdmi_audio_blk_strt_end_sig { 152 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, 153 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 154 }; 155 156 enum hdmi_core_audio_layout { 157 HDMI_AUDIO_LAYOUT_2CH = 0, 158 HDMI_AUDIO_LAYOUT_8CH = 1, 159 HDMI_AUDIO_LAYOUT_6CH = 2 160 }; 161 162 enum hdmi_core_cts_mode { 163 HDMI_AUDIO_CTS_MODE_HW = 0, 164 HDMI_AUDIO_CTS_MODE_SW = 1 165 }; 166 167 enum hdmi_audio_mclk_mode { 168 HDMI_AUDIO_MCLK_128FS = 0, 169 HDMI_AUDIO_MCLK_256FS = 1, 170 HDMI_AUDIO_MCLK_384FS = 2, 171 HDMI_AUDIO_MCLK_512FS = 3, 172 HDMI_AUDIO_MCLK_768FS = 4, 173 HDMI_AUDIO_MCLK_1024FS = 5, 174 HDMI_AUDIO_MCLK_1152FS = 6, 175 HDMI_AUDIO_MCLK_192FS = 7 176 }; 177 178 struct hdmi_video_format { 179 enum hdmi_packing_mode packing_mode; 180 u32 y_res; /* Line per panel */ 181 u32 x_res; /* pixel per line */ 182 }; 183 184 struct hdmi_config { 185 struct videomode vm; 186 struct hdmi_avi_infoframe infoframe; 187 enum hdmi_core_hdmi_dvi hdmi_dvi_mode; 188 }; 189 190 struct hdmi_audio_format { 191 enum hdmi_stereo_channels stereo_channels; 192 u8 active_chnnls_msk; 193 enum hdmi_audio_type type; 194 enum hdmi_audio_justify justification; 195 enum hdmi_audio_sample_order sample_order; 196 enum hdmi_audio_samples_perword samples_per_word; 197 enum hdmi_audio_sample_size_omap sample_size; 198 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; 199 }; 200 201 struct hdmi_audio_dma { 202 u8 transfer_size; 203 u8 block_size; 204 enum hdmi_audio_transf_mode mode; 205 u16 fifo_threshold; 206 }; 207 208 struct hdmi_core_audio_i2s_config { 209 u8 in_length_bits; 210 u8 justification; 211 u8 sck_edge_mode; 212 u8 vbit; 213 u8 direction; 214 u8 shift; 215 u8 active_sds; 216 }; 217 218 struct hdmi_core_audio_config { 219 struct hdmi_core_audio_i2s_config i2s_cfg; 220 struct snd_aes_iec958 *iec60958_cfg; 221 bool fs_override; 222 u32 n; 223 u32 cts; 224 u32 aud_par_busclk; 225 enum hdmi_core_audio_layout layout; 226 enum hdmi_core_cts_mode cts_mode; 227 bool use_mclk; 228 enum hdmi_audio_mclk_mode mclk_mode; 229 bool en_acr_pkt; 230 bool en_dsd_audio; 231 bool en_parallel_aud_input; 232 bool en_spdif; 233 }; 234 235 struct hdmi_wp_data { 236 void __iomem *base; 237 phys_addr_t phys_base; 238 unsigned int version; 239 }; 240 241 struct hdmi_pll_data { 242 struct dss_pll pll; 243 244 void __iomem *base; 245 246 struct platform_device *pdev; 247 struct hdmi_wp_data *wp; 248 }; 249 250 struct hdmi_phy_features { 251 bool bist_ctrl; 252 bool ldo_voltage; 253 unsigned long max_phy; 254 }; 255 256 struct hdmi_phy_data { 257 void __iomem *base; 258 259 const struct hdmi_phy_features *features; 260 u8 lane_function[4]; 261 u8 lane_polarity[4]; 262 }; 263 264 struct hdmi_core_data { 265 void __iomem *base; 266 bool cts_swmode; 267 bool audio_use_mclk; 268 269 struct hdmi_wp_data *wp; 270 unsigned int core_pwr_cnt; 271 struct cec_adapter *adap; 272 }; 273 274 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, 275 u32 val) 276 { 277 __raw_writel(val, base_addr + idx); 278 } 279 280 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) 281 { 282 return __raw_readl(base_addr + idx); 283 } 284 285 #define REG_FLD_MOD(base, idx, val, start, end) \ 286 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ 287 val, start, end)) 288 #define REG_GET(base, idx, start, end) \ 289 FLD_GET(hdmi_read_reg(base, idx), start, end) 290 291 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, 292 const u32 idx, int b2, int b1, u32 val) 293 { 294 u32 t = 0, v; 295 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { 296 if (t++ > 10000) 297 return v; 298 udelay(1); 299 } 300 return v; 301 } 302 303 /* HDMI wrapper funcs */ 304 int hdmi_wp_video_start(struct hdmi_wp_data *wp); 305 void hdmi_wp_video_stop(struct hdmi_wp_data *wp); 306 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); 307 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); 308 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); 309 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); 310 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); 311 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); 312 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); 313 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, 314 struct hdmi_video_format *video_fmt); 315 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 316 struct videomode *vm); 317 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 318 struct videomode *vm); 319 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 320 struct videomode *vm, struct hdmi_config *param); 321 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, 322 unsigned int version); 323 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); 324 325 /* HDMI PLL funcs */ 326 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 327 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 328 struct hdmi_wp_data *wp); 329 void hdmi_pll_uninit(struct hdmi_pll_data *hpll); 330 331 /* HDMI PHY funcs */ 332 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, 333 unsigned long lfbitclk); 334 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); 335 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy, 336 unsigned int version); 337 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); 338 339 /* HDMI common funcs */ 340 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, 341 struct hdmi_phy_data *phy); 342 343 /* Audio funcs */ 344 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts); 345 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); 346 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); 347 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, 348 struct hdmi_audio_format *aud_fmt); 349 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, 350 struct hdmi_audio_dma *aud_dma); 351 static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg) 352 { 353 return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false; 354 } 355 356 /* HDMI DRV data */ 357 struct omap_hdmi { 358 struct mutex lock; 359 struct platform_device *pdev; 360 361 struct hdmi_wp_data wp; 362 struct hdmi_pll_data pll; 363 struct hdmi_phy_data phy; 364 struct hdmi_core_data core; 365 366 struct hdmi_config cfg; 367 368 struct regulator *vdda_reg; 369 370 bool core_enabled; 371 372 struct omap_dss_device output; 373 374 struct platform_device *audio_pdev; 375 void (*audio_abort_cb)(struct device *dev); 376 int wp_idlemode; 377 378 bool audio_configured; 379 struct omap_dss_audio audio_config; 380 381 /* This lock should be taken when booleans below are touched. */ 382 spinlock_t audio_playing_lock; 383 bool audio_playing; 384 bool display_enabled; 385 }; 386 387 #endif 388