1 /* 2 * linux/drivers/video/omap2/dss/dss.h 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __OMAP2_DSS_H 24 #define __OMAP2_DSS_H 25 26 #include <linux/interrupt.h> 27 28 #include "omapdss.h" 29 30 #ifdef pr_fmt 31 #undef pr_fmt 32 #endif 33 34 #ifdef DSS_SUBSYS_NAME 35 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt 36 #else 37 #define pr_fmt(fmt) fmt 38 #endif 39 40 #define DSSDBG(format, ...) \ 41 pr_debug(format, ## __VA_ARGS__) 42 43 #ifdef DSS_SUBSYS_NAME 44 #define DSSERR(format, ...) \ 45 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__) 46 #else 47 #define DSSERR(format, ...) \ 48 pr_err("omapdss error: " format, ##__VA_ARGS__) 49 #endif 50 51 #ifdef DSS_SUBSYS_NAME 52 #define DSSINFO(format, ...) \ 53 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 54 #else 55 #define DSSINFO(format, ...) \ 56 pr_info("omapdss: " format, ## __VA_ARGS__) 57 #endif 58 59 #ifdef DSS_SUBSYS_NAME 60 #define DSSWARN(format, ...) \ 61 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 62 #else 63 #define DSSWARN(format, ...) \ 64 pr_warn("omapdss: " format, ##__VA_ARGS__) 65 #endif 66 67 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 68 number. For example 7:0 */ 69 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 70 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 71 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 72 #define FLD_MOD(orig, val, start, end) \ 73 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 74 75 enum dss_io_pad_mode { 76 DSS_IO_PAD_MODE_RESET, 77 DSS_IO_PAD_MODE_RFBI, 78 DSS_IO_PAD_MODE_BYPASS, 79 }; 80 81 enum dss_hdmi_venc_clk_source_select { 82 DSS_VENC_TV_CLK = 0, 83 DSS_HDMI_M_PCLK = 1, 84 }; 85 86 enum dss_dsi_content_type { 87 DSS_DSI_CONTENT_DCS, 88 DSS_DSI_CONTENT_GENERIC, 89 }; 90 91 enum dss_writeback_channel { 92 DSS_WB_LCD1_MGR = 0, 93 DSS_WB_LCD2_MGR = 1, 94 DSS_WB_TV_MGR = 2, 95 DSS_WB_OVL0 = 3, 96 DSS_WB_OVL1 = 4, 97 DSS_WB_OVL2 = 5, 98 DSS_WB_OVL3 = 6, 99 DSS_WB_LCD3_MGR = 7, 100 }; 101 102 enum dss_clk_source { 103 DSS_CLK_SRC_FCK = 0, 104 105 DSS_CLK_SRC_PLL1_1, 106 DSS_CLK_SRC_PLL1_2, 107 DSS_CLK_SRC_PLL1_3, 108 109 DSS_CLK_SRC_PLL2_1, 110 DSS_CLK_SRC_PLL2_2, 111 DSS_CLK_SRC_PLL2_3, 112 113 DSS_CLK_SRC_HDMI_PLL, 114 }; 115 116 enum dss_pll_id { 117 DSS_PLL_DSI1, 118 DSS_PLL_DSI2, 119 DSS_PLL_HDMI, 120 DSS_PLL_VIDEO1, 121 DSS_PLL_VIDEO2, 122 }; 123 124 struct dss_pll; 125 126 #define DSS_PLL_MAX_HSDIVS 4 127 128 enum dss_pll_type { 129 DSS_PLL_TYPE_A, 130 DSS_PLL_TYPE_B, 131 }; 132 133 /* 134 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. 135 * Type-B PLLs: clkout[0] refers to m2. 136 */ 137 struct dss_pll_clock_info { 138 /* rates that we get with dividers below */ 139 unsigned long fint; 140 unsigned long clkdco; 141 unsigned long clkout[DSS_PLL_MAX_HSDIVS]; 142 143 /* dividers */ 144 u16 n; 145 u16 m; 146 u32 mf; 147 u16 mX[DSS_PLL_MAX_HSDIVS]; 148 u16 sd; 149 }; 150 151 struct dss_pll_ops { 152 int (*enable)(struct dss_pll *pll); 153 void (*disable)(struct dss_pll *pll); 154 int (*set_config)(struct dss_pll *pll, 155 const struct dss_pll_clock_info *cinfo); 156 }; 157 158 struct dss_pll_hw { 159 enum dss_pll_type type; 160 161 unsigned n_max; 162 unsigned m_min; 163 unsigned m_max; 164 unsigned mX_max; 165 166 unsigned long fint_min, fint_max; 167 unsigned long clkdco_min, clkdco_low, clkdco_max; 168 169 u8 n_msb, n_lsb; 170 u8 m_msb, m_lsb; 171 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS]; 172 173 bool has_stopmode; 174 bool has_freqsel; 175 bool has_selfreqdco; 176 bool has_refsel; 177 }; 178 179 struct dss_pll { 180 const char *name; 181 enum dss_pll_id id; 182 183 struct clk *clkin; 184 struct regulator *regulator; 185 186 void __iomem *base; 187 188 const struct dss_pll_hw *hw; 189 190 const struct dss_pll_ops *ops; 191 192 struct dss_pll_clock_info cinfo; 193 }; 194 195 struct dispc_clock_info { 196 /* rates that we get with dividers below */ 197 unsigned long lck; 198 unsigned long pck; 199 200 /* dividers */ 201 u16 lck_div; 202 u16 pck_div; 203 }; 204 205 struct dss_lcd_mgr_config { 206 enum dss_io_pad_mode io_pad_mode; 207 208 bool stallmode; 209 bool fifohandcheck; 210 211 struct dispc_clock_info clock_info; 212 213 int video_port_width; 214 215 int lcden_sig_polarity; 216 }; 217 218 struct seq_file; 219 struct platform_device; 220 221 /* core */ 222 struct platform_device *dss_get_core_pdev(void); 223 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); 224 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); 225 int dss_set_min_bus_tput(struct device *dev, unsigned long tput); 226 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); 227 228 static inline bool dss_mgr_is_lcd(enum omap_channel id) 229 { 230 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || 231 id == OMAP_DSS_CHANNEL_LCD3) 232 return true; 233 else 234 return false; 235 } 236 237 /* DSS */ 238 int dss_init_platform_driver(void) __init; 239 void dss_uninit_platform_driver(void); 240 241 int dss_runtime_get(void); 242 void dss_runtime_put(void); 243 244 unsigned long dss_get_dispc_clk_rate(void); 245 int dss_dpi_select_source(int port, enum omap_channel channel); 246 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 247 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 248 const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 249 void dss_dump_clocks(struct seq_file *s); 250 251 /* DSS VIDEO PLL */ 252 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, 253 struct regulator *regulator); 254 void dss_video_pll_uninit(struct dss_pll *pll); 255 256 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 257 void dss_debug_dump_clocks(struct seq_file *s); 258 #endif 259 260 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); 261 262 void dss_sdi_init(int datapairs); 263 int dss_sdi_enable(void); 264 void dss_sdi_disable(void); 265 266 void dss_select_dsi_clk_source(int dsi_module, 267 enum dss_clk_source clk_src); 268 void dss_select_lcd_clk_source(enum omap_channel channel, 269 enum dss_clk_source clk_src); 270 enum dss_clk_source dss_get_dispc_clk_source(void); 271 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module); 272 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 273 274 void dss_set_venc_output(enum omap_dss_venc_type type); 275 void dss_set_dac_pwrdn_bgz(bool enable); 276 277 int dss_set_fck_rate(unsigned long rate); 278 279 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 280 bool dss_div_calc(unsigned long pck, unsigned long fck_min, 281 dss_div_calc_func func, void *data); 282 283 /* SDI */ 284 int sdi_init_platform_driver(void) __init; 285 void sdi_uninit_platform_driver(void); 286 287 #ifdef CONFIG_OMAP2_DSS_SDI 288 int sdi_init_port(struct platform_device *pdev, struct device_node *port); 289 void sdi_uninit_port(struct device_node *port); 290 #else 291 static inline int sdi_init_port(struct platform_device *pdev, 292 struct device_node *port) 293 { 294 return 0; 295 } 296 static inline void sdi_uninit_port(struct device_node *port) 297 { 298 } 299 #endif 300 301 /* DSI */ 302 303 #ifdef CONFIG_OMAP2_DSS_DSI 304 305 struct dentry; 306 struct file_operations; 307 308 int dsi_init_platform_driver(void) __init; 309 void dsi_uninit_platform_driver(void); 310 311 void dsi_dump_clocks(struct seq_file *s); 312 313 void dsi_irq_handler(void); 314 315 #endif 316 317 /* DPI */ 318 int dpi_init_platform_driver(void) __init; 319 void dpi_uninit_platform_driver(void); 320 321 #ifdef CONFIG_OMAP2_DSS_DPI 322 int dpi_init_port(struct platform_device *pdev, struct device_node *port); 323 void dpi_uninit_port(struct device_node *port); 324 #else 325 static inline int dpi_init_port(struct platform_device *pdev, 326 struct device_node *port) 327 { 328 return 0; 329 } 330 static inline void dpi_uninit_port(struct device_node *port) 331 { 332 } 333 #endif 334 335 /* DISPC */ 336 int dispc_init_platform_driver(void) __init; 337 void dispc_uninit_platform_driver(void); 338 void dispc_dump_clocks(struct seq_file *s); 339 340 int dispc_runtime_get(void); 341 void dispc_runtime_put(void); 342 343 void dispc_enable_sidle(void); 344 void dispc_disable_sidle(void); 345 346 void dispc_lcd_enable_signal(bool enable); 347 void dispc_pck_free_enable(bool enable); 348 void dispc_enable_fifomerge(bool enable); 349 void dispc_enable_gamma_table(bool enable); 350 351 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 352 unsigned long pck, void *data); 353 bool dispc_div_calc(unsigned long dispc, 354 unsigned long pck_min, unsigned long pck_max, 355 dispc_div_calc_func func, void *data); 356 357 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm); 358 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 359 struct dispc_clock_info *cinfo); 360 361 362 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 363 u32 high); 364 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 365 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 366 bool manual_update); 367 368 void dispc_mgr_set_clock_div(enum omap_channel channel, 369 const struct dispc_clock_info *cinfo); 370 int dispc_mgr_get_clock_div(enum omap_channel channel, 371 struct dispc_clock_info *cinfo); 372 void dispc_set_tv_pclk(unsigned long pclk); 373 374 u32 dispc_wb_get_framedone_irq(void); 375 bool dispc_wb_go_busy(void); 376 void dispc_wb_go(void); 377 void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 378 int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 379 bool mem_to_mem, const struct videomode *vm); 380 381 /* VENC */ 382 int venc_init_platform_driver(void) __init; 383 void venc_uninit_platform_driver(void); 384 385 /* HDMI */ 386 int hdmi4_init_platform_driver(void) __init; 387 void hdmi4_uninit_platform_driver(void); 388 389 int hdmi5_init_platform_driver(void) __init; 390 void hdmi5_uninit_platform_driver(void); 391 392 /* RFBI */ 393 int rfbi_init_platform_driver(void) __init; 394 void rfbi_uninit_platform_driver(void); 395 396 397 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 398 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 399 { 400 int b; 401 for (b = 0; b < 32; ++b) { 402 if (irqstatus & (1 << b)) 403 irq_arr[b]++; 404 } 405 } 406 #endif 407 408 /* PLL */ 409 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint, 410 unsigned long clkdco, void *data); 411 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, 412 void *data); 413 414 int dss_pll_register(struct dss_pll *pll); 415 void dss_pll_unregister(struct dss_pll *pll); 416 struct dss_pll *dss_pll_find(const char *name); 417 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src); 418 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 419 int dss_pll_enable(struct dss_pll *pll); 420 void dss_pll_disable(struct dss_pll *pll); 421 int dss_pll_set_config(struct dss_pll *pll, 422 const struct dss_pll_clock_info *cinfo); 423 424 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 425 unsigned long out_min, unsigned long out_max, 426 dss_hsdiv_calc_func func, void *data); 427 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 428 unsigned long pll_min, unsigned long pll_max, 429 dss_pll_calc_func func, void *data); 430 431 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 432 unsigned long target_clkout, struct dss_pll_clock_info *cinfo); 433 434 int dss_pll_write_config_type_a(struct dss_pll *pll, 435 const struct dss_pll_clock_info *cinfo); 436 int dss_pll_write_config_type_b(struct dss_pll *pll, 437 const struct dss_pll_clock_info *cinfo); 438 int dss_pll_wait_reset_done(struct dss_pll *pll); 439 440 #endif 441