1 /* 2 * linux/drivers/video/omap2/dss/dss.h 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __OMAP2_DSS_H 24 #define __OMAP2_DSS_H 25 26 #include <linux/interrupt.h> 27 28 #include "omapdss.h" 29 30 #define MAX_DSS_LCD_MANAGERS 3 31 #define MAX_NUM_DSI 2 32 33 #ifdef pr_fmt 34 #undef pr_fmt 35 #endif 36 37 #ifdef DSS_SUBSYS_NAME 38 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt 39 #else 40 #define pr_fmt(fmt) fmt 41 #endif 42 43 #define DSSDBG(format, ...) \ 44 pr_debug(format, ## __VA_ARGS__) 45 46 #ifdef DSS_SUBSYS_NAME 47 #define DSSERR(format, ...) \ 48 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__) 49 #else 50 #define DSSERR(format, ...) \ 51 pr_err("omapdss error: " format, ##__VA_ARGS__) 52 #endif 53 54 #ifdef DSS_SUBSYS_NAME 55 #define DSSINFO(format, ...) \ 56 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 57 #else 58 #define DSSINFO(format, ...) \ 59 pr_info("omapdss: " format, ## __VA_ARGS__) 60 #endif 61 62 #ifdef DSS_SUBSYS_NAME 63 #define DSSWARN(format, ...) \ 64 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 65 #else 66 #define DSSWARN(format, ...) \ 67 pr_warn("omapdss: " format, ##__VA_ARGS__) 68 #endif 69 70 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 71 number. For example 7:0 */ 72 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 73 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 74 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 75 #define FLD_MOD(orig, val, start, end) \ 76 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 77 78 enum dss_model { 79 DSS_MODEL_OMAP2, 80 DSS_MODEL_OMAP3, 81 DSS_MODEL_OMAP4, 82 DSS_MODEL_OMAP5, 83 DSS_MODEL_DRA7, 84 }; 85 86 enum dss_io_pad_mode { 87 DSS_IO_PAD_MODE_RESET, 88 DSS_IO_PAD_MODE_RFBI, 89 DSS_IO_PAD_MODE_BYPASS, 90 }; 91 92 enum dss_hdmi_venc_clk_source_select { 93 DSS_VENC_TV_CLK = 0, 94 DSS_HDMI_M_PCLK = 1, 95 }; 96 97 enum dss_dsi_content_type { 98 DSS_DSI_CONTENT_DCS, 99 DSS_DSI_CONTENT_GENERIC, 100 }; 101 102 enum dss_writeback_channel { 103 DSS_WB_LCD1_MGR = 0, 104 DSS_WB_LCD2_MGR = 1, 105 DSS_WB_TV_MGR = 2, 106 DSS_WB_OVL0 = 3, 107 DSS_WB_OVL1 = 4, 108 DSS_WB_OVL2 = 5, 109 DSS_WB_OVL3 = 6, 110 DSS_WB_LCD3_MGR = 7, 111 }; 112 113 enum dss_clk_source { 114 DSS_CLK_SRC_FCK = 0, 115 116 DSS_CLK_SRC_PLL1_1, 117 DSS_CLK_SRC_PLL1_2, 118 DSS_CLK_SRC_PLL1_3, 119 120 DSS_CLK_SRC_PLL2_1, 121 DSS_CLK_SRC_PLL2_2, 122 DSS_CLK_SRC_PLL2_3, 123 124 DSS_CLK_SRC_HDMI_PLL, 125 }; 126 127 enum dss_pll_id { 128 DSS_PLL_DSI1, 129 DSS_PLL_DSI2, 130 DSS_PLL_HDMI, 131 DSS_PLL_VIDEO1, 132 DSS_PLL_VIDEO2, 133 }; 134 135 struct dss_pll; 136 137 #define DSS_PLL_MAX_HSDIVS 4 138 139 enum dss_pll_type { 140 DSS_PLL_TYPE_A, 141 DSS_PLL_TYPE_B, 142 }; 143 144 /* 145 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. 146 * Type-B PLLs: clkout[0] refers to m2. 147 */ 148 struct dss_pll_clock_info { 149 /* rates that we get with dividers below */ 150 unsigned long fint; 151 unsigned long clkdco; 152 unsigned long clkout[DSS_PLL_MAX_HSDIVS]; 153 154 /* dividers */ 155 u16 n; 156 u16 m; 157 u32 mf; 158 u16 mX[DSS_PLL_MAX_HSDIVS]; 159 u16 sd; 160 }; 161 162 struct dss_pll_ops { 163 int (*enable)(struct dss_pll *pll); 164 void (*disable)(struct dss_pll *pll); 165 int (*set_config)(struct dss_pll *pll, 166 const struct dss_pll_clock_info *cinfo); 167 }; 168 169 struct dss_pll_hw { 170 enum dss_pll_type type; 171 172 unsigned n_max; 173 unsigned m_min; 174 unsigned m_max; 175 unsigned mX_max; 176 177 unsigned long fint_min, fint_max; 178 unsigned long clkdco_min, clkdco_low, clkdco_max; 179 180 u8 n_msb, n_lsb; 181 u8 m_msb, m_lsb; 182 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS]; 183 184 bool has_stopmode; 185 bool has_freqsel; 186 bool has_selfreqdco; 187 bool has_refsel; 188 189 /* DRA7 errata i886: use high N & M to avoid jitter */ 190 bool errata_i886; 191 }; 192 193 struct dss_pll { 194 const char *name; 195 enum dss_pll_id id; 196 197 struct clk *clkin; 198 struct regulator *regulator; 199 200 void __iomem *base; 201 202 const struct dss_pll_hw *hw; 203 204 const struct dss_pll_ops *ops; 205 206 struct dss_pll_clock_info cinfo; 207 }; 208 209 /* Defines a generic omap register field */ 210 struct dss_reg_field { 211 u8 start, end; 212 }; 213 214 struct dispc_clock_info { 215 /* rates that we get with dividers below */ 216 unsigned long lck; 217 unsigned long pck; 218 219 /* dividers */ 220 u16 lck_div; 221 u16 pck_div; 222 }; 223 224 struct dss_lcd_mgr_config { 225 enum dss_io_pad_mode io_pad_mode; 226 227 bool stallmode; 228 bool fifohandcheck; 229 230 struct dispc_clock_info clock_info; 231 232 int video_port_width; 233 234 int lcden_sig_polarity; 235 }; 236 237 struct seq_file; 238 struct platform_device; 239 240 /* core */ 241 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput) 242 { 243 /* To be implemented when the OMAP platform will provide this feature */ 244 return 0; 245 } 246 247 static inline bool dss_mgr_is_lcd(enum omap_channel id) 248 { 249 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || 250 id == OMAP_DSS_CHANNEL_LCD3) 251 return true; 252 else 253 return false; 254 } 255 256 /* DSS */ 257 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 258 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); 259 #else 260 static inline int dss_debugfs_create_file(const char *name, 261 void (*write)(struct seq_file *)) 262 { 263 return 0; 264 } 265 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 266 267 int dss_init_platform_driver(void) __init; 268 void dss_uninit_platform_driver(void); 269 270 int dss_runtime_get(void); 271 void dss_runtime_put(void); 272 273 unsigned long dss_get_dispc_clk_rate(void); 274 unsigned long dss_get_max_fck_rate(void); 275 enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel); 276 int dss_dpi_select_source(int port, enum omap_channel channel); 277 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 278 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 279 const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 280 void dss_dump_clocks(struct seq_file *s); 281 282 /* DSS VIDEO PLL */ 283 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, 284 struct regulator *regulator); 285 void dss_video_pll_uninit(struct dss_pll *pll); 286 287 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); 288 289 void dss_sdi_init(int datapairs); 290 int dss_sdi_enable(void); 291 void dss_sdi_disable(void); 292 293 void dss_select_dsi_clk_source(int dsi_module, 294 enum dss_clk_source clk_src); 295 void dss_select_lcd_clk_source(enum omap_channel channel, 296 enum dss_clk_source clk_src); 297 enum dss_clk_source dss_get_dispc_clk_source(void); 298 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module); 299 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 300 301 void dss_set_venc_output(enum omap_dss_venc_type type); 302 void dss_set_dac_pwrdn_bgz(bool enable); 303 304 int dss_set_fck_rate(unsigned long rate); 305 306 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 307 bool dss_div_calc(unsigned long pck, unsigned long fck_min, 308 dss_div_calc_func func, void *data); 309 310 /* SDI */ 311 #ifdef CONFIG_OMAP2_DSS_SDI 312 int sdi_init_port(struct platform_device *pdev, struct device_node *port); 313 void sdi_uninit_port(struct device_node *port); 314 #else 315 static inline int sdi_init_port(struct platform_device *pdev, 316 struct device_node *port) 317 { 318 return 0; 319 } 320 static inline void sdi_uninit_port(struct device_node *port) 321 { 322 } 323 #endif 324 325 /* DSI */ 326 327 #ifdef CONFIG_OMAP2_DSS_DSI 328 329 struct dentry; 330 struct file_operations; 331 332 int dsi_init_platform_driver(void) __init; 333 void dsi_uninit_platform_driver(void); 334 335 void dsi_dump_clocks(struct seq_file *s); 336 337 void dsi_irq_handler(void); 338 339 #endif 340 341 /* DPI */ 342 #ifdef CONFIG_OMAP2_DSS_DPI 343 int dpi_init_port(struct platform_device *pdev, struct device_node *port, 344 enum dss_model dss_model); 345 void dpi_uninit_port(struct device_node *port); 346 #else 347 static inline int dpi_init_port(struct platform_device *pdev, 348 struct device_node *port, enum dss_model dss_model) 349 { 350 return 0; 351 } 352 static inline void dpi_uninit_port(struct device_node *port) 353 { 354 } 355 #endif 356 357 /* DISPC */ 358 int dispc_init_platform_driver(void) __init; 359 void dispc_uninit_platform_driver(void); 360 void dispc_dump_clocks(struct seq_file *s); 361 362 int dispc_runtime_get(void); 363 void dispc_runtime_put(void); 364 365 void dispc_enable_sidle(void); 366 void dispc_disable_sidle(void); 367 368 void dispc_lcd_enable_signal(bool enable); 369 void dispc_pck_free_enable(bool enable); 370 void dispc_enable_fifomerge(bool enable); 371 void dispc_enable_gamma_table(bool enable); 372 373 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 374 unsigned long pck, void *data); 375 bool dispc_div_calc(unsigned long dispc, 376 unsigned long pck_min, unsigned long pck_max, 377 dispc_div_calc_func func, void *data); 378 379 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm); 380 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 381 struct dispc_clock_info *cinfo); 382 383 384 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 385 u32 high); 386 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 387 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 388 bool manual_update); 389 390 void dispc_mgr_set_clock_div(enum omap_channel channel, 391 const struct dispc_clock_info *cinfo); 392 int dispc_mgr_get_clock_div(enum omap_channel channel, 393 struct dispc_clock_info *cinfo); 394 void dispc_set_tv_pclk(unsigned long pclk); 395 396 u32 dispc_wb_get_framedone_irq(void); 397 bool dispc_wb_go_busy(void); 398 void dispc_wb_go(void); 399 void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 400 int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 401 bool mem_to_mem, const struct videomode *vm); 402 403 /* VENC */ 404 int venc_init_platform_driver(void) __init; 405 void venc_uninit_platform_driver(void); 406 407 /* HDMI */ 408 int hdmi4_init_platform_driver(void) __init; 409 void hdmi4_uninit_platform_driver(void); 410 411 int hdmi5_init_platform_driver(void) __init; 412 void hdmi5_uninit_platform_driver(void); 413 414 415 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 416 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 417 { 418 int b; 419 for (b = 0; b < 32; ++b) { 420 if (irqstatus & (1 << b)) 421 irq_arr[b]++; 422 } 423 } 424 #endif 425 426 /* PLL */ 427 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint, 428 unsigned long clkdco, void *data); 429 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, 430 void *data); 431 432 int dss_pll_register(struct dss_pll *pll); 433 void dss_pll_unregister(struct dss_pll *pll); 434 struct dss_pll *dss_pll_find(const char *name); 435 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src); 436 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 437 int dss_pll_enable(struct dss_pll *pll); 438 void dss_pll_disable(struct dss_pll *pll); 439 int dss_pll_set_config(struct dss_pll *pll, 440 const struct dss_pll_clock_info *cinfo); 441 442 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 443 unsigned long out_min, unsigned long out_max, 444 dss_hsdiv_calc_func func, void *data); 445 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 446 unsigned long pll_min, unsigned long pll_max, 447 dss_pll_calc_func func, void *data); 448 449 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 450 unsigned long target_clkout, struct dss_pll_clock_info *cinfo); 451 452 int dss_pll_write_config_type_a(struct dss_pll *pll, 453 const struct dss_pll_clock_info *cinfo); 454 int dss_pll_write_config_type_b(struct dss_pll *pll, 455 const struct dss_pll_clock_info *cinfo); 456 int dss_pll_wait_reset_done(struct dss_pll *pll); 457 458 #endif 459