1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef __OMAP2_DSS_H 22 #define __OMAP2_DSS_H 23 24 #include <linux/interrupt.h> 25 26 #include "omapdss.h" 27 28 struct dispc_device; 29 struct dss_debugfs_entry; 30 struct platform_device; 31 struct seq_file; 32 33 #define MAX_DSS_LCD_MANAGERS 3 34 #define MAX_NUM_DSI 2 35 36 #ifdef pr_fmt 37 #undef pr_fmt 38 #endif 39 40 #ifdef DSS_SUBSYS_NAME 41 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt 42 #else 43 #define pr_fmt(fmt) fmt 44 #endif 45 46 #define DSSDBG(format, ...) \ 47 pr_debug(format, ## __VA_ARGS__) 48 49 #ifdef DSS_SUBSYS_NAME 50 #define DSSERR(format, ...) \ 51 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__) 52 #else 53 #define DSSERR(format, ...) \ 54 pr_err("omapdss error: " format, ##__VA_ARGS__) 55 #endif 56 57 #ifdef DSS_SUBSYS_NAME 58 #define DSSINFO(format, ...) \ 59 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 60 #else 61 #define DSSINFO(format, ...) \ 62 pr_info("omapdss: " format, ## __VA_ARGS__) 63 #endif 64 65 #ifdef DSS_SUBSYS_NAME 66 #define DSSWARN(format, ...) \ 67 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 68 #else 69 #define DSSWARN(format, ...) \ 70 pr_warn("omapdss: " format, ##__VA_ARGS__) 71 #endif 72 73 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 74 number. For example 7:0 */ 75 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 76 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 77 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 78 #define FLD_MOD(orig, val, start, end) \ 79 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 80 81 enum dss_model { 82 DSS_MODEL_OMAP2, 83 DSS_MODEL_OMAP3, 84 DSS_MODEL_OMAP4, 85 DSS_MODEL_OMAP5, 86 DSS_MODEL_DRA7, 87 }; 88 89 enum dss_io_pad_mode { 90 DSS_IO_PAD_MODE_RESET, 91 DSS_IO_PAD_MODE_RFBI, 92 DSS_IO_PAD_MODE_BYPASS, 93 }; 94 95 enum dss_hdmi_venc_clk_source_select { 96 DSS_VENC_TV_CLK = 0, 97 DSS_HDMI_M_PCLK = 1, 98 }; 99 100 enum dss_dsi_content_type { 101 DSS_DSI_CONTENT_DCS, 102 DSS_DSI_CONTENT_GENERIC, 103 }; 104 105 enum dss_clk_source { 106 DSS_CLK_SRC_FCK = 0, 107 108 DSS_CLK_SRC_PLL1_1, 109 DSS_CLK_SRC_PLL1_2, 110 DSS_CLK_SRC_PLL1_3, 111 112 DSS_CLK_SRC_PLL2_1, 113 DSS_CLK_SRC_PLL2_2, 114 DSS_CLK_SRC_PLL2_3, 115 116 DSS_CLK_SRC_HDMI_PLL, 117 }; 118 119 enum dss_pll_id { 120 DSS_PLL_DSI1, 121 DSS_PLL_DSI2, 122 DSS_PLL_HDMI, 123 DSS_PLL_VIDEO1, 124 DSS_PLL_VIDEO2, 125 }; 126 127 struct dss_pll; 128 129 #define DSS_PLL_MAX_HSDIVS 4 130 131 enum dss_pll_type { 132 DSS_PLL_TYPE_A, 133 DSS_PLL_TYPE_B, 134 }; 135 136 /* 137 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. 138 * Type-B PLLs: clkout[0] refers to m2. 139 */ 140 struct dss_pll_clock_info { 141 /* rates that we get with dividers below */ 142 unsigned long fint; 143 unsigned long clkdco; 144 unsigned long clkout[DSS_PLL_MAX_HSDIVS]; 145 146 /* dividers */ 147 u16 n; 148 u16 m; 149 u32 mf; 150 u16 mX[DSS_PLL_MAX_HSDIVS]; 151 u16 sd; 152 }; 153 154 struct dss_pll_ops { 155 int (*enable)(struct dss_pll *pll); 156 void (*disable)(struct dss_pll *pll); 157 int (*set_config)(struct dss_pll *pll, 158 const struct dss_pll_clock_info *cinfo); 159 }; 160 161 struct dss_pll_hw { 162 enum dss_pll_type type; 163 164 unsigned int n_max; 165 unsigned int m_min; 166 unsigned int m_max; 167 unsigned int mX_max; 168 169 unsigned long fint_min, fint_max; 170 unsigned long clkdco_min, clkdco_low, clkdco_max; 171 172 u8 n_msb, n_lsb; 173 u8 m_msb, m_lsb; 174 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS]; 175 176 bool has_stopmode; 177 bool has_freqsel; 178 bool has_selfreqdco; 179 bool has_refsel; 180 181 /* DRA7 errata i886: use high N & M to avoid jitter */ 182 bool errata_i886; 183 }; 184 185 struct dss_pll { 186 const char *name; 187 enum dss_pll_id id; 188 struct dss_device *dss; 189 190 struct clk *clkin; 191 struct regulator *regulator; 192 193 void __iomem *base; 194 195 const struct dss_pll_hw *hw; 196 197 const struct dss_pll_ops *ops; 198 199 struct dss_pll_clock_info cinfo; 200 }; 201 202 /* Defines a generic omap register field */ 203 struct dss_reg_field { 204 u8 start, end; 205 }; 206 207 struct dispc_clock_info { 208 /* rates that we get with dividers below */ 209 unsigned long lck; 210 unsigned long pck; 211 212 /* dividers */ 213 u16 lck_div; 214 u16 pck_div; 215 }; 216 217 struct dss_lcd_mgr_config { 218 enum dss_io_pad_mode io_pad_mode; 219 220 bool stallmode; 221 bool fifohandcheck; 222 223 struct dispc_clock_info clock_info; 224 225 int video_port_width; 226 227 int lcden_sig_polarity; 228 }; 229 230 #define DSS_SZ_REGS SZ_512 231 232 struct dss_device { 233 struct platform_device *pdev; 234 void __iomem *base; 235 struct regmap *syscon_pll_ctrl; 236 u32 syscon_pll_ctrl_offset; 237 238 struct clk *parent_clk; 239 struct clk *dss_clk; 240 unsigned long dss_clk_rate; 241 242 unsigned long cache_req_pck; 243 unsigned long cache_prate; 244 struct dispc_clock_info cache_dispc_cinfo; 245 246 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 247 enum dss_clk_source dispc_clk_source; 248 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 249 250 bool ctx_valid; 251 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 252 253 const struct dss_features *feat; 254 255 struct { 256 struct dentry *root; 257 struct dss_debugfs_entry *clk; 258 struct dss_debugfs_entry *dss; 259 } debugfs; 260 261 struct dss_pll *plls[4]; 262 struct dss_pll *video1_pll; 263 struct dss_pll *video2_pll; 264 265 struct dispc_device *dispc; 266 const struct dispc_ops *dispc_ops; 267 }; 268 269 /* core */ 270 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput) 271 { 272 /* To be implemented when the OMAP platform will provide this feature */ 273 return 0; 274 } 275 276 static inline bool dss_mgr_is_lcd(enum omap_channel id) 277 { 278 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || 279 id == OMAP_DSS_CHANNEL_LCD3) 280 return true; 281 else 282 return false; 283 } 284 285 /* DSS */ 286 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 287 struct dss_debugfs_entry * 288 dss_debugfs_create_file(struct dss_device *dss, const char *name, 289 int (*show_fn)(struct seq_file *s, void *data), 290 void *data); 291 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry); 292 #else 293 static inline struct dss_debugfs_entry * 294 dss_debugfs_create_file(struct dss_device *dss, const char *name, 295 int (*show_fn)(struct seq_file *s, void *data), 296 void *data) 297 { 298 return NULL; 299 } 300 301 static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry) 302 { 303 } 304 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 305 306 struct dss_device *dss_get_device(struct device *dev); 307 308 int dss_runtime_get(struct dss_device *dss); 309 void dss_runtime_put(struct dss_device *dss); 310 311 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss); 312 unsigned long dss_get_max_fck_rate(struct dss_device *dss); 313 enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss, 314 enum omap_channel channel); 315 int dss_dpi_select_source(struct dss_device *dss, int port, 316 enum omap_channel channel); 317 void dss_select_hdmi_venc_clk_source(struct dss_device *dss, 318 enum dss_hdmi_venc_clk_source_select src); 319 const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 320 321 /* DSS VIDEO PLL */ 322 struct dss_pll *dss_video_pll_init(struct dss_device *dss, 323 struct platform_device *pdev, int id, 324 struct regulator *regulator); 325 void dss_video_pll_uninit(struct dss_pll *pll); 326 327 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable); 328 329 void dss_sdi_init(struct dss_device *dss, int datapairs); 330 int dss_sdi_enable(struct dss_device *dss); 331 void dss_sdi_disable(struct dss_device *dss); 332 333 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module, 334 enum dss_clk_source clk_src); 335 void dss_select_lcd_clk_source(struct dss_device *dss, 336 enum omap_channel channel, 337 enum dss_clk_source clk_src); 338 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss); 339 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss, 340 int dsi_module); 341 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss, 342 enum omap_channel channel); 343 344 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type); 345 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable); 346 347 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate); 348 349 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 350 bool dss_div_calc(struct dss_device *dss, unsigned long pck, 351 unsigned long fck_min, dss_div_calc_func func, void *data); 352 353 /* SDI */ 354 #ifdef CONFIG_OMAP2_DSS_SDI 355 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 356 struct device_node *port); 357 void sdi_uninit_port(struct device_node *port); 358 #else 359 static inline int sdi_init_port(struct dss_device *dss, 360 struct platform_device *pdev, 361 struct device_node *port) 362 { 363 return 0; 364 } 365 static inline void sdi_uninit_port(struct device_node *port) 366 { 367 } 368 #endif 369 370 /* DSI */ 371 372 #ifdef CONFIG_OMAP2_DSS_DSI 373 374 void dsi_dump_clocks(struct seq_file *s); 375 376 void dsi_irq_handler(void); 377 378 #endif 379 380 /* DPI */ 381 #ifdef CONFIG_OMAP2_DSS_DPI 382 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 383 struct device_node *port, enum dss_model dss_model); 384 void dpi_uninit_port(struct device_node *port); 385 #else 386 static inline int dpi_init_port(struct dss_device *dss, 387 struct platform_device *pdev, 388 struct device_node *port, 389 enum dss_model dss_model) 390 { 391 return 0; 392 } 393 static inline void dpi_uninit_port(struct device_node *port) 394 { 395 } 396 #endif 397 398 /* DISPC */ 399 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s); 400 401 int dispc_runtime_get(struct dispc_device *dispc); 402 void dispc_runtime_put(struct dispc_device *dispc); 403 404 void dispc_enable_sidle(struct dispc_device *dispc); 405 void dispc_disable_sidle(struct dispc_device *dispc); 406 407 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable); 408 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable); 409 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable); 410 411 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 412 unsigned long pck, void *data); 413 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, 414 unsigned long pck_min, unsigned long pck_max, 415 dispc_div_calc_func func, void *data); 416 417 bool dispc_mgr_timings_ok(struct dispc_device *dispc, 418 enum omap_channel channel, 419 const struct videomode *vm); 420 int dispc_calc_clock_rates(struct dispc_device *dispc, 421 unsigned long dispc_fclk_rate, 422 struct dispc_clock_info *cinfo); 423 424 425 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, 426 enum omap_plane_id plane, u32 low, u32 high); 427 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, 428 enum omap_plane_id plane, 429 u32 *fifo_low, u32 *fifo_high, 430 bool use_fifomerge, bool manual_update); 431 432 void dispc_mgr_set_clock_div(struct dispc_device *dispc, 433 enum omap_channel channel, 434 const struct dispc_clock_info *cinfo); 435 int dispc_mgr_get_clock_div(struct dispc_device *dispc, 436 enum omap_channel channel, 437 struct dispc_clock_info *cinfo); 438 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk); 439 440 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 441 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr) 442 { 443 int b; 444 for (b = 0; b < 32; ++b) { 445 if (irqstatus & (1 << b)) 446 irq_arr[b]++; 447 } 448 } 449 #endif 450 451 /* PLL */ 452 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint, 453 unsigned long clkdco, void *data); 454 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, 455 void *data); 456 457 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll); 458 void dss_pll_unregister(struct dss_pll *pll); 459 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name); 460 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss, 461 enum dss_clk_source src); 462 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 463 int dss_pll_enable(struct dss_pll *pll); 464 void dss_pll_disable(struct dss_pll *pll); 465 int dss_pll_set_config(struct dss_pll *pll, 466 const struct dss_pll_clock_info *cinfo); 467 468 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 469 unsigned long out_min, unsigned long out_max, 470 dss_hsdiv_calc_func func, void *data); 471 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 472 unsigned long pll_min, unsigned long pll_max, 473 dss_pll_calc_func func, void *data); 474 475 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 476 unsigned long target_clkout, struct dss_pll_clock_info *cinfo); 477 478 int dss_pll_write_config_type_a(struct dss_pll *pll, 479 const struct dss_pll_clock_info *cinfo); 480 int dss_pll_write_config_type_b(struct dss_pll *pll, 481 const struct dss_pll_clock_info *cinfo); 482 int dss_pll_wait_reset_done(struct dss_pll *pll); 483 484 extern struct platform_driver omap_dsshw_driver; 485 extern struct platform_driver omap_dispchw_driver; 486 #ifdef CONFIG_OMAP2_DSS_DSI 487 extern struct platform_driver omap_dsihw_driver; 488 #endif 489 #ifdef CONFIG_OMAP2_DSS_VENC 490 extern struct platform_driver omap_venchw_driver; 491 #endif 492 #ifdef CONFIG_OMAP4_DSS_HDMI 493 extern struct platform_driver omapdss_hdmi4hw_driver; 494 #endif 495 #ifdef CONFIG_OMAP5_DSS_HDMI 496 extern struct platform_driver omapdss_hdmi5hw_driver; 497 #endif 498 499 #endif 500