1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "DSS" 22 23 #include <linux/debugfs.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/io.h> 28 #include <linux/export.h> 29 #include <linux/err.h> 30 #include <linux/delay.h> 31 #include <linux/seq_file.h> 32 #include <linux/clk.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/gfp.h> 37 #include <linux/sizes.h> 38 #include <linux/mfd/syscon.h> 39 #include <linux/regmap.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/of_graph.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/suspend.h> 45 #include <linux/component.h> 46 #include <linux/sys_soc.h> 47 48 #include "omapdss.h" 49 #include "dss.h" 50 51 #define DSS_SZ_REGS SZ_512 52 53 struct dss_reg { 54 u16 idx; 55 }; 56 57 #define DSS_REG(idx) ((const struct dss_reg) { idx }) 58 59 #define DSS_REVISION DSS_REG(0x0000) 60 #define DSS_SYSCONFIG DSS_REG(0x0010) 61 #define DSS_SYSSTATUS DSS_REG(0x0014) 62 #define DSS_CONTROL DSS_REG(0x0040) 63 #define DSS_SDI_CONTROL DSS_REG(0x0044) 64 #define DSS_PLL_CONTROL DSS_REG(0x0048) 65 #define DSS_SDI_STATUS DSS_REG(0x005C) 66 67 #define REG_GET(idx, start, end) \ 68 FLD_GET(dss_read_reg(idx), start, end) 69 70 #define REG_FLD_MOD(idx, val, start, end) \ 71 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 72 73 struct dss_ops { 74 int (*dpi_select_source)(int port, enum omap_channel channel); 75 int (*select_lcd_source)(enum omap_channel channel, 76 enum dss_clk_source clk_src); 77 }; 78 79 struct dss_features { 80 enum dss_model model; 81 u8 fck_div_max; 82 unsigned int fck_freq_max; 83 u8 dss_fck_multiplier; 84 const char *parent_clk_name; 85 const enum omap_display_type *ports; 86 int num_ports; 87 const enum omap_dss_output_id *outputs; 88 const struct dss_ops *ops; 89 struct dss_reg_field dispc_clk_switch; 90 bool has_lcd_clk_src; 91 }; 92 93 static struct { 94 struct platform_device *pdev; 95 void __iomem *base; 96 struct regmap *syscon_pll_ctrl; 97 u32 syscon_pll_ctrl_offset; 98 99 struct clk *parent_clk; 100 struct clk *dss_clk; 101 unsigned long dss_clk_rate; 102 103 unsigned long cache_req_pck; 104 unsigned long cache_prate; 105 struct dispc_clock_info cache_dispc_cinfo; 106 107 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 108 enum dss_clk_source dispc_clk_source; 109 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 110 111 bool ctx_valid; 112 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 113 114 const struct dss_features *feat; 115 116 struct dss_pll *video1_pll; 117 struct dss_pll *video2_pll; 118 } dss; 119 120 static const char * const dss_generic_clk_source_names[] = { 121 [DSS_CLK_SRC_FCK] = "FCK", 122 [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 123 [DSS_CLK_SRC_PLL1_2] = "PLL1:2", 124 [DSS_CLK_SRC_PLL1_3] = "PLL1:3", 125 [DSS_CLK_SRC_PLL2_1] = "PLL2:1", 126 [DSS_CLK_SRC_PLL2_2] = "PLL2:2", 127 [DSS_CLK_SRC_PLL2_3] = "PLL2:3", 128 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 129 }; 130 131 static inline void dss_write_reg(const struct dss_reg idx, u32 val) 132 { 133 __raw_writel(val, dss.base + idx.idx); 134 } 135 136 static inline u32 dss_read_reg(const struct dss_reg idx) 137 { 138 return __raw_readl(dss.base + idx.idx); 139 } 140 141 #define SR(reg) \ 142 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) 143 #define RR(reg) \ 144 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) 145 146 static void dss_save_context(void) 147 { 148 DSSDBG("dss_save_context\n"); 149 150 SR(CONTROL); 151 152 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 153 SR(SDI_CONTROL); 154 SR(PLL_CONTROL); 155 } 156 157 dss.ctx_valid = true; 158 159 DSSDBG("context saved\n"); 160 } 161 162 static void dss_restore_context(void) 163 { 164 DSSDBG("dss_restore_context\n"); 165 166 if (!dss.ctx_valid) 167 return; 168 169 RR(CONTROL); 170 171 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 172 RR(SDI_CONTROL); 173 RR(PLL_CONTROL); 174 } 175 176 DSSDBG("context restored\n"); 177 } 178 179 #undef SR 180 #undef RR 181 182 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) 183 { 184 unsigned shift; 185 unsigned val; 186 187 if (!dss.syscon_pll_ctrl) 188 return; 189 190 val = !enable; 191 192 switch (pll_id) { 193 case DSS_PLL_VIDEO1: 194 shift = 0; 195 break; 196 case DSS_PLL_VIDEO2: 197 shift = 1; 198 break; 199 case DSS_PLL_HDMI: 200 shift = 2; 201 break; 202 default: 203 DSSERR("illegal DSS PLL ID %d\n", pll_id); 204 return; 205 } 206 207 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 208 1 << shift, val << shift); 209 } 210 211 static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, 212 enum omap_channel channel) 213 { 214 unsigned shift, val; 215 216 if (!dss.syscon_pll_ctrl) 217 return -EINVAL; 218 219 switch (channel) { 220 case OMAP_DSS_CHANNEL_LCD: 221 shift = 3; 222 223 switch (clk_src) { 224 case DSS_CLK_SRC_PLL1_1: 225 val = 0; break; 226 case DSS_CLK_SRC_HDMI_PLL: 227 val = 1; break; 228 default: 229 DSSERR("error in PLL mux config for LCD\n"); 230 return -EINVAL; 231 } 232 233 break; 234 case OMAP_DSS_CHANNEL_LCD2: 235 shift = 5; 236 237 switch (clk_src) { 238 case DSS_CLK_SRC_PLL1_3: 239 val = 0; break; 240 case DSS_CLK_SRC_PLL2_3: 241 val = 1; break; 242 case DSS_CLK_SRC_HDMI_PLL: 243 val = 2; break; 244 default: 245 DSSERR("error in PLL mux config for LCD2\n"); 246 return -EINVAL; 247 } 248 249 break; 250 case OMAP_DSS_CHANNEL_LCD3: 251 shift = 7; 252 253 switch (clk_src) { 254 case DSS_CLK_SRC_PLL2_1: 255 val = 0; break; 256 case DSS_CLK_SRC_PLL1_3: 257 val = 1; break; 258 case DSS_CLK_SRC_HDMI_PLL: 259 val = 2; break; 260 default: 261 DSSERR("error in PLL mux config for LCD3\n"); 262 return -EINVAL; 263 } 264 265 break; 266 default: 267 DSSERR("error in PLL mux config\n"); 268 return -EINVAL; 269 } 270 271 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 272 0x3 << shift, val << shift); 273 274 return 0; 275 } 276 277 void dss_sdi_init(int datapairs) 278 { 279 u32 l; 280 281 BUG_ON(datapairs > 3 || datapairs < 1); 282 283 l = dss_read_reg(DSS_SDI_CONTROL); 284 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 285 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 286 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 287 dss_write_reg(DSS_SDI_CONTROL, l); 288 289 l = dss_read_reg(DSS_PLL_CONTROL); 290 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 291 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 292 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 293 dss_write_reg(DSS_PLL_CONTROL, l); 294 } 295 296 int dss_sdi_enable(void) 297 { 298 unsigned long timeout; 299 300 dispc_pck_free_enable(1); 301 302 /* Reset SDI PLL */ 303 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 304 udelay(1); /* wait 2x PCLK */ 305 306 /* Lock SDI PLL */ 307 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 308 309 /* Waiting for PLL lock request to complete */ 310 timeout = jiffies + msecs_to_jiffies(500); 311 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { 312 if (time_after_eq(jiffies, timeout)) { 313 DSSERR("PLL lock request timed out\n"); 314 goto err1; 315 } 316 } 317 318 /* Clearing PLL_GO bit */ 319 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 320 321 /* Waiting for PLL to lock */ 322 timeout = jiffies + msecs_to_jiffies(500); 323 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { 324 if (time_after_eq(jiffies, timeout)) { 325 DSSERR("PLL lock timed out\n"); 326 goto err1; 327 } 328 } 329 330 dispc_lcd_enable_signal(1); 331 332 /* Waiting for SDI reset to complete */ 333 timeout = jiffies + msecs_to_jiffies(500); 334 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { 335 if (time_after_eq(jiffies, timeout)) { 336 DSSERR("SDI reset timed out\n"); 337 goto err2; 338 } 339 } 340 341 return 0; 342 343 err2: 344 dispc_lcd_enable_signal(0); 345 err1: 346 /* Reset SDI PLL */ 347 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 348 349 dispc_pck_free_enable(0); 350 351 return -ETIMEDOUT; 352 } 353 354 void dss_sdi_disable(void) 355 { 356 dispc_lcd_enable_signal(0); 357 358 dispc_pck_free_enable(0); 359 360 /* Reset SDI PLL */ 361 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 362 } 363 364 const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 365 { 366 return dss_generic_clk_source_names[clk_src]; 367 } 368 369 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 370 static void dss_dump_clocks(struct seq_file *s) 371 { 372 const char *fclk_name; 373 unsigned long fclk_rate; 374 375 if (dss_runtime_get()) 376 return; 377 378 seq_printf(s, "- DSS -\n"); 379 380 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 381 fclk_rate = clk_get_rate(dss.dss_clk); 382 383 seq_printf(s, "%s = %lu\n", 384 fclk_name, 385 fclk_rate); 386 387 dss_runtime_put(); 388 } 389 #endif 390 391 static void dss_dump_regs(struct seq_file *s) 392 { 393 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 394 395 if (dss_runtime_get()) 396 return; 397 398 DUMPREG(DSS_REVISION); 399 DUMPREG(DSS_SYSCONFIG); 400 DUMPREG(DSS_SYSSTATUS); 401 DUMPREG(DSS_CONTROL); 402 403 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 404 DUMPREG(DSS_SDI_CONTROL); 405 DUMPREG(DSS_PLL_CONTROL); 406 DUMPREG(DSS_SDI_STATUS); 407 } 408 409 dss_runtime_put(); 410 #undef DUMPREG 411 } 412 413 static int dss_get_channel_index(enum omap_channel channel) 414 { 415 switch (channel) { 416 case OMAP_DSS_CHANNEL_LCD: 417 return 0; 418 case OMAP_DSS_CHANNEL_LCD2: 419 return 1; 420 case OMAP_DSS_CHANNEL_LCD3: 421 return 2; 422 default: 423 WARN_ON(1); 424 return 0; 425 } 426 } 427 428 static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 429 { 430 int b; 431 432 /* 433 * We always use PRCM clock as the DISPC func clock, except on DSS3, 434 * where we don't have separate DISPC and LCD clock sources. 435 */ 436 if (WARN_ON(dss.feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) 437 return; 438 439 switch (clk_src) { 440 case DSS_CLK_SRC_FCK: 441 b = 0; 442 break; 443 case DSS_CLK_SRC_PLL1_1: 444 b = 1; 445 break; 446 case DSS_CLK_SRC_PLL2_1: 447 b = 2; 448 break; 449 default: 450 BUG(); 451 return; 452 } 453 454 REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ 455 dss.feat->dispc_clk_switch.start, 456 dss.feat->dispc_clk_switch.end); 457 458 dss.dispc_clk_source = clk_src; 459 } 460 461 void dss_select_dsi_clk_source(int dsi_module, 462 enum dss_clk_source clk_src) 463 { 464 int b, pos; 465 466 switch (clk_src) { 467 case DSS_CLK_SRC_FCK: 468 b = 0; 469 break; 470 case DSS_CLK_SRC_PLL1_2: 471 BUG_ON(dsi_module != 0); 472 b = 1; 473 break; 474 case DSS_CLK_SRC_PLL2_2: 475 BUG_ON(dsi_module != 1); 476 b = 1; 477 break; 478 default: 479 BUG(); 480 return; 481 } 482 483 pos = dsi_module == 0 ? 1 : 10; 484 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 485 486 dss.dsi_clk_source[dsi_module] = clk_src; 487 } 488 489 static int dss_lcd_clk_mux_dra7(enum omap_channel channel, 490 enum dss_clk_source clk_src) 491 { 492 const u8 ctrl_bits[] = { 493 [OMAP_DSS_CHANNEL_LCD] = 0, 494 [OMAP_DSS_CHANNEL_LCD2] = 12, 495 [OMAP_DSS_CHANNEL_LCD3] = 19, 496 }; 497 498 u8 ctrl_bit = ctrl_bits[channel]; 499 int r; 500 501 if (clk_src == DSS_CLK_SRC_FCK) { 502 /* LCDx_CLK_SWITCH */ 503 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 504 return -EINVAL; 505 } 506 507 r = dss_ctrl_pll_set_control_mux(clk_src, channel); 508 if (r) 509 return r; 510 511 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 512 513 return 0; 514 } 515 516 static int dss_lcd_clk_mux_omap5(enum omap_channel channel, 517 enum dss_clk_source clk_src) 518 { 519 const u8 ctrl_bits[] = { 520 [OMAP_DSS_CHANNEL_LCD] = 0, 521 [OMAP_DSS_CHANNEL_LCD2] = 12, 522 [OMAP_DSS_CHANNEL_LCD3] = 19, 523 }; 524 const enum dss_clk_source allowed_plls[] = { 525 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 526 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, 527 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, 528 }; 529 530 u8 ctrl_bit = ctrl_bits[channel]; 531 532 if (clk_src == DSS_CLK_SRC_FCK) { 533 /* LCDx_CLK_SWITCH */ 534 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 535 return -EINVAL; 536 } 537 538 if (WARN_ON(allowed_plls[channel] != clk_src)) 539 return -EINVAL; 540 541 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 542 543 return 0; 544 } 545 546 static int dss_lcd_clk_mux_omap4(enum omap_channel channel, 547 enum dss_clk_source clk_src) 548 { 549 const u8 ctrl_bits[] = { 550 [OMAP_DSS_CHANNEL_LCD] = 0, 551 [OMAP_DSS_CHANNEL_LCD2] = 12, 552 }; 553 const enum dss_clk_source allowed_plls[] = { 554 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 555 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, 556 }; 557 558 u8 ctrl_bit = ctrl_bits[channel]; 559 560 if (clk_src == DSS_CLK_SRC_FCK) { 561 /* LCDx_CLK_SWITCH */ 562 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 563 return 0; 564 } 565 566 if (WARN_ON(allowed_plls[channel] != clk_src)) 567 return -EINVAL; 568 569 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 570 571 return 0; 572 } 573 574 void dss_select_lcd_clk_source(enum omap_channel channel, 575 enum dss_clk_source clk_src) 576 { 577 int idx = dss_get_channel_index(channel); 578 int r; 579 580 if (!dss.feat->has_lcd_clk_src) { 581 dss_select_dispc_clk_source(clk_src); 582 dss.lcd_clk_source[idx] = clk_src; 583 return; 584 } 585 586 r = dss.feat->ops->select_lcd_source(channel, clk_src); 587 if (r) 588 return; 589 590 dss.lcd_clk_source[idx] = clk_src; 591 } 592 593 enum dss_clk_source dss_get_dispc_clk_source(void) 594 { 595 return dss.dispc_clk_source; 596 } 597 598 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) 599 { 600 return dss.dsi_clk_source[dsi_module]; 601 } 602 603 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 604 { 605 if (dss.feat->has_lcd_clk_src) { 606 int idx = dss_get_channel_index(channel); 607 return dss.lcd_clk_source[idx]; 608 } else { 609 /* LCD_CLK source is the same as DISPC_FCLK source for 610 * OMAP2 and OMAP3 */ 611 return dss.dispc_clk_source; 612 } 613 } 614 615 bool dss_div_calc(unsigned long pck, unsigned long fck_min, 616 dss_div_calc_func func, void *data) 617 { 618 int fckd, fckd_start, fckd_stop; 619 unsigned long fck; 620 unsigned long fck_hw_max; 621 unsigned long fckd_hw_max; 622 unsigned long prate; 623 unsigned m; 624 625 fck_hw_max = dss.feat->fck_freq_max; 626 627 if (dss.parent_clk == NULL) { 628 unsigned pckd; 629 630 pckd = fck_hw_max / pck; 631 632 fck = pck * pckd; 633 634 fck = clk_round_rate(dss.dss_clk, fck); 635 636 return func(fck, data); 637 } 638 639 fckd_hw_max = dss.feat->fck_div_max; 640 641 m = dss.feat->dss_fck_multiplier; 642 prate = clk_get_rate(dss.parent_clk); 643 644 fck_min = fck_min ? fck_min : 1; 645 646 fckd_start = min(prate * m / fck_min, fckd_hw_max); 647 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); 648 649 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { 650 fck = DIV_ROUND_UP(prate, fckd) * m; 651 652 if (func(fck, data)) 653 return true; 654 } 655 656 return false; 657 } 658 659 int dss_set_fck_rate(unsigned long rate) 660 { 661 int r; 662 663 DSSDBG("set fck to %lu\n", rate); 664 665 r = clk_set_rate(dss.dss_clk, rate); 666 if (r) 667 return r; 668 669 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 670 671 WARN_ONCE(dss.dss_clk_rate != rate, 672 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, 673 rate); 674 675 return 0; 676 } 677 678 unsigned long dss_get_dispc_clk_rate(void) 679 { 680 return dss.dss_clk_rate; 681 } 682 683 unsigned long dss_get_max_fck_rate(void) 684 { 685 return dss.feat->fck_freq_max; 686 } 687 688 enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel) 689 { 690 return dss.feat->outputs[channel]; 691 } 692 693 static int dss_setup_default_clock(void) 694 { 695 unsigned long max_dss_fck, prate; 696 unsigned long fck; 697 unsigned fck_div; 698 int r; 699 700 max_dss_fck = dss.feat->fck_freq_max; 701 702 if (dss.parent_clk == NULL) { 703 fck = clk_round_rate(dss.dss_clk, max_dss_fck); 704 } else { 705 prate = clk_get_rate(dss.parent_clk); 706 707 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, 708 max_dss_fck); 709 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; 710 } 711 712 r = dss_set_fck_rate(fck); 713 if (r) 714 return r; 715 716 return 0; 717 } 718 719 void dss_set_venc_output(enum omap_dss_venc_type type) 720 { 721 int l = 0; 722 723 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) 724 l = 0; 725 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) 726 l = 1; 727 else 728 BUG(); 729 730 /* venc out selection. 0 = comp, 1 = svideo */ 731 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); 732 } 733 734 void dss_set_dac_pwrdn_bgz(bool enable) 735 { 736 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ 737 } 738 739 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) 740 { 741 enum omap_dss_output_id outputs; 742 743 outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; 744 745 /* Complain about invalid selections */ 746 WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC)); 747 WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI)); 748 749 /* Select only if we have options */ 750 if ((outputs & OMAP_DSS_OUTPUT_VENC) && 751 (outputs & OMAP_DSS_OUTPUT_HDMI)) 752 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ 753 } 754 755 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) 756 { 757 enum omap_dss_output_id outputs; 758 759 outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; 760 if ((outputs & OMAP_DSS_OUTPUT_HDMI) == 0) 761 return DSS_VENC_TV_CLK; 762 763 if ((outputs & OMAP_DSS_OUTPUT_VENC) == 0) 764 return DSS_HDMI_M_PCLK; 765 766 return REG_GET(DSS_CONTROL, 15, 15); 767 } 768 769 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) 770 { 771 if (channel != OMAP_DSS_CHANNEL_LCD) 772 return -EINVAL; 773 774 return 0; 775 } 776 777 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) 778 { 779 int val; 780 781 switch (channel) { 782 case OMAP_DSS_CHANNEL_LCD2: 783 val = 0; 784 break; 785 case OMAP_DSS_CHANNEL_DIGIT: 786 val = 1; 787 break; 788 default: 789 return -EINVAL; 790 } 791 792 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); 793 794 return 0; 795 } 796 797 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) 798 { 799 int val; 800 801 switch (channel) { 802 case OMAP_DSS_CHANNEL_LCD: 803 val = 1; 804 break; 805 case OMAP_DSS_CHANNEL_LCD2: 806 val = 2; 807 break; 808 case OMAP_DSS_CHANNEL_LCD3: 809 val = 3; 810 break; 811 case OMAP_DSS_CHANNEL_DIGIT: 812 val = 0; 813 break; 814 default: 815 return -EINVAL; 816 } 817 818 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); 819 820 return 0; 821 } 822 823 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) 824 { 825 switch (port) { 826 case 0: 827 return dss_dpi_select_source_omap5(port, channel); 828 case 1: 829 if (channel != OMAP_DSS_CHANNEL_LCD2) 830 return -EINVAL; 831 break; 832 case 2: 833 if (channel != OMAP_DSS_CHANNEL_LCD3) 834 return -EINVAL; 835 break; 836 default: 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 int dss_dpi_select_source(int port, enum omap_channel channel) 844 { 845 return dss.feat->ops->dpi_select_source(port, channel); 846 } 847 848 static int dss_get_clocks(void) 849 { 850 struct clk *clk; 851 852 clk = devm_clk_get(&dss.pdev->dev, "fck"); 853 if (IS_ERR(clk)) { 854 DSSERR("can't get clock fck\n"); 855 return PTR_ERR(clk); 856 } 857 858 dss.dss_clk = clk; 859 860 if (dss.feat->parent_clk_name) { 861 clk = clk_get(NULL, dss.feat->parent_clk_name); 862 if (IS_ERR(clk)) { 863 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); 864 return PTR_ERR(clk); 865 } 866 } else { 867 clk = NULL; 868 } 869 870 dss.parent_clk = clk; 871 872 return 0; 873 } 874 875 static void dss_put_clocks(void) 876 { 877 if (dss.parent_clk) 878 clk_put(dss.parent_clk); 879 } 880 881 int dss_runtime_get(void) 882 { 883 int r; 884 885 DSSDBG("dss_runtime_get\n"); 886 887 r = pm_runtime_get_sync(&dss.pdev->dev); 888 WARN_ON(r < 0); 889 return r < 0 ? r : 0; 890 } 891 892 void dss_runtime_put(void) 893 { 894 int r; 895 896 DSSDBG("dss_runtime_put\n"); 897 898 r = pm_runtime_put_sync(&dss.pdev->dev); 899 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); 900 } 901 902 /* DEBUGFS */ 903 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 904 static void dss_debug_dump_clocks(struct seq_file *s) 905 { 906 dss_dump_clocks(s); 907 dispc_dump_clocks(s); 908 #ifdef CONFIG_OMAP2_DSS_DSI 909 dsi_dump_clocks(s); 910 #endif 911 } 912 913 static int dss_debug_show(struct seq_file *s, void *unused) 914 { 915 void (*func)(struct seq_file *) = s->private; 916 917 func(s); 918 return 0; 919 } 920 921 static int dss_debug_open(struct inode *inode, struct file *file) 922 { 923 return single_open(file, dss_debug_show, inode->i_private); 924 } 925 926 static const struct file_operations dss_debug_fops = { 927 .open = dss_debug_open, 928 .read = seq_read, 929 .llseek = seq_lseek, 930 .release = single_release, 931 }; 932 933 static struct dentry *dss_debugfs_dir; 934 935 static int dss_initialize_debugfs(void) 936 { 937 dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); 938 if (IS_ERR(dss_debugfs_dir)) { 939 int err = PTR_ERR(dss_debugfs_dir); 940 941 dss_debugfs_dir = NULL; 942 return err; 943 } 944 945 debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, 946 &dss_debug_dump_clocks, &dss_debug_fops); 947 948 return 0; 949 } 950 951 static void dss_uninitialize_debugfs(void) 952 { 953 if (dss_debugfs_dir) 954 debugfs_remove_recursive(dss_debugfs_dir); 955 } 956 957 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)) 958 { 959 struct dentry *d; 960 961 d = debugfs_create_file(name, S_IRUGO, dss_debugfs_dir, 962 write, &dss_debug_fops); 963 964 return PTR_ERR_OR_ZERO(d); 965 } 966 #else /* CONFIG_OMAP2_DSS_DEBUGFS */ 967 static inline int dss_initialize_debugfs(void) 968 { 969 return 0; 970 } 971 static inline void dss_uninitialize_debugfs(void) 972 { 973 } 974 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 975 976 static const struct dss_ops dss_ops_omap2_omap3 = { 977 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 978 }; 979 980 static const struct dss_ops dss_ops_omap4 = { 981 .dpi_select_source = &dss_dpi_select_source_omap4, 982 .select_lcd_source = &dss_lcd_clk_mux_omap4, 983 }; 984 985 static const struct dss_ops dss_ops_omap5 = { 986 .dpi_select_source = &dss_dpi_select_source_omap5, 987 .select_lcd_source = &dss_lcd_clk_mux_omap5, 988 }; 989 990 static const struct dss_ops dss_ops_dra7 = { 991 .dpi_select_source = &dss_dpi_select_source_dra7xx, 992 .select_lcd_source = &dss_lcd_clk_mux_dra7, 993 }; 994 995 static const enum omap_display_type omap2plus_ports[] = { 996 OMAP_DISPLAY_TYPE_DPI, 997 }; 998 999 static const enum omap_display_type omap34xx_ports[] = { 1000 OMAP_DISPLAY_TYPE_DPI, 1001 OMAP_DISPLAY_TYPE_SDI, 1002 }; 1003 1004 static const enum omap_display_type dra7xx_ports[] = { 1005 OMAP_DISPLAY_TYPE_DPI, 1006 OMAP_DISPLAY_TYPE_DPI, 1007 OMAP_DISPLAY_TYPE_DPI, 1008 }; 1009 1010 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { 1011 /* OMAP_DSS_CHANNEL_LCD */ 1012 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, 1013 1014 /* OMAP_DSS_CHANNEL_DIGIT */ 1015 OMAP_DSS_OUTPUT_VENC, 1016 }; 1017 1018 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = { 1019 /* OMAP_DSS_CHANNEL_LCD */ 1020 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1021 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1, 1022 1023 /* OMAP_DSS_CHANNEL_DIGIT */ 1024 OMAP_DSS_OUTPUT_VENC, 1025 }; 1026 1027 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { 1028 /* OMAP_DSS_CHANNEL_LCD */ 1029 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1030 OMAP_DSS_OUTPUT_DSI1, 1031 1032 /* OMAP_DSS_CHANNEL_DIGIT */ 1033 OMAP_DSS_OUTPUT_VENC, 1034 }; 1035 1036 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { 1037 /* OMAP_DSS_CHANNEL_LCD */ 1038 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, 1039 }; 1040 1041 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { 1042 /* OMAP_DSS_CHANNEL_LCD */ 1043 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, 1044 1045 /* OMAP_DSS_CHANNEL_DIGIT */ 1046 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI, 1047 1048 /* OMAP_DSS_CHANNEL_LCD2 */ 1049 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1050 OMAP_DSS_OUTPUT_DSI2, 1051 }; 1052 1053 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { 1054 /* OMAP_DSS_CHANNEL_LCD */ 1055 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1056 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2, 1057 1058 /* OMAP_DSS_CHANNEL_DIGIT */ 1059 OMAP_DSS_OUTPUT_HDMI, 1060 1061 /* OMAP_DSS_CHANNEL_LCD2 */ 1062 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1063 OMAP_DSS_OUTPUT_DSI1, 1064 1065 /* OMAP_DSS_CHANNEL_LCD3 */ 1066 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1067 OMAP_DSS_OUTPUT_DSI2, 1068 }; 1069 1070 static const struct dss_features omap24xx_dss_feats = { 1071 .model = DSS_MODEL_OMAP2, 1072 /* 1073 * fck div max is really 16, but the divider range has gaps. The range 1074 * from 1 to 6 has no gaps, so let's use that as a max. 1075 */ 1076 .fck_div_max = 6, 1077 .fck_freq_max = 133000000, 1078 .dss_fck_multiplier = 2, 1079 .parent_clk_name = "core_ck", 1080 .ports = omap2plus_ports, 1081 .num_ports = ARRAY_SIZE(omap2plus_ports), 1082 .outputs = omap2_dss_supported_outputs, 1083 .ops = &dss_ops_omap2_omap3, 1084 .dispc_clk_switch = { 0, 0 }, 1085 .has_lcd_clk_src = false, 1086 }; 1087 1088 static const struct dss_features omap34xx_dss_feats = { 1089 .model = DSS_MODEL_OMAP3, 1090 .fck_div_max = 16, 1091 .fck_freq_max = 173000000, 1092 .dss_fck_multiplier = 2, 1093 .parent_clk_name = "dpll4_ck", 1094 .ports = omap34xx_ports, 1095 .outputs = omap3430_dss_supported_outputs, 1096 .num_ports = ARRAY_SIZE(omap34xx_ports), 1097 .ops = &dss_ops_omap2_omap3, 1098 .dispc_clk_switch = { 0, 0 }, 1099 .has_lcd_clk_src = false, 1100 }; 1101 1102 static const struct dss_features omap3630_dss_feats = { 1103 .model = DSS_MODEL_OMAP3, 1104 .fck_div_max = 32, 1105 .fck_freq_max = 173000000, 1106 .dss_fck_multiplier = 1, 1107 .parent_clk_name = "dpll4_ck", 1108 .ports = omap2plus_ports, 1109 .num_ports = ARRAY_SIZE(omap2plus_ports), 1110 .outputs = omap3630_dss_supported_outputs, 1111 .ops = &dss_ops_omap2_omap3, 1112 .dispc_clk_switch = { 0, 0 }, 1113 .has_lcd_clk_src = false, 1114 }; 1115 1116 static const struct dss_features omap44xx_dss_feats = { 1117 .model = DSS_MODEL_OMAP4, 1118 .fck_div_max = 32, 1119 .fck_freq_max = 186000000, 1120 .dss_fck_multiplier = 1, 1121 .parent_clk_name = "dpll_per_x2_ck", 1122 .ports = omap2plus_ports, 1123 .num_ports = ARRAY_SIZE(omap2plus_ports), 1124 .outputs = omap4_dss_supported_outputs, 1125 .ops = &dss_ops_omap4, 1126 .dispc_clk_switch = { 9, 8 }, 1127 .has_lcd_clk_src = true, 1128 }; 1129 1130 static const struct dss_features omap54xx_dss_feats = { 1131 .model = DSS_MODEL_OMAP5, 1132 .fck_div_max = 64, 1133 .fck_freq_max = 209250000, 1134 .dss_fck_multiplier = 1, 1135 .parent_clk_name = "dpll_per_x2_ck", 1136 .ports = omap2plus_ports, 1137 .num_ports = ARRAY_SIZE(omap2plus_ports), 1138 .outputs = omap5_dss_supported_outputs, 1139 .ops = &dss_ops_omap5, 1140 .dispc_clk_switch = { 9, 7 }, 1141 .has_lcd_clk_src = true, 1142 }; 1143 1144 static const struct dss_features am43xx_dss_feats = { 1145 .model = DSS_MODEL_OMAP3, 1146 .fck_div_max = 0, 1147 .fck_freq_max = 200000000, 1148 .dss_fck_multiplier = 0, 1149 .parent_clk_name = NULL, 1150 .ports = omap2plus_ports, 1151 .num_ports = ARRAY_SIZE(omap2plus_ports), 1152 .outputs = am43xx_dss_supported_outputs, 1153 .ops = &dss_ops_omap2_omap3, 1154 .dispc_clk_switch = { 0, 0 }, 1155 .has_lcd_clk_src = true, 1156 }; 1157 1158 static const struct dss_features dra7xx_dss_feats = { 1159 .model = DSS_MODEL_DRA7, 1160 .fck_div_max = 64, 1161 .fck_freq_max = 209250000, 1162 .dss_fck_multiplier = 1, 1163 .parent_clk_name = "dpll_per_x2_ck", 1164 .ports = dra7xx_ports, 1165 .num_ports = ARRAY_SIZE(dra7xx_ports), 1166 .outputs = omap5_dss_supported_outputs, 1167 .ops = &dss_ops_dra7, 1168 .dispc_clk_switch = { 9, 7 }, 1169 .has_lcd_clk_src = true, 1170 }; 1171 1172 static int dss_init_ports(struct platform_device *pdev) 1173 { 1174 struct device_node *parent = pdev->dev.of_node; 1175 struct device_node *port; 1176 int i; 1177 1178 for (i = 0; i < dss.feat->num_ports; i++) { 1179 port = of_graph_get_port_by_id(parent, i); 1180 if (!port) 1181 continue; 1182 1183 switch (dss.feat->ports[i]) { 1184 case OMAP_DISPLAY_TYPE_DPI: 1185 dpi_init_port(pdev, port, dss.feat->model); 1186 break; 1187 case OMAP_DISPLAY_TYPE_SDI: 1188 sdi_init_port(pdev, port); 1189 break; 1190 default: 1191 break; 1192 } 1193 } 1194 1195 return 0; 1196 } 1197 1198 static void dss_uninit_ports(struct platform_device *pdev) 1199 { 1200 struct device_node *parent = pdev->dev.of_node; 1201 struct device_node *port; 1202 int i; 1203 1204 for (i = 0; i < dss.feat->num_ports; i++) { 1205 port = of_graph_get_port_by_id(parent, i); 1206 if (!port) 1207 continue; 1208 1209 switch (dss.feat->ports[i]) { 1210 case OMAP_DISPLAY_TYPE_DPI: 1211 dpi_uninit_port(port); 1212 break; 1213 case OMAP_DISPLAY_TYPE_SDI: 1214 sdi_uninit_port(port); 1215 break; 1216 default: 1217 break; 1218 } 1219 } 1220 } 1221 1222 static int dss_video_pll_probe(struct platform_device *pdev) 1223 { 1224 struct device_node *np = pdev->dev.of_node; 1225 struct regulator *pll_regulator; 1226 int r; 1227 1228 if (!np) 1229 return 0; 1230 1231 if (of_property_read_bool(np, "syscon-pll-ctrl")) { 1232 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, 1233 "syscon-pll-ctrl"); 1234 if (IS_ERR(dss.syscon_pll_ctrl)) { 1235 dev_err(&pdev->dev, 1236 "failed to get syscon-pll-ctrl regmap\n"); 1237 return PTR_ERR(dss.syscon_pll_ctrl); 1238 } 1239 1240 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, 1241 &dss.syscon_pll_ctrl_offset)) { 1242 dev_err(&pdev->dev, 1243 "failed to get syscon-pll-ctrl offset\n"); 1244 return -EINVAL; 1245 } 1246 } 1247 1248 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); 1249 if (IS_ERR(pll_regulator)) { 1250 r = PTR_ERR(pll_regulator); 1251 1252 switch (r) { 1253 case -ENOENT: 1254 pll_regulator = NULL; 1255 break; 1256 1257 case -EPROBE_DEFER: 1258 return -EPROBE_DEFER; 1259 1260 default: 1261 DSSERR("can't get DPLL VDDA regulator\n"); 1262 return r; 1263 } 1264 } 1265 1266 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { 1267 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); 1268 if (IS_ERR(dss.video1_pll)) 1269 return PTR_ERR(dss.video1_pll); 1270 } 1271 1272 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { 1273 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); 1274 if (IS_ERR(dss.video2_pll)) { 1275 dss_video_pll_uninit(dss.video1_pll); 1276 return PTR_ERR(dss.video2_pll); 1277 } 1278 } 1279 1280 return 0; 1281 } 1282 1283 /* DSS HW IP initialisation */ 1284 static const struct of_device_id dss_of_match[] = { 1285 { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats }, 1286 { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats }, 1287 { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats }, 1288 { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats }, 1289 { .compatible = "ti,dra7-dss", .data = &dra7xx_dss_feats }, 1290 {}, 1291 }; 1292 MODULE_DEVICE_TABLE(of, dss_of_match); 1293 1294 static const struct soc_device_attribute dss_soc_devices[] = { 1295 { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats }, 1296 { .machine = "AM35??", .data = &omap34xx_dss_feats }, 1297 { .family = "AM43xx", .data = &am43xx_dss_feats }, 1298 { /* sentinel */ } 1299 }; 1300 1301 static int dss_bind(struct device *dev) 1302 { 1303 struct platform_device *pdev = to_platform_device(dev); 1304 struct resource *dss_mem; 1305 u32 rev; 1306 int r; 1307 1308 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); 1309 dss.base = devm_ioremap_resource(&pdev->dev, dss_mem); 1310 if (IS_ERR(dss.base)) 1311 return PTR_ERR(dss.base); 1312 1313 r = dss_get_clocks(); 1314 if (r) 1315 return r; 1316 1317 r = dss_setup_default_clock(); 1318 if (r) 1319 goto err_setup_clocks; 1320 1321 r = dss_video_pll_probe(pdev); 1322 if (r) 1323 goto err_pll_init; 1324 1325 r = dss_init_ports(pdev); 1326 if (r) 1327 goto err_init_ports; 1328 1329 pm_runtime_enable(&pdev->dev); 1330 1331 r = dss_runtime_get(); 1332 if (r) 1333 goto err_runtime_get; 1334 1335 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 1336 1337 /* Select DPLL */ 1338 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); 1339 1340 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); 1341 1342 #ifdef CONFIG_OMAP2_DSS_VENC 1343 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 1344 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 1345 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 1346 #endif 1347 dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; 1348 dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; 1349 dss.dispc_clk_source = DSS_CLK_SRC_FCK; 1350 dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; 1351 dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; 1352 1353 rev = dss_read_reg(DSS_REVISION); 1354 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 1355 1356 dss_runtime_put(); 1357 1358 r = component_bind_all(&pdev->dev, NULL); 1359 if (r) 1360 goto err_component; 1361 1362 dss_debugfs_create_file("dss", dss_dump_regs); 1363 1364 pm_set_vt_switch(0); 1365 1366 omapdss_gather_components(dev); 1367 omapdss_set_is_initialized(true); 1368 1369 return 0; 1370 1371 err_component: 1372 err_runtime_get: 1373 pm_runtime_disable(&pdev->dev); 1374 dss_uninit_ports(pdev); 1375 err_init_ports: 1376 if (dss.video1_pll) 1377 dss_video_pll_uninit(dss.video1_pll); 1378 1379 if (dss.video2_pll) 1380 dss_video_pll_uninit(dss.video2_pll); 1381 err_pll_init: 1382 err_setup_clocks: 1383 dss_put_clocks(); 1384 return r; 1385 } 1386 1387 static void dss_unbind(struct device *dev) 1388 { 1389 struct platform_device *pdev = to_platform_device(dev); 1390 1391 omapdss_set_is_initialized(false); 1392 1393 component_unbind_all(&pdev->dev, NULL); 1394 1395 if (dss.video1_pll) 1396 dss_video_pll_uninit(dss.video1_pll); 1397 1398 if (dss.video2_pll) 1399 dss_video_pll_uninit(dss.video2_pll); 1400 1401 dss_uninit_ports(pdev); 1402 1403 pm_runtime_disable(&pdev->dev); 1404 1405 dss_put_clocks(); 1406 } 1407 1408 static const struct component_master_ops dss_component_ops = { 1409 .bind = dss_bind, 1410 .unbind = dss_unbind, 1411 }; 1412 1413 static int dss_component_compare(struct device *dev, void *data) 1414 { 1415 struct device *child = data; 1416 return dev == child; 1417 } 1418 1419 static int dss_add_child_component(struct device *dev, void *data) 1420 { 1421 struct component_match **match = data; 1422 1423 /* 1424 * HACK 1425 * We don't have a working driver for rfbi, so skip it here always. 1426 * Otherwise dss will never get probed successfully, as it will wait 1427 * for rfbi to get probed. 1428 */ 1429 if (strstr(dev_name(dev), "rfbi")) 1430 return 0; 1431 1432 component_match_add(dev->parent, match, dss_component_compare, dev); 1433 1434 return 0; 1435 } 1436 1437 static int dss_probe(struct platform_device *pdev) 1438 { 1439 const struct soc_device_attribute *soc; 1440 struct component_match *match = NULL; 1441 int r; 1442 1443 dss.pdev = pdev; 1444 1445 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1446 if (r) { 1447 dev_err(&pdev->dev, "Failed to set the DMA mask\n"); 1448 return r; 1449 } 1450 1451 /* 1452 * The various OMAP3-based SoCs can't be told apart using the compatible 1453 * string, use SoC device matching. 1454 */ 1455 soc = soc_device_match(dss_soc_devices); 1456 if (soc) 1457 dss.feat = soc->data; 1458 else 1459 dss.feat = of_match_device(dss_of_match, &pdev->dev)->data; 1460 1461 r = dss_initialize_debugfs(); 1462 if (r) 1463 return r; 1464 1465 /* add all the child devices as components */ 1466 device_for_each_child(&pdev->dev, &match, dss_add_child_component); 1467 1468 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); 1469 if (r) { 1470 dss_uninitialize_debugfs(); 1471 return r; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int dss_remove(struct platform_device *pdev) 1478 { 1479 component_master_del(&pdev->dev, &dss_component_ops); 1480 1481 dss_uninitialize_debugfs(); 1482 1483 return 0; 1484 } 1485 1486 static void dss_shutdown(struct platform_device *pdev) 1487 { 1488 struct omap_dss_device *dssdev = NULL; 1489 1490 DSSDBG("shutdown\n"); 1491 1492 for_each_dss_dev(dssdev) { 1493 if (!dssdev->driver) 1494 continue; 1495 1496 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) 1497 dssdev->driver->disable(dssdev); 1498 } 1499 } 1500 1501 static int dss_runtime_suspend(struct device *dev) 1502 { 1503 dss_save_context(); 1504 dss_set_min_bus_tput(dev, 0); 1505 1506 pinctrl_pm_select_sleep_state(dev); 1507 1508 return 0; 1509 } 1510 1511 static int dss_runtime_resume(struct device *dev) 1512 { 1513 int r; 1514 1515 pinctrl_pm_select_default_state(dev); 1516 1517 /* 1518 * Set an arbitrarily high tput request to ensure OPP100. 1519 * What we should really do is to make a request to stay in OPP100, 1520 * without any tput requirements, but that is not currently possible 1521 * via the PM layer. 1522 */ 1523 1524 r = dss_set_min_bus_tput(dev, 1000000000); 1525 if (r) 1526 return r; 1527 1528 dss_restore_context(); 1529 return 0; 1530 } 1531 1532 static const struct dev_pm_ops dss_pm_ops = { 1533 .runtime_suspend = dss_runtime_suspend, 1534 .runtime_resume = dss_runtime_resume, 1535 }; 1536 1537 struct platform_driver omap_dsshw_driver = { 1538 .probe = dss_probe, 1539 .remove = dss_remove, 1540 .shutdown = dss_shutdown, 1541 .driver = { 1542 .name = "omapdss_dss", 1543 .pm = &dss_pm_ops, 1544 .of_match_table = dss_of_match, 1545 .suppress_bind_attrs = true, 1546 }, 1547 }; 1548