1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "DSS" 22 23 #include <linux/debugfs.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/io.h> 28 #include <linux/export.h> 29 #include <linux/err.h> 30 #include <linux/delay.h> 31 #include <linux/seq_file.h> 32 #include <linux/clk.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/gfp.h> 37 #include <linux/sizes.h> 38 #include <linux/mfd/syscon.h> 39 #include <linux/regmap.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/of_graph.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/suspend.h> 45 #include <linux/component.h> 46 #include <linux/sys_soc.h> 47 48 #include "omapdss.h" 49 #include "dss.h" 50 51 struct dss_reg { 52 u16 idx; 53 }; 54 55 #define DSS_REG(idx) ((const struct dss_reg) { idx }) 56 57 #define DSS_REVISION DSS_REG(0x0000) 58 #define DSS_SYSCONFIG DSS_REG(0x0010) 59 #define DSS_SYSSTATUS DSS_REG(0x0014) 60 #define DSS_CONTROL DSS_REG(0x0040) 61 #define DSS_SDI_CONTROL DSS_REG(0x0044) 62 #define DSS_PLL_CONTROL DSS_REG(0x0048) 63 #define DSS_SDI_STATUS DSS_REG(0x005C) 64 65 #define REG_GET(dss, idx, start, end) \ 66 FLD_GET(dss_read_reg(dss, idx), start, end) 67 68 #define REG_FLD_MOD(dss, idx, val, start, end) \ 69 dss_write_reg(dss, idx, \ 70 FLD_MOD(dss_read_reg(dss, idx), val, start, end)) 71 72 struct dss_ops { 73 int (*dpi_select_source)(struct dss_device *dss, int port, 74 enum omap_channel channel); 75 int (*select_lcd_source)(struct dss_device *dss, 76 enum omap_channel channel, 77 enum dss_clk_source clk_src); 78 }; 79 80 struct dss_features { 81 enum dss_model model; 82 u8 fck_div_max; 83 unsigned int fck_freq_max; 84 u8 dss_fck_multiplier; 85 const char *parent_clk_name; 86 const enum omap_display_type *ports; 87 int num_ports; 88 const enum omap_dss_output_id *outputs; 89 const struct dss_ops *ops; 90 struct dss_reg_field dispc_clk_switch; 91 bool has_lcd_clk_src; 92 }; 93 94 static const char * const dss_generic_clk_source_names[] = { 95 [DSS_CLK_SRC_FCK] = "FCK", 96 [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 97 [DSS_CLK_SRC_PLL1_2] = "PLL1:2", 98 [DSS_CLK_SRC_PLL1_3] = "PLL1:3", 99 [DSS_CLK_SRC_PLL2_1] = "PLL2:1", 100 [DSS_CLK_SRC_PLL2_2] = "PLL2:2", 101 [DSS_CLK_SRC_PLL2_3] = "PLL2:3", 102 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 103 }; 104 105 static inline void dss_write_reg(struct dss_device *dss, 106 const struct dss_reg idx, u32 val) 107 { 108 __raw_writel(val, dss->base + idx.idx); 109 } 110 111 static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx) 112 { 113 return __raw_readl(dss->base + idx.idx); 114 } 115 116 #define SR(dss, reg) \ 117 dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg) 118 #define RR(dss, reg) \ 119 dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)]) 120 121 static void dss_save_context(struct dss_device *dss) 122 { 123 DSSDBG("dss_save_context\n"); 124 125 SR(dss, CONTROL); 126 127 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 128 SR(dss, SDI_CONTROL); 129 SR(dss, PLL_CONTROL); 130 } 131 132 dss->ctx_valid = true; 133 134 DSSDBG("context saved\n"); 135 } 136 137 static void dss_restore_context(struct dss_device *dss) 138 { 139 DSSDBG("dss_restore_context\n"); 140 141 if (!dss->ctx_valid) 142 return; 143 144 RR(dss, CONTROL); 145 146 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 147 RR(dss, SDI_CONTROL); 148 RR(dss, PLL_CONTROL); 149 } 150 151 DSSDBG("context restored\n"); 152 } 153 154 #undef SR 155 #undef RR 156 157 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable) 158 { 159 unsigned int shift; 160 unsigned int val; 161 162 if (!pll->dss->syscon_pll_ctrl) 163 return; 164 165 val = !enable; 166 167 switch (pll->id) { 168 case DSS_PLL_VIDEO1: 169 shift = 0; 170 break; 171 case DSS_PLL_VIDEO2: 172 shift = 1; 173 break; 174 case DSS_PLL_HDMI: 175 shift = 2; 176 break; 177 default: 178 DSSERR("illegal DSS PLL ID %d\n", pll->id); 179 return; 180 } 181 182 regmap_update_bits(pll->dss->syscon_pll_ctrl, 183 pll->dss->syscon_pll_ctrl_offset, 184 1 << shift, val << shift); 185 } 186 187 static int dss_ctrl_pll_set_control_mux(struct dss_device *dss, 188 enum dss_clk_source clk_src, 189 enum omap_channel channel) 190 { 191 unsigned int shift, val; 192 193 if (!dss->syscon_pll_ctrl) 194 return -EINVAL; 195 196 switch (channel) { 197 case OMAP_DSS_CHANNEL_LCD: 198 shift = 3; 199 200 switch (clk_src) { 201 case DSS_CLK_SRC_PLL1_1: 202 val = 0; break; 203 case DSS_CLK_SRC_HDMI_PLL: 204 val = 1; break; 205 default: 206 DSSERR("error in PLL mux config for LCD\n"); 207 return -EINVAL; 208 } 209 210 break; 211 case OMAP_DSS_CHANNEL_LCD2: 212 shift = 5; 213 214 switch (clk_src) { 215 case DSS_CLK_SRC_PLL1_3: 216 val = 0; break; 217 case DSS_CLK_SRC_PLL2_3: 218 val = 1; break; 219 case DSS_CLK_SRC_HDMI_PLL: 220 val = 2; break; 221 default: 222 DSSERR("error in PLL mux config for LCD2\n"); 223 return -EINVAL; 224 } 225 226 break; 227 case OMAP_DSS_CHANNEL_LCD3: 228 shift = 7; 229 230 switch (clk_src) { 231 case DSS_CLK_SRC_PLL2_1: 232 val = 0; break; 233 case DSS_CLK_SRC_PLL1_3: 234 val = 1; break; 235 case DSS_CLK_SRC_HDMI_PLL: 236 val = 2; break; 237 default: 238 DSSERR("error in PLL mux config for LCD3\n"); 239 return -EINVAL; 240 } 241 242 break; 243 default: 244 DSSERR("error in PLL mux config\n"); 245 return -EINVAL; 246 } 247 248 regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset, 249 0x3 << shift, val << shift); 250 251 return 0; 252 } 253 254 void dss_sdi_init(struct dss_device *dss, int datapairs) 255 { 256 u32 l; 257 258 BUG_ON(datapairs > 3 || datapairs < 1); 259 260 l = dss_read_reg(dss, DSS_SDI_CONTROL); 261 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 262 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 263 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 264 dss_write_reg(dss, DSS_SDI_CONTROL, l); 265 266 l = dss_read_reg(dss, DSS_PLL_CONTROL); 267 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 268 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 269 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 270 dss_write_reg(dss, DSS_PLL_CONTROL, l); 271 } 272 273 int dss_sdi_enable(struct dss_device *dss) 274 { 275 unsigned long timeout; 276 277 dispc_pck_free_enable(dss->dispc, 1); 278 279 /* Reset SDI PLL */ 280 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 281 udelay(1); /* wait 2x PCLK */ 282 283 /* Lock SDI PLL */ 284 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 285 286 /* Waiting for PLL lock request to complete */ 287 timeout = jiffies + msecs_to_jiffies(500); 288 while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) { 289 if (time_after_eq(jiffies, timeout)) { 290 DSSERR("PLL lock request timed out\n"); 291 goto err1; 292 } 293 } 294 295 /* Clearing PLL_GO bit */ 296 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); 297 298 /* Waiting for PLL to lock */ 299 timeout = jiffies + msecs_to_jiffies(500); 300 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) { 301 if (time_after_eq(jiffies, timeout)) { 302 DSSERR("PLL lock timed out\n"); 303 goto err1; 304 } 305 } 306 307 dispc_lcd_enable_signal(dss->dispc, 1); 308 309 /* Waiting for SDI reset to complete */ 310 timeout = jiffies + msecs_to_jiffies(500); 311 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) { 312 if (time_after_eq(jiffies, timeout)) { 313 DSSERR("SDI reset timed out\n"); 314 goto err2; 315 } 316 } 317 318 return 0; 319 320 err2: 321 dispc_lcd_enable_signal(dss->dispc, 0); 322 err1: 323 /* Reset SDI PLL */ 324 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 325 326 dispc_pck_free_enable(dss->dispc, 0); 327 328 return -ETIMEDOUT; 329 } 330 331 void dss_sdi_disable(struct dss_device *dss) 332 { 333 dispc_lcd_enable_signal(dss->dispc, 0); 334 335 dispc_pck_free_enable(dss->dispc, 0); 336 337 /* Reset SDI PLL */ 338 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 339 } 340 341 const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 342 { 343 return dss_generic_clk_source_names[clk_src]; 344 } 345 346 static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s) 347 { 348 const char *fclk_name; 349 unsigned long fclk_rate; 350 351 if (dss_runtime_get(dss)) 352 return; 353 354 seq_printf(s, "- DSS -\n"); 355 356 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 357 fclk_rate = clk_get_rate(dss->dss_clk); 358 359 seq_printf(s, "%s = %lu\n", 360 fclk_name, 361 fclk_rate); 362 363 dss_runtime_put(dss); 364 } 365 366 static int dss_dump_regs(struct seq_file *s, void *p) 367 { 368 struct dss_device *dss = s->private; 369 370 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r)) 371 372 if (dss_runtime_get(dss)) 373 return 0; 374 375 DUMPREG(dss, DSS_REVISION); 376 DUMPREG(dss, DSS_SYSCONFIG); 377 DUMPREG(dss, DSS_SYSSTATUS); 378 DUMPREG(dss, DSS_CONTROL); 379 380 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 381 DUMPREG(dss, DSS_SDI_CONTROL); 382 DUMPREG(dss, DSS_PLL_CONTROL); 383 DUMPREG(dss, DSS_SDI_STATUS); 384 } 385 386 dss_runtime_put(dss); 387 #undef DUMPREG 388 return 0; 389 } 390 391 static int dss_debug_dump_clocks(struct seq_file *s, void *p) 392 { 393 struct dss_device *dss = s->private; 394 395 dss_dump_clocks(dss, s); 396 dispc_dump_clocks(dss->dispc, s); 397 #ifdef CONFIG_OMAP2_DSS_DSI 398 dsi_dump_clocks(s); 399 #endif 400 return 0; 401 } 402 403 static int dss_get_channel_index(enum omap_channel channel) 404 { 405 switch (channel) { 406 case OMAP_DSS_CHANNEL_LCD: 407 return 0; 408 case OMAP_DSS_CHANNEL_LCD2: 409 return 1; 410 case OMAP_DSS_CHANNEL_LCD3: 411 return 2; 412 default: 413 WARN_ON(1); 414 return 0; 415 } 416 } 417 418 static void dss_select_dispc_clk_source(struct dss_device *dss, 419 enum dss_clk_source clk_src) 420 { 421 int b; 422 423 /* 424 * We always use PRCM clock as the DISPC func clock, except on DSS3, 425 * where we don't have separate DISPC and LCD clock sources. 426 */ 427 if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) 428 return; 429 430 switch (clk_src) { 431 case DSS_CLK_SRC_FCK: 432 b = 0; 433 break; 434 case DSS_CLK_SRC_PLL1_1: 435 b = 1; 436 break; 437 case DSS_CLK_SRC_PLL2_1: 438 b = 2; 439 break; 440 default: 441 BUG(); 442 return; 443 } 444 445 REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ 446 dss->feat->dispc_clk_switch.start, 447 dss->feat->dispc_clk_switch.end); 448 449 dss->dispc_clk_source = clk_src; 450 } 451 452 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module, 453 enum dss_clk_source clk_src) 454 { 455 int b, pos; 456 457 switch (clk_src) { 458 case DSS_CLK_SRC_FCK: 459 b = 0; 460 break; 461 case DSS_CLK_SRC_PLL1_2: 462 BUG_ON(dsi_module != 0); 463 b = 1; 464 break; 465 case DSS_CLK_SRC_PLL2_2: 466 BUG_ON(dsi_module != 1); 467 b = 1; 468 break; 469 default: 470 BUG(); 471 return; 472 } 473 474 pos = dsi_module == 0 ? 1 : 10; 475 REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 476 477 dss->dsi_clk_source[dsi_module] = clk_src; 478 } 479 480 static int dss_lcd_clk_mux_dra7(struct dss_device *dss, 481 enum omap_channel channel, 482 enum dss_clk_source clk_src) 483 { 484 const u8 ctrl_bits[] = { 485 [OMAP_DSS_CHANNEL_LCD] = 0, 486 [OMAP_DSS_CHANNEL_LCD2] = 12, 487 [OMAP_DSS_CHANNEL_LCD3] = 19, 488 }; 489 490 u8 ctrl_bit = ctrl_bits[channel]; 491 int r; 492 493 if (clk_src == DSS_CLK_SRC_FCK) { 494 /* LCDx_CLK_SWITCH */ 495 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 496 return -EINVAL; 497 } 498 499 r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel); 500 if (r) 501 return r; 502 503 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 504 505 return 0; 506 } 507 508 static int dss_lcd_clk_mux_omap5(struct dss_device *dss, 509 enum omap_channel channel, 510 enum dss_clk_source clk_src) 511 { 512 const u8 ctrl_bits[] = { 513 [OMAP_DSS_CHANNEL_LCD] = 0, 514 [OMAP_DSS_CHANNEL_LCD2] = 12, 515 [OMAP_DSS_CHANNEL_LCD3] = 19, 516 }; 517 const enum dss_clk_source allowed_plls[] = { 518 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 519 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, 520 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, 521 }; 522 523 u8 ctrl_bit = ctrl_bits[channel]; 524 525 if (clk_src == DSS_CLK_SRC_FCK) { 526 /* LCDx_CLK_SWITCH */ 527 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 528 return -EINVAL; 529 } 530 531 if (WARN_ON(allowed_plls[channel] != clk_src)) 532 return -EINVAL; 533 534 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 535 536 return 0; 537 } 538 539 static int dss_lcd_clk_mux_omap4(struct dss_device *dss, 540 enum omap_channel channel, 541 enum dss_clk_source clk_src) 542 { 543 const u8 ctrl_bits[] = { 544 [OMAP_DSS_CHANNEL_LCD] = 0, 545 [OMAP_DSS_CHANNEL_LCD2] = 12, 546 }; 547 const enum dss_clk_source allowed_plls[] = { 548 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 549 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, 550 }; 551 552 u8 ctrl_bit = ctrl_bits[channel]; 553 554 if (clk_src == DSS_CLK_SRC_FCK) { 555 /* LCDx_CLK_SWITCH */ 556 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 557 return 0; 558 } 559 560 if (WARN_ON(allowed_plls[channel] != clk_src)) 561 return -EINVAL; 562 563 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 564 565 return 0; 566 } 567 568 void dss_select_lcd_clk_source(struct dss_device *dss, 569 enum omap_channel channel, 570 enum dss_clk_source clk_src) 571 { 572 int idx = dss_get_channel_index(channel); 573 int r; 574 575 if (!dss->feat->has_lcd_clk_src) { 576 dss_select_dispc_clk_source(dss, clk_src); 577 dss->lcd_clk_source[idx] = clk_src; 578 return; 579 } 580 581 r = dss->feat->ops->select_lcd_source(dss, channel, clk_src); 582 if (r) 583 return; 584 585 dss->lcd_clk_source[idx] = clk_src; 586 } 587 588 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss) 589 { 590 return dss->dispc_clk_source; 591 } 592 593 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss, 594 int dsi_module) 595 { 596 return dss->dsi_clk_source[dsi_module]; 597 } 598 599 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss, 600 enum omap_channel channel) 601 { 602 if (dss->feat->has_lcd_clk_src) { 603 int idx = dss_get_channel_index(channel); 604 return dss->lcd_clk_source[idx]; 605 } else { 606 /* LCD_CLK source is the same as DISPC_FCLK source for 607 * OMAP2 and OMAP3 */ 608 return dss->dispc_clk_source; 609 } 610 } 611 612 bool dss_div_calc(struct dss_device *dss, unsigned long pck, 613 unsigned long fck_min, dss_div_calc_func func, void *data) 614 { 615 int fckd, fckd_start, fckd_stop; 616 unsigned long fck; 617 unsigned long fck_hw_max; 618 unsigned long fckd_hw_max; 619 unsigned long prate; 620 unsigned int m; 621 622 fck_hw_max = dss->feat->fck_freq_max; 623 624 if (dss->parent_clk == NULL) { 625 unsigned int pckd; 626 627 pckd = fck_hw_max / pck; 628 629 fck = pck * pckd; 630 631 fck = clk_round_rate(dss->dss_clk, fck); 632 633 return func(fck, data); 634 } 635 636 fckd_hw_max = dss->feat->fck_div_max; 637 638 m = dss->feat->dss_fck_multiplier; 639 prate = clk_get_rate(dss->parent_clk); 640 641 fck_min = fck_min ? fck_min : 1; 642 643 fckd_start = min(prate * m / fck_min, fckd_hw_max); 644 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); 645 646 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { 647 fck = DIV_ROUND_UP(prate, fckd) * m; 648 649 if (func(fck, data)) 650 return true; 651 } 652 653 return false; 654 } 655 656 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate) 657 { 658 int r; 659 660 DSSDBG("set fck to %lu\n", rate); 661 662 r = clk_set_rate(dss->dss_clk, rate); 663 if (r) 664 return r; 665 666 dss->dss_clk_rate = clk_get_rate(dss->dss_clk); 667 668 WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu", 669 dss->dss_clk_rate, rate); 670 671 return 0; 672 } 673 674 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss) 675 { 676 return dss->dss_clk_rate; 677 } 678 679 unsigned long dss_get_max_fck_rate(struct dss_device *dss) 680 { 681 return dss->feat->fck_freq_max; 682 } 683 684 enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss, 685 enum omap_channel channel) 686 { 687 return dss->feat->outputs[channel]; 688 } 689 690 static int dss_setup_default_clock(struct dss_device *dss) 691 { 692 unsigned long max_dss_fck, prate; 693 unsigned long fck; 694 unsigned int fck_div; 695 int r; 696 697 max_dss_fck = dss->feat->fck_freq_max; 698 699 if (dss->parent_clk == NULL) { 700 fck = clk_round_rate(dss->dss_clk, max_dss_fck); 701 } else { 702 prate = clk_get_rate(dss->parent_clk); 703 704 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier, 705 max_dss_fck); 706 fck = DIV_ROUND_UP(prate, fck_div) 707 * dss->feat->dss_fck_multiplier; 708 } 709 710 r = dss_set_fck_rate(dss, fck); 711 if (r) 712 return r; 713 714 return 0; 715 } 716 717 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type) 718 { 719 int l = 0; 720 721 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) 722 l = 0; 723 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) 724 l = 1; 725 else 726 BUG(); 727 728 /* venc out selection. 0 = comp, 1 = svideo */ 729 REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6); 730 } 731 732 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable) 733 { 734 /* DAC Power-Down Control */ 735 REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5); 736 } 737 738 void dss_select_hdmi_venc_clk_source(struct dss_device *dss, 739 enum dss_hdmi_venc_clk_source_select src) 740 { 741 enum omap_dss_output_id outputs; 742 743 outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; 744 745 /* Complain about invalid selections */ 746 WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC)); 747 WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI)); 748 749 /* Select only if we have options */ 750 if ((outputs & OMAP_DSS_OUTPUT_VENC) && 751 (outputs & OMAP_DSS_OUTPUT_HDMI)) 752 /* VENC_HDMI_SWITCH */ 753 REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15); 754 } 755 756 static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port, 757 enum omap_channel channel) 758 { 759 if (channel != OMAP_DSS_CHANNEL_LCD) 760 return -EINVAL; 761 762 return 0; 763 } 764 765 static int dss_dpi_select_source_omap4(struct dss_device *dss, int port, 766 enum omap_channel channel) 767 { 768 int val; 769 770 switch (channel) { 771 case OMAP_DSS_CHANNEL_LCD2: 772 val = 0; 773 break; 774 case OMAP_DSS_CHANNEL_DIGIT: 775 val = 1; 776 break; 777 default: 778 return -EINVAL; 779 } 780 781 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17); 782 783 return 0; 784 } 785 786 static int dss_dpi_select_source_omap5(struct dss_device *dss, int port, 787 enum omap_channel channel) 788 { 789 int val; 790 791 switch (channel) { 792 case OMAP_DSS_CHANNEL_LCD: 793 val = 1; 794 break; 795 case OMAP_DSS_CHANNEL_LCD2: 796 val = 2; 797 break; 798 case OMAP_DSS_CHANNEL_LCD3: 799 val = 3; 800 break; 801 case OMAP_DSS_CHANNEL_DIGIT: 802 val = 0; 803 break; 804 default: 805 return -EINVAL; 806 } 807 808 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16); 809 810 return 0; 811 } 812 813 static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port, 814 enum omap_channel channel) 815 { 816 switch (port) { 817 case 0: 818 return dss_dpi_select_source_omap5(dss, port, channel); 819 case 1: 820 if (channel != OMAP_DSS_CHANNEL_LCD2) 821 return -EINVAL; 822 break; 823 case 2: 824 if (channel != OMAP_DSS_CHANNEL_LCD3) 825 return -EINVAL; 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 return 0; 832 } 833 834 int dss_dpi_select_source(struct dss_device *dss, int port, 835 enum omap_channel channel) 836 { 837 return dss->feat->ops->dpi_select_source(dss, port, channel); 838 } 839 840 static int dss_get_clocks(struct dss_device *dss) 841 { 842 struct clk *clk; 843 844 clk = devm_clk_get(&dss->pdev->dev, "fck"); 845 if (IS_ERR(clk)) { 846 DSSERR("can't get clock fck\n"); 847 return PTR_ERR(clk); 848 } 849 850 dss->dss_clk = clk; 851 852 if (dss->feat->parent_clk_name) { 853 clk = clk_get(NULL, dss->feat->parent_clk_name); 854 if (IS_ERR(clk)) { 855 DSSERR("Failed to get %s\n", 856 dss->feat->parent_clk_name); 857 return PTR_ERR(clk); 858 } 859 } else { 860 clk = NULL; 861 } 862 863 dss->parent_clk = clk; 864 865 return 0; 866 } 867 868 static void dss_put_clocks(struct dss_device *dss) 869 { 870 if (dss->parent_clk) 871 clk_put(dss->parent_clk); 872 } 873 874 int dss_runtime_get(struct dss_device *dss) 875 { 876 int r; 877 878 DSSDBG("dss_runtime_get\n"); 879 880 r = pm_runtime_get_sync(&dss->pdev->dev); 881 WARN_ON(r < 0); 882 return r < 0 ? r : 0; 883 } 884 885 void dss_runtime_put(struct dss_device *dss) 886 { 887 int r; 888 889 DSSDBG("dss_runtime_put\n"); 890 891 r = pm_runtime_put_sync(&dss->pdev->dev); 892 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); 893 } 894 895 struct dss_device *dss_get_device(struct device *dev) 896 { 897 return dev_get_drvdata(dev); 898 } 899 900 /* DEBUGFS */ 901 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 902 static int dss_initialize_debugfs(struct dss_device *dss) 903 { 904 struct dentry *dir; 905 906 dir = debugfs_create_dir("omapdss", NULL); 907 if (IS_ERR(dir)) 908 return PTR_ERR(dir); 909 910 dss->debugfs.root = dir; 911 912 return 0; 913 } 914 915 static void dss_uninitialize_debugfs(struct dss_device *dss) 916 { 917 debugfs_remove_recursive(dss->debugfs.root); 918 } 919 920 struct dss_debugfs_entry { 921 struct dentry *dentry; 922 int (*show_fn)(struct seq_file *s, void *data); 923 void *data; 924 }; 925 926 static int dss_debug_open(struct inode *inode, struct file *file) 927 { 928 struct dss_debugfs_entry *entry = inode->i_private; 929 930 return single_open(file, entry->show_fn, entry->data); 931 } 932 933 static const struct file_operations dss_debug_fops = { 934 .open = dss_debug_open, 935 .read = seq_read, 936 .llseek = seq_lseek, 937 .release = single_release, 938 }; 939 940 struct dss_debugfs_entry * 941 dss_debugfs_create_file(struct dss_device *dss, const char *name, 942 int (*show_fn)(struct seq_file *s, void *data), 943 void *data) 944 { 945 struct dss_debugfs_entry *entry; 946 struct dentry *d; 947 948 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 949 if (!entry) 950 return ERR_PTR(-ENOMEM); 951 952 entry->show_fn = show_fn; 953 entry->data = data; 954 955 d = debugfs_create_file(name, 0444, dss->debugfs.root, entry, 956 &dss_debug_fops); 957 if (IS_ERR(d)) { 958 kfree(entry); 959 return ERR_PTR(PTR_ERR(d)); 960 } 961 962 entry->dentry = d; 963 return entry; 964 } 965 966 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry) 967 { 968 if (IS_ERR_OR_NULL(entry)) 969 return; 970 971 debugfs_remove(entry->dentry); 972 kfree(entry); 973 } 974 975 #else /* CONFIG_OMAP2_DSS_DEBUGFS */ 976 static inline int dss_initialize_debugfs(struct dss_device *dss) 977 { 978 return 0; 979 } 980 static inline void dss_uninitialize_debugfs(struct dss_device *dss) 981 { 982 } 983 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 984 985 static const struct dss_ops dss_ops_omap2_omap3 = { 986 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 987 }; 988 989 static const struct dss_ops dss_ops_omap4 = { 990 .dpi_select_source = &dss_dpi_select_source_omap4, 991 .select_lcd_source = &dss_lcd_clk_mux_omap4, 992 }; 993 994 static const struct dss_ops dss_ops_omap5 = { 995 .dpi_select_source = &dss_dpi_select_source_omap5, 996 .select_lcd_source = &dss_lcd_clk_mux_omap5, 997 }; 998 999 static const struct dss_ops dss_ops_dra7 = { 1000 .dpi_select_source = &dss_dpi_select_source_dra7xx, 1001 .select_lcd_source = &dss_lcd_clk_mux_dra7, 1002 }; 1003 1004 static const enum omap_display_type omap2plus_ports[] = { 1005 OMAP_DISPLAY_TYPE_DPI, 1006 }; 1007 1008 static const enum omap_display_type omap34xx_ports[] = { 1009 OMAP_DISPLAY_TYPE_DPI, 1010 OMAP_DISPLAY_TYPE_SDI, 1011 }; 1012 1013 static const enum omap_display_type dra7xx_ports[] = { 1014 OMAP_DISPLAY_TYPE_DPI, 1015 OMAP_DISPLAY_TYPE_DPI, 1016 OMAP_DISPLAY_TYPE_DPI, 1017 }; 1018 1019 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { 1020 /* OMAP_DSS_CHANNEL_LCD */ 1021 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, 1022 1023 /* OMAP_DSS_CHANNEL_DIGIT */ 1024 OMAP_DSS_OUTPUT_VENC, 1025 }; 1026 1027 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = { 1028 /* OMAP_DSS_CHANNEL_LCD */ 1029 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1030 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1, 1031 1032 /* OMAP_DSS_CHANNEL_DIGIT */ 1033 OMAP_DSS_OUTPUT_VENC, 1034 }; 1035 1036 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { 1037 /* OMAP_DSS_CHANNEL_LCD */ 1038 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1039 OMAP_DSS_OUTPUT_DSI1, 1040 1041 /* OMAP_DSS_CHANNEL_DIGIT */ 1042 OMAP_DSS_OUTPUT_VENC, 1043 }; 1044 1045 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { 1046 /* OMAP_DSS_CHANNEL_LCD */ 1047 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, 1048 }; 1049 1050 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { 1051 /* OMAP_DSS_CHANNEL_LCD */ 1052 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, 1053 1054 /* OMAP_DSS_CHANNEL_DIGIT */ 1055 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI, 1056 1057 /* OMAP_DSS_CHANNEL_LCD2 */ 1058 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1059 OMAP_DSS_OUTPUT_DSI2, 1060 }; 1061 1062 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { 1063 /* OMAP_DSS_CHANNEL_LCD */ 1064 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1065 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2, 1066 1067 /* OMAP_DSS_CHANNEL_DIGIT */ 1068 OMAP_DSS_OUTPUT_HDMI, 1069 1070 /* OMAP_DSS_CHANNEL_LCD2 */ 1071 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1072 OMAP_DSS_OUTPUT_DSI1, 1073 1074 /* OMAP_DSS_CHANNEL_LCD3 */ 1075 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | 1076 OMAP_DSS_OUTPUT_DSI2, 1077 }; 1078 1079 static const struct dss_features omap24xx_dss_feats = { 1080 .model = DSS_MODEL_OMAP2, 1081 /* 1082 * fck div max is really 16, but the divider range has gaps. The range 1083 * from 1 to 6 has no gaps, so let's use that as a max. 1084 */ 1085 .fck_div_max = 6, 1086 .fck_freq_max = 133000000, 1087 .dss_fck_multiplier = 2, 1088 .parent_clk_name = "core_ck", 1089 .ports = omap2plus_ports, 1090 .num_ports = ARRAY_SIZE(omap2plus_ports), 1091 .outputs = omap2_dss_supported_outputs, 1092 .ops = &dss_ops_omap2_omap3, 1093 .dispc_clk_switch = { 0, 0 }, 1094 .has_lcd_clk_src = false, 1095 }; 1096 1097 static const struct dss_features omap34xx_dss_feats = { 1098 .model = DSS_MODEL_OMAP3, 1099 .fck_div_max = 16, 1100 .fck_freq_max = 173000000, 1101 .dss_fck_multiplier = 2, 1102 .parent_clk_name = "dpll4_ck", 1103 .ports = omap34xx_ports, 1104 .outputs = omap3430_dss_supported_outputs, 1105 .num_ports = ARRAY_SIZE(omap34xx_ports), 1106 .ops = &dss_ops_omap2_omap3, 1107 .dispc_clk_switch = { 0, 0 }, 1108 .has_lcd_clk_src = false, 1109 }; 1110 1111 static const struct dss_features omap3630_dss_feats = { 1112 .model = DSS_MODEL_OMAP3, 1113 .fck_div_max = 32, 1114 .fck_freq_max = 173000000, 1115 .dss_fck_multiplier = 1, 1116 .parent_clk_name = "dpll4_ck", 1117 .ports = omap2plus_ports, 1118 .num_ports = ARRAY_SIZE(omap2plus_ports), 1119 .outputs = omap3630_dss_supported_outputs, 1120 .ops = &dss_ops_omap2_omap3, 1121 .dispc_clk_switch = { 0, 0 }, 1122 .has_lcd_clk_src = false, 1123 }; 1124 1125 static const struct dss_features omap44xx_dss_feats = { 1126 .model = DSS_MODEL_OMAP4, 1127 .fck_div_max = 32, 1128 .fck_freq_max = 186000000, 1129 .dss_fck_multiplier = 1, 1130 .parent_clk_name = "dpll_per_x2_ck", 1131 .ports = omap2plus_ports, 1132 .num_ports = ARRAY_SIZE(omap2plus_ports), 1133 .outputs = omap4_dss_supported_outputs, 1134 .ops = &dss_ops_omap4, 1135 .dispc_clk_switch = { 9, 8 }, 1136 .has_lcd_clk_src = true, 1137 }; 1138 1139 static const struct dss_features omap54xx_dss_feats = { 1140 .model = DSS_MODEL_OMAP5, 1141 .fck_div_max = 64, 1142 .fck_freq_max = 209250000, 1143 .dss_fck_multiplier = 1, 1144 .parent_clk_name = "dpll_per_x2_ck", 1145 .ports = omap2plus_ports, 1146 .num_ports = ARRAY_SIZE(omap2plus_ports), 1147 .outputs = omap5_dss_supported_outputs, 1148 .ops = &dss_ops_omap5, 1149 .dispc_clk_switch = { 9, 7 }, 1150 .has_lcd_clk_src = true, 1151 }; 1152 1153 static const struct dss_features am43xx_dss_feats = { 1154 .model = DSS_MODEL_OMAP3, 1155 .fck_div_max = 0, 1156 .fck_freq_max = 200000000, 1157 .dss_fck_multiplier = 0, 1158 .parent_clk_name = NULL, 1159 .ports = omap2plus_ports, 1160 .num_ports = ARRAY_SIZE(omap2plus_ports), 1161 .outputs = am43xx_dss_supported_outputs, 1162 .ops = &dss_ops_omap2_omap3, 1163 .dispc_clk_switch = { 0, 0 }, 1164 .has_lcd_clk_src = true, 1165 }; 1166 1167 static const struct dss_features dra7xx_dss_feats = { 1168 .model = DSS_MODEL_DRA7, 1169 .fck_div_max = 64, 1170 .fck_freq_max = 209250000, 1171 .dss_fck_multiplier = 1, 1172 .parent_clk_name = "dpll_per_x2_ck", 1173 .ports = dra7xx_ports, 1174 .num_ports = ARRAY_SIZE(dra7xx_ports), 1175 .outputs = omap5_dss_supported_outputs, 1176 .ops = &dss_ops_dra7, 1177 .dispc_clk_switch = { 9, 7 }, 1178 .has_lcd_clk_src = true, 1179 }; 1180 1181 static int dss_init_ports(struct dss_device *dss) 1182 { 1183 struct platform_device *pdev = dss->pdev; 1184 struct device_node *parent = pdev->dev.of_node; 1185 struct device_node *port; 1186 int i; 1187 1188 for (i = 0; i < dss->feat->num_ports; i++) { 1189 port = of_graph_get_port_by_id(parent, i); 1190 if (!port) 1191 continue; 1192 1193 switch (dss->feat->ports[i]) { 1194 case OMAP_DISPLAY_TYPE_DPI: 1195 dpi_init_port(dss, pdev, port, dss->feat->model); 1196 break; 1197 case OMAP_DISPLAY_TYPE_SDI: 1198 sdi_init_port(dss, pdev, port); 1199 break; 1200 default: 1201 break; 1202 } 1203 } 1204 1205 return 0; 1206 } 1207 1208 static void dss_uninit_ports(struct dss_device *dss) 1209 { 1210 struct platform_device *pdev = dss->pdev; 1211 struct device_node *parent = pdev->dev.of_node; 1212 struct device_node *port; 1213 int i; 1214 1215 for (i = 0; i < dss->feat->num_ports; i++) { 1216 port = of_graph_get_port_by_id(parent, i); 1217 if (!port) 1218 continue; 1219 1220 switch (dss->feat->ports[i]) { 1221 case OMAP_DISPLAY_TYPE_DPI: 1222 dpi_uninit_port(port); 1223 break; 1224 case OMAP_DISPLAY_TYPE_SDI: 1225 sdi_uninit_port(port); 1226 break; 1227 default: 1228 break; 1229 } 1230 } 1231 } 1232 1233 static int dss_video_pll_probe(struct dss_device *dss) 1234 { 1235 struct platform_device *pdev = dss->pdev; 1236 struct device_node *np = pdev->dev.of_node; 1237 struct regulator *pll_regulator; 1238 int r; 1239 1240 if (!np) 1241 return 0; 1242 1243 if (of_property_read_bool(np, "syscon-pll-ctrl")) { 1244 dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, 1245 "syscon-pll-ctrl"); 1246 if (IS_ERR(dss->syscon_pll_ctrl)) { 1247 dev_err(&pdev->dev, 1248 "failed to get syscon-pll-ctrl regmap\n"); 1249 return PTR_ERR(dss->syscon_pll_ctrl); 1250 } 1251 1252 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, 1253 &dss->syscon_pll_ctrl_offset)) { 1254 dev_err(&pdev->dev, 1255 "failed to get syscon-pll-ctrl offset\n"); 1256 return -EINVAL; 1257 } 1258 } 1259 1260 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); 1261 if (IS_ERR(pll_regulator)) { 1262 r = PTR_ERR(pll_regulator); 1263 1264 switch (r) { 1265 case -ENOENT: 1266 pll_regulator = NULL; 1267 break; 1268 1269 case -EPROBE_DEFER: 1270 return -EPROBE_DEFER; 1271 1272 default: 1273 DSSERR("can't get DPLL VDDA regulator\n"); 1274 return r; 1275 } 1276 } 1277 1278 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { 1279 dss->video1_pll = dss_video_pll_init(dss, pdev, 0, 1280 pll_regulator); 1281 if (IS_ERR(dss->video1_pll)) 1282 return PTR_ERR(dss->video1_pll); 1283 } 1284 1285 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { 1286 dss->video2_pll = dss_video_pll_init(dss, pdev, 1, 1287 pll_regulator); 1288 if (IS_ERR(dss->video2_pll)) { 1289 dss_video_pll_uninit(dss->video1_pll); 1290 return PTR_ERR(dss->video2_pll); 1291 } 1292 } 1293 1294 return 0; 1295 } 1296 1297 /* DSS HW IP initialisation */ 1298 static const struct of_device_id dss_of_match[] = { 1299 { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats }, 1300 { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats }, 1301 { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats }, 1302 { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats }, 1303 { .compatible = "ti,dra7-dss", .data = &dra7xx_dss_feats }, 1304 {}, 1305 }; 1306 MODULE_DEVICE_TABLE(of, dss_of_match); 1307 1308 static const struct soc_device_attribute dss_soc_devices[] = { 1309 { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats }, 1310 { .machine = "AM35??", .data = &omap34xx_dss_feats }, 1311 { .family = "AM43xx", .data = &am43xx_dss_feats }, 1312 { /* sentinel */ } 1313 }; 1314 1315 static int dss_bind(struct device *dev) 1316 { 1317 struct dss_device *dss = dev_get_drvdata(dev); 1318 int r; 1319 1320 r = component_bind_all(dev, NULL); 1321 if (r) 1322 return r; 1323 1324 pm_set_vt_switch(0); 1325 1326 omapdss_gather_components(dev); 1327 omapdss_set_dss(dss); 1328 1329 return 0; 1330 } 1331 1332 static void dss_unbind(struct device *dev) 1333 { 1334 omapdss_set_dss(NULL); 1335 1336 component_unbind_all(dev, NULL); 1337 } 1338 1339 static const struct component_master_ops dss_component_ops = { 1340 .bind = dss_bind, 1341 .unbind = dss_unbind, 1342 }; 1343 1344 static int dss_component_compare(struct device *dev, void *data) 1345 { 1346 struct device *child = data; 1347 return dev == child; 1348 } 1349 1350 static int dss_add_child_component(struct device *dev, void *data) 1351 { 1352 struct component_match **match = data; 1353 1354 /* 1355 * HACK 1356 * We don't have a working driver for rfbi, so skip it here always. 1357 * Otherwise dss will never get probed successfully, as it will wait 1358 * for rfbi to get probed. 1359 */ 1360 if (strstr(dev_name(dev), "rfbi")) 1361 return 0; 1362 1363 component_match_add(dev->parent, match, dss_component_compare, dev); 1364 1365 return 0; 1366 } 1367 1368 static int dss_probe_hardware(struct dss_device *dss) 1369 { 1370 u32 rev; 1371 int r; 1372 1373 r = dss_runtime_get(dss); 1374 if (r) 1375 return r; 1376 1377 dss->dss_clk_rate = clk_get_rate(dss->dss_clk); 1378 1379 /* Select DPLL */ 1380 REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0); 1381 1382 dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK); 1383 1384 #ifdef CONFIG_OMAP2_DSS_VENC 1385 REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 1386 REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 1387 REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 1388 #endif 1389 dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK; 1390 dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK; 1391 dss->dispc_clk_source = DSS_CLK_SRC_FCK; 1392 dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK; 1393 dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK; 1394 1395 rev = dss_read_reg(dss, DSS_REVISION); 1396 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 1397 1398 dss_runtime_put(dss); 1399 1400 return 0; 1401 } 1402 1403 static int dss_probe(struct platform_device *pdev) 1404 { 1405 const struct soc_device_attribute *soc; 1406 struct component_match *match = NULL; 1407 struct resource *dss_mem; 1408 struct dss_device *dss; 1409 int r; 1410 1411 dss = kzalloc(sizeof(*dss), GFP_KERNEL); 1412 if (!dss) 1413 return -ENOMEM; 1414 1415 dss->pdev = pdev; 1416 platform_set_drvdata(pdev, dss); 1417 1418 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1419 if (r) { 1420 dev_err(&pdev->dev, "Failed to set the DMA mask\n"); 1421 goto err_free_dss; 1422 } 1423 1424 /* 1425 * The various OMAP3-based SoCs can't be told apart using the compatible 1426 * string, use SoC device matching. 1427 */ 1428 soc = soc_device_match(dss_soc_devices); 1429 if (soc) 1430 dss->feat = soc->data; 1431 else 1432 dss->feat = of_match_device(dss_of_match, &pdev->dev)->data; 1433 1434 /* Map I/O registers, get and setup clocks. */ 1435 dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1436 dss->base = devm_ioremap_resource(&pdev->dev, dss_mem); 1437 if (IS_ERR(dss->base)) { 1438 r = PTR_ERR(dss->base); 1439 goto err_free_dss; 1440 } 1441 1442 r = dss_get_clocks(dss); 1443 if (r) 1444 goto err_free_dss; 1445 1446 r = dss_setup_default_clock(dss); 1447 if (r) 1448 goto err_put_clocks; 1449 1450 /* Setup the video PLLs and the DPI and SDI ports. */ 1451 r = dss_video_pll_probe(dss); 1452 if (r) 1453 goto err_put_clocks; 1454 1455 r = dss_init_ports(dss); 1456 if (r) 1457 goto err_uninit_plls; 1458 1459 /* Enable runtime PM and probe the hardware. */ 1460 pm_runtime_enable(&pdev->dev); 1461 1462 r = dss_probe_hardware(dss); 1463 if (r) 1464 goto err_pm_runtime_disable; 1465 1466 /* Initialize debugfs. */ 1467 r = dss_initialize_debugfs(dss); 1468 if (r) 1469 goto err_pm_runtime_disable; 1470 1471 dss->debugfs.clk = dss_debugfs_create_file(dss, "clk", 1472 dss_debug_dump_clocks, dss); 1473 dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs, 1474 dss); 1475 1476 /* Add all the child devices as components. */ 1477 device_for_each_child(&pdev->dev, &match, dss_add_child_component); 1478 1479 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); 1480 if (r) 1481 goto err_uninit_debugfs; 1482 1483 return 0; 1484 1485 err_uninit_debugfs: 1486 dss_debugfs_remove_file(dss->debugfs.clk); 1487 dss_debugfs_remove_file(dss->debugfs.dss); 1488 dss_uninitialize_debugfs(dss); 1489 1490 err_pm_runtime_disable: 1491 pm_runtime_disable(&pdev->dev); 1492 dss_uninit_ports(dss); 1493 1494 err_uninit_plls: 1495 if (dss->video1_pll) 1496 dss_video_pll_uninit(dss->video1_pll); 1497 if (dss->video2_pll) 1498 dss_video_pll_uninit(dss->video2_pll); 1499 1500 err_put_clocks: 1501 dss_put_clocks(dss); 1502 1503 err_free_dss: 1504 kfree(dss); 1505 1506 return r; 1507 } 1508 1509 static int dss_remove(struct platform_device *pdev) 1510 { 1511 struct dss_device *dss = platform_get_drvdata(pdev); 1512 1513 component_master_del(&pdev->dev, &dss_component_ops); 1514 1515 dss_debugfs_remove_file(dss->debugfs.clk); 1516 dss_debugfs_remove_file(dss->debugfs.dss); 1517 dss_uninitialize_debugfs(dss); 1518 1519 pm_runtime_disable(&pdev->dev); 1520 1521 dss_uninit_ports(dss); 1522 1523 if (dss->video1_pll) 1524 dss_video_pll_uninit(dss->video1_pll); 1525 1526 if (dss->video2_pll) 1527 dss_video_pll_uninit(dss->video2_pll); 1528 1529 dss_put_clocks(dss); 1530 1531 kfree(dss); 1532 1533 return 0; 1534 } 1535 1536 static void dss_shutdown(struct platform_device *pdev) 1537 { 1538 struct omap_dss_device *dssdev = NULL; 1539 1540 DSSDBG("shutdown\n"); 1541 1542 for_each_dss_dev(dssdev) { 1543 if (!dssdev->driver) 1544 continue; 1545 1546 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) 1547 dssdev->driver->disable(dssdev); 1548 } 1549 } 1550 1551 static int dss_runtime_suspend(struct device *dev) 1552 { 1553 struct dss_device *dss = dev_get_drvdata(dev); 1554 1555 dss_save_context(dss); 1556 dss_set_min_bus_tput(dev, 0); 1557 1558 pinctrl_pm_select_sleep_state(dev); 1559 1560 return 0; 1561 } 1562 1563 static int dss_runtime_resume(struct device *dev) 1564 { 1565 struct dss_device *dss = dev_get_drvdata(dev); 1566 int r; 1567 1568 pinctrl_pm_select_default_state(dev); 1569 1570 /* 1571 * Set an arbitrarily high tput request to ensure OPP100. 1572 * What we should really do is to make a request to stay in OPP100, 1573 * without any tput requirements, but that is not currently possible 1574 * via the PM layer. 1575 */ 1576 1577 r = dss_set_min_bus_tput(dev, 1000000000); 1578 if (r) 1579 return r; 1580 1581 dss_restore_context(dss); 1582 return 0; 1583 } 1584 1585 static const struct dev_pm_ops dss_pm_ops = { 1586 .runtime_suspend = dss_runtime_suspend, 1587 .runtime_resume = dss_runtime_resume, 1588 }; 1589 1590 struct platform_driver omap_dsshw_driver = { 1591 .probe = dss_probe, 1592 .remove = dss_remove, 1593 .shutdown = dss_shutdown, 1594 .driver = { 1595 .name = "omapdss_dss", 1596 .pm = &dss_pm_ops, 1597 .of_match_table = dss_of_match, 1598 .suppress_bind_attrs = true, 1599 }, 1600 }; 1601