1 /* 2 * linux/drivers/video/omap2/dss/dss.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #define DSS_SUBSYS_NAME "DSS" 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/io.h> 28 #include <linux/export.h> 29 #include <linux/err.h> 30 #include <linux/delay.h> 31 #include <linux/seq_file.h> 32 #include <linux/clk.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/gfp.h> 37 #include <linux/sizes.h> 38 #include <linux/mfd/syscon.h> 39 #include <linux/regmap.h> 40 #include <linux/of.h> 41 #include <linux/of_graph.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/suspend.h> 44 #include <linux/component.h> 45 46 #include "omapdss.h" 47 #include "dss.h" 48 #include "dss_features.h" 49 50 #define DSS_SZ_REGS SZ_512 51 52 struct dss_reg { 53 u16 idx; 54 }; 55 56 #define DSS_REG(idx) ((const struct dss_reg) { idx }) 57 58 #define DSS_REVISION DSS_REG(0x0000) 59 #define DSS_SYSCONFIG DSS_REG(0x0010) 60 #define DSS_SYSSTATUS DSS_REG(0x0014) 61 #define DSS_CONTROL DSS_REG(0x0040) 62 #define DSS_SDI_CONTROL DSS_REG(0x0044) 63 #define DSS_PLL_CONTROL DSS_REG(0x0048) 64 #define DSS_SDI_STATUS DSS_REG(0x005C) 65 66 #define REG_GET(idx, start, end) \ 67 FLD_GET(dss_read_reg(idx), start, end) 68 69 #define REG_FLD_MOD(idx, val, start, end) \ 70 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 71 72 struct dss_features { 73 u8 fck_div_max; 74 u8 dss_fck_multiplier; 75 const char *parent_clk_name; 76 const enum omap_display_type *ports; 77 int num_ports; 78 int (*dpi_select_source)(int port, enum omap_channel channel); 79 int (*select_lcd_source)(enum omap_channel channel, 80 enum dss_clk_source clk_src); 81 }; 82 83 static struct { 84 struct platform_device *pdev; 85 void __iomem *base; 86 struct regmap *syscon_pll_ctrl; 87 u32 syscon_pll_ctrl_offset; 88 89 struct clk *parent_clk; 90 struct clk *dss_clk; 91 unsigned long dss_clk_rate; 92 93 unsigned long cache_req_pck; 94 unsigned long cache_prate; 95 struct dispc_clock_info cache_dispc_cinfo; 96 97 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 98 enum dss_clk_source dispc_clk_source; 99 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 100 101 bool ctx_valid; 102 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 103 104 const struct dss_features *feat; 105 106 struct dss_pll *video1_pll; 107 struct dss_pll *video2_pll; 108 } dss; 109 110 static const char * const dss_generic_clk_source_names[] = { 111 [DSS_CLK_SRC_FCK] = "FCK", 112 [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 113 [DSS_CLK_SRC_PLL1_2] = "PLL1:2", 114 [DSS_CLK_SRC_PLL1_3] = "PLL1:3", 115 [DSS_CLK_SRC_PLL2_1] = "PLL2:1", 116 [DSS_CLK_SRC_PLL2_2] = "PLL2:2", 117 [DSS_CLK_SRC_PLL2_3] = "PLL2:3", 118 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 119 }; 120 121 static inline void dss_write_reg(const struct dss_reg idx, u32 val) 122 { 123 __raw_writel(val, dss.base + idx.idx); 124 } 125 126 static inline u32 dss_read_reg(const struct dss_reg idx) 127 { 128 return __raw_readl(dss.base + idx.idx); 129 } 130 131 #define SR(reg) \ 132 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) 133 #define RR(reg) \ 134 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) 135 136 static void dss_save_context(void) 137 { 138 DSSDBG("dss_save_context\n"); 139 140 SR(CONTROL); 141 142 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 143 OMAP_DISPLAY_TYPE_SDI) { 144 SR(SDI_CONTROL); 145 SR(PLL_CONTROL); 146 } 147 148 dss.ctx_valid = true; 149 150 DSSDBG("context saved\n"); 151 } 152 153 static void dss_restore_context(void) 154 { 155 DSSDBG("dss_restore_context\n"); 156 157 if (!dss.ctx_valid) 158 return; 159 160 RR(CONTROL); 161 162 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 163 OMAP_DISPLAY_TYPE_SDI) { 164 RR(SDI_CONTROL); 165 RR(PLL_CONTROL); 166 } 167 168 DSSDBG("context restored\n"); 169 } 170 171 #undef SR 172 #undef RR 173 174 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) 175 { 176 unsigned shift; 177 unsigned val; 178 179 if (!dss.syscon_pll_ctrl) 180 return; 181 182 val = !enable; 183 184 switch (pll_id) { 185 case DSS_PLL_VIDEO1: 186 shift = 0; 187 break; 188 case DSS_PLL_VIDEO2: 189 shift = 1; 190 break; 191 case DSS_PLL_HDMI: 192 shift = 2; 193 break; 194 default: 195 DSSERR("illegal DSS PLL ID %d\n", pll_id); 196 return; 197 } 198 199 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 200 1 << shift, val << shift); 201 } 202 203 static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, 204 enum omap_channel channel) 205 { 206 unsigned shift, val; 207 208 if (!dss.syscon_pll_ctrl) 209 return -EINVAL; 210 211 switch (channel) { 212 case OMAP_DSS_CHANNEL_LCD: 213 shift = 3; 214 215 switch (clk_src) { 216 case DSS_CLK_SRC_PLL1_1: 217 val = 0; break; 218 case DSS_CLK_SRC_HDMI_PLL: 219 val = 1; break; 220 default: 221 DSSERR("error in PLL mux config for LCD\n"); 222 return -EINVAL; 223 } 224 225 break; 226 case OMAP_DSS_CHANNEL_LCD2: 227 shift = 5; 228 229 switch (clk_src) { 230 case DSS_CLK_SRC_PLL1_3: 231 val = 0; break; 232 case DSS_CLK_SRC_PLL2_3: 233 val = 1; break; 234 case DSS_CLK_SRC_HDMI_PLL: 235 val = 2; break; 236 default: 237 DSSERR("error in PLL mux config for LCD2\n"); 238 return -EINVAL; 239 } 240 241 break; 242 case OMAP_DSS_CHANNEL_LCD3: 243 shift = 7; 244 245 switch (clk_src) { 246 case DSS_CLK_SRC_PLL2_1: 247 val = 0; break; 248 case DSS_CLK_SRC_PLL1_3: 249 val = 1; break; 250 case DSS_CLK_SRC_HDMI_PLL: 251 val = 2; break; 252 default: 253 DSSERR("error in PLL mux config for LCD3\n"); 254 return -EINVAL; 255 } 256 257 break; 258 default: 259 DSSERR("error in PLL mux config\n"); 260 return -EINVAL; 261 } 262 263 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 264 0x3 << shift, val << shift); 265 266 return 0; 267 } 268 269 void dss_sdi_init(int datapairs) 270 { 271 u32 l; 272 273 BUG_ON(datapairs > 3 || datapairs < 1); 274 275 l = dss_read_reg(DSS_SDI_CONTROL); 276 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 277 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 278 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 279 dss_write_reg(DSS_SDI_CONTROL, l); 280 281 l = dss_read_reg(DSS_PLL_CONTROL); 282 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 283 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 284 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 285 dss_write_reg(DSS_PLL_CONTROL, l); 286 } 287 288 int dss_sdi_enable(void) 289 { 290 unsigned long timeout; 291 292 dispc_pck_free_enable(1); 293 294 /* Reset SDI PLL */ 295 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 296 udelay(1); /* wait 2x PCLK */ 297 298 /* Lock SDI PLL */ 299 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 300 301 /* Waiting for PLL lock request to complete */ 302 timeout = jiffies + msecs_to_jiffies(500); 303 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { 304 if (time_after_eq(jiffies, timeout)) { 305 DSSERR("PLL lock request timed out\n"); 306 goto err1; 307 } 308 } 309 310 /* Clearing PLL_GO bit */ 311 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 312 313 /* Waiting for PLL to lock */ 314 timeout = jiffies + msecs_to_jiffies(500); 315 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { 316 if (time_after_eq(jiffies, timeout)) { 317 DSSERR("PLL lock timed out\n"); 318 goto err1; 319 } 320 } 321 322 dispc_lcd_enable_signal(1); 323 324 /* Waiting for SDI reset to complete */ 325 timeout = jiffies + msecs_to_jiffies(500); 326 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { 327 if (time_after_eq(jiffies, timeout)) { 328 DSSERR("SDI reset timed out\n"); 329 goto err2; 330 } 331 } 332 333 return 0; 334 335 err2: 336 dispc_lcd_enable_signal(0); 337 err1: 338 /* Reset SDI PLL */ 339 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 340 341 dispc_pck_free_enable(0); 342 343 return -ETIMEDOUT; 344 } 345 346 void dss_sdi_disable(void) 347 { 348 dispc_lcd_enable_signal(0); 349 350 dispc_pck_free_enable(0); 351 352 /* Reset SDI PLL */ 353 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 354 } 355 356 const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 357 { 358 return dss_generic_clk_source_names[clk_src]; 359 } 360 361 void dss_dump_clocks(struct seq_file *s) 362 { 363 const char *fclk_name; 364 unsigned long fclk_rate; 365 366 if (dss_runtime_get()) 367 return; 368 369 seq_printf(s, "- DSS -\n"); 370 371 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 372 fclk_rate = clk_get_rate(dss.dss_clk); 373 374 seq_printf(s, "%s = %lu\n", 375 fclk_name, 376 fclk_rate); 377 378 dss_runtime_put(); 379 } 380 381 static void dss_dump_regs(struct seq_file *s) 382 { 383 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 384 385 if (dss_runtime_get()) 386 return; 387 388 DUMPREG(DSS_REVISION); 389 DUMPREG(DSS_SYSCONFIG); 390 DUMPREG(DSS_SYSSTATUS); 391 DUMPREG(DSS_CONTROL); 392 393 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 394 OMAP_DISPLAY_TYPE_SDI) { 395 DUMPREG(DSS_SDI_CONTROL); 396 DUMPREG(DSS_PLL_CONTROL); 397 DUMPREG(DSS_SDI_STATUS); 398 } 399 400 dss_runtime_put(); 401 #undef DUMPREG 402 } 403 404 static int dss_get_channel_index(enum omap_channel channel) 405 { 406 switch (channel) { 407 case OMAP_DSS_CHANNEL_LCD: 408 return 0; 409 case OMAP_DSS_CHANNEL_LCD2: 410 return 1; 411 case OMAP_DSS_CHANNEL_LCD3: 412 return 2; 413 default: 414 WARN_ON(1); 415 return 0; 416 } 417 } 418 419 static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 420 { 421 int b; 422 u8 start, end; 423 424 /* 425 * We always use PRCM clock as the DISPC func clock, except on DSS3, 426 * where we don't have separate DISPC and LCD clock sources. 427 */ 428 if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC) && 429 clk_src != DSS_CLK_SRC_FCK)) 430 return; 431 432 switch (clk_src) { 433 case DSS_CLK_SRC_FCK: 434 b = 0; 435 break; 436 case DSS_CLK_SRC_PLL1_1: 437 b = 1; 438 break; 439 case DSS_CLK_SRC_PLL2_1: 440 b = 2; 441 break; 442 default: 443 BUG(); 444 return; 445 } 446 447 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); 448 449 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ 450 451 dss.dispc_clk_source = clk_src; 452 } 453 454 void dss_select_dsi_clk_source(int dsi_module, 455 enum dss_clk_source clk_src) 456 { 457 int b, pos; 458 459 switch (clk_src) { 460 case DSS_CLK_SRC_FCK: 461 b = 0; 462 break; 463 case DSS_CLK_SRC_PLL1_2: 464 BUG_ON(dsi_module != 0); 465 b = 1; 466 break; 467 case DSS_CLK_SRC_PLL2_2: 468 BUG_ON(dsi_module != 1); 469 b = 1; 470 break; 471 default: 472 BUG(); 473 return; 474 } 475 476 pos = dsi_module == 0 ? 1 : 10; 477 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 478 479 dss.dsi_clk_source[dsi_module] = clk_src; 480 } 481 482 static int dss_lcd_clk_mux_dra7(enum omap_channel channel, 483 enum dss_clk_source clk_src) 484 { 485 const u8 ctrl_bits[] = { 486 [OMAP_DSS_CHANNEL_LCD] = 0, 487 [OMAP_DSS_CHANNEL_LCD2] = 12, 488 [OMAP_DSS_CHANNEL_LCD3] = 19, 489 }; 490 491 u8 ctrl_bit = ctrl_bits[channel]; 492 int r; 493 494 if (clk_src == DSS_CLK_SRC_FCK) { 495 /* LCDx_CLK_SWITCH */ 496 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 497 return -EINVAL; 498 } 499 500 r = dss_ctrl_pll_set_control_mux(clk_src, channel); 501 if (r) 502 return r; 503 504 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 505 506 return 0; 507 } 508 509 static int dss_lcd_clk_mux_omap5(enum omap_channel channel, 510 enum dss_clk_source clk_src) 511 { 512 const u8 ctrl_bits[] = { 513 [OMAP_DSS_CHANNEL_LCD] = 0, 514 [OMAP_DSS_CHANNEL_LCD2] = 12, 515 [OMAP_DSS_CHANNEL_LCD3] = 19, 516 }; 517 const enum dss_clk_source allowed_plls[] = { 518 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 519 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, 520 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, 521 }; 522 523 u8 ctrl_bit = ctrl_bits[channel]; 524 525 if (clk_src == DSS_CLK_SRC_FCK) { 526 /* LCDx_CLK_SWITCH */ 527 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 528 return -EINVAL; 529 } 530 531 if (WARN_ON(allowed_plls[channel] != clk_src)) 532 return -EINVAL; 533 534 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 535 536 return 0; 537 } 538 539 static int dss_lcd_clk_mux_omap4(enum omap_channel channel, 540 enum dss_clk_source clk_src) 541 { 542 const u8 ctrl_bits[] = { 543 [OMAP_DSS_CHANNEL_LCD] = 0, 544 [OMAP_DSS_CHANNEL_LCD2] = 12, 545 }; 546 const enum dss_clk_source allowed_plls[] = { 547 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 548 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, 549 }; 550 551 u8 ctrl_bit = ctrl_bits[channel]; 552 553 if (clk_src == DSS_CLK_SRC_FCK) { 554 /* LCDx_CLK_SWITCH */ 555 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 556 return 0; 557 } 558 559 if (WARN_ON(allowed_plls[channel] != clk_src)) 560 return -EINVAL; 561 562 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 563 564 return 0; 565 } 566 567 void dss_select_lcd_clk_source(enum omap_channel channel, 568 enum dss_clk_source clk_src) 569 { 570 int idx = dss_get_channel_index(channel); 571 int r; 572 573 if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { 574 dss_select_dispc_clk_source(clk_src); 575 dss.lcd_clk_source[idx] = clk_src; 576 return; 577 } 578 579 r = dss.feat->select_lcd_source(channel, clk_src); 580 if (r) 581 return; 582 583 dss.lcd_clk_source[idx] = clk_src; 584 } 585 586 enum dss_clk_source dss_get_dispc_clk_source(void) 587 { 588 return dss.dispc_clk_source; 589 } 590 591 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) 592 { 593 return dss.dsi_clk_source[dsi_module]; 594 } 595 596 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 597 { 598 if (dss_has_feature(FEAT_LCD_CLK_SRC)) { 599 int idx = dss_get_channel_index(channel); 600 return dss.lcd_clk_source[idx]; 601 } else { 602 /* LCD_CLK source is the same as DISPC_FCLK source for 603 * OMAP2 and OMAP3 */ 604 return dss.dispc_clk_source; 605 } 606 } 607 608 bool dss_div_calc(unsigned long pck, unsigned long fck_min, 609 dss_div_calc_func func, void *data) 610 { 611 int fckd, fckd_start, fckd_stop; 612 unsigned long fck; 613 unsigned long fck_hw_max; 614 unsigned long fckd_hw_max; 615 unsigned long prate; 616 unsigned m; 617 618 fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 619 620 if (dss.parent_clk == NULL) { 621 unsigned pckd; 622 623 pckd = fck_hw_max / pck; 624 625 fck = pck * pckd; 626 627 fck = clk_round_rate(dss.dss_clk, fck); 628 629 return func(fck, data); 630 } 631 632 fckd_hw_max = dss.feat->fck_div_max; 633 634 m = dss.feat->dss_fck_multiplier; 635 prate = clk_get_rate(dss.parent_clk); 636 637 fck_min = fck_min ? fck_min : 1; 638 639 fckd_start = min(prate * m / fck_min, fckd_hw_max); 640 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); 641 642 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { 643 fck = DIV_ROUND_UP(prate, fckd) * m; 644 645 if (func(fck, data)) 646 return true; 647 } 648 649 return false; 650 } 651 652 int dss_set_fck_rate(unsigned long rate) 653 { 654 int r; 655 656 DSSDBG("set fck to %lu\n", rate); 657 658 r = clk_set_rate(dss.dss_clk, rate); 659 if (r) 660 return r; 661 662 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 663 664 WARN_ONCE(dss.dss_clk_rate != rate, 665 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, 666 rate); 667 668 return 0; 669 } 670 671 unsigned long dss_get_dispc_clk_rate(void) 672 { 673 return dss.dss_clk_rate; 674 } 675 676 static int dss_setup_default_clock(void) 677 { 678 unsigned long max_dss_fck, prate; 679 unsigned long fck; 680 unsigned fck_div; 681 int r; 682 683 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 684 685 if (dss.parent_clk == NULL) { 686 fck = clk_round_rate(dss.dss_clk, max_dss_fck); 687 } else { 688 prate = clk_get_rate(dss.parent_clk); 689 690 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, 691 max_dss_fck); 692 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; 693 } 694 695 r = dss_set_fck_rate(fck); 696 if (r) 697 return r; 698 699 return 0; 700 } 701 702 void dss_set_venc_output(enum omap_dss_venc_type type) 703 { 704 int l = 0; 705 706 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) 707 l = 0; 708 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) 709 l = 1; 710 else 711 BUG(); 712 713 /* venc out selection. 0 = comp, 1 = svideo */ 714 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); 715 } 716 717 void dss_set_dac_pwrdn_bgz(bool enable) 718 { 719 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ 720 } 721 722 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) 723 { 724 enum omap_display_type dp; 725 dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); 726 727 /* Complain about invalid selections */ 728 WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); 729 WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); 730 731 /* Select only if we have options */ 732 if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) 733 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ 734 } 735 736 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) 737 { 738 enum omap_display_type displays; 739 740 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); 741 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) 742 return DSS_VENC_TV_CLK; 743 744 if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) 745 return DSS_HDMI_M_PCLK; 746 747 return REG_GET(DSS_CONTROL, 15, 15); 748 } 749 750 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) 751 { 752 if (channel != OMAP_DSS_CHANNEL_LCD) 753 return -EINVAL; 754 755 return 0; 756 } 757 758 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) 759 { 760 int val; 761 762 switch (channel) { 763 case OMAP_DSS_CHANNEL_LCD2: 764 val = 0; 765 break; 766 case OMAP_DSS_CHANNEL_DIGIT: 767 val = 1; 768 break; 769 default: 770 return -EINVAL; 771 } 772 773 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); 774 775 return 0; 776 } 777 778 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) 779 { 780 int val; 781 782 switch (channel) { 783 case OMAP_DSS_CHANNEL_LCD: 784 val = 1; 785 break; 786 case OMAP_DSS_CHANNEL_LCD2: 787 val = 2; 788 break; 789 case OMAP_DSS_CHANNEL_LCD3: 790 val = 3; 791 break; 792 case OMAP_DSS_CHANNEL_DIGIT: 793 val = 0; 794 break; 795 default: 796 return -EINVAL; 797 } 798 799 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); 800 801 return 0; 802 } 803 804 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) 805 { 806 switch (port) { 807 case 0: 808 return dss_dpi_select_source_omap5(port, channel); 809 case 1: 810 if (channel != OMAP_DSS_CHANNEL_LCD2) 811 return -EINVAL; 812 break; 813 case 2: 814 if (channel != OMAP_DSS_CHANNEL_LCD3) 815 return -EINVAL; 816 break; 817 default: 818 return -EINVAL; 819 } 820 821 return 0; 822 } 823 824 int dss_dpi_select_source(int port, enum omap_channel channel) 825 { 826 return dss.feat->dpi_select_source(port, channel); 827 } 828 829 static int dss_get_clocks(void) 830 { 831 struct clk *clk; 832 833 clk = devm_clk_get(&dss.pdev->dev, "fck"); 834 if (IS_ERR(clk)) { 835 DSSERR("can't get clock fck\n"); 836 return PTR_ERR(clk); 837 } 838 839 dss.dss_clk = clk; 840 841 if (dss.feat->parent_clk_name) { 842 clk = clk_get(NULL, dss.feat->parent_clk_name); 843 if (IS_ERR(clk)) { 844 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); 845 return PTR_ERR(clk); 846 } 847 } else { 848 clk = NULL; 849 } 850 851 dss.parent_clk = clk; 852 853 return 0; 854 } 855 856 static void dss_put_clocks(void) 857 { 858 if (dss.parent_clk) 859 clk_put(dss.parent_clk); 860 } 861 862 int dss_runtime_get(void) 863 { 864 int r; 865 866 DSSDBG("dss_runtime_get\n"); 867 868 r = pm_runtime_get_sync(&dss.pdev->dev); 869 WARN_ON(r < 0); 870 return r < 0 ? r : 0; 871 } 872 873 void dss_runtime_put(void) 874 { 875 int r; 876 877 DSSDBG("dss_runtime_put\n"); 878 879 r = pm_runtime_put_sync(&dss.pdev->dev); 880 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); 881 } 882 883 /* DEBUGFS */ 884 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 885 void dss_debug_dump_clocks(struct seq_file *s) 886 { 887 dss_dump_clocks(s); 888 dispc_dump_clocks(s); 889 #ifdef CONFIG_OMAP2_DSS_DSI 890 dsi_dump_clocks(s); 891 #endif 892 } 893 #endif 894 895 896 static const enum omap_display_type omap2plus_ports[] = { 897 OMAP_DISPLAY_TYPE_DPI, 898 }; 899 900 static const enum omap_display_type omap34xx_ports[] = { 901 OMAP_DISPLAY_TYPE_DPI, 902 OMAP_DISPLAY_TYPE_SDI, 903 }; 904 905 static const enum omap_display_type dra7xx_ports[] = { 906 OMAP_DISPLAY_TYPE_DPI, 907 OMAP_DISPLAY_TYPE_DPI, 908 OMAP_DISPLAY_TYPE_DPI, 909 }; 910 911 static const struct dss_features omap24xx_dss_feats = { 912 /* 913 * fck div max is really 16, but the divider range has gaps. The range 914 * from 1 to 6 has no gaps, so let's use that as a max. 915 */ 916 .fck_div_max = 6, 917 .dss_fck_multiplier = 2, 918 .parent_clk_name = "core_ck", 919 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 920 .ports = omap2plus_ports, 921 .num_ports = ARRAY_SIZE(omap2plus_ports), 922 }; 923 924 static const struct dss_features omap34xx_dss_feats = { 925 .fck_div_max = 16, 926 .dss_fck_multiplier = 2, 927 .parent_clk_name = "dpll4_ck", 928 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 929 .ports = omap34xx_ports, 930 .num_ports = ARRAY_SIZE(omap34xx_ports), 931 }; 932 933 static const struct dss_features omap3630_dss_feats = { 934 .fck_div_max = 32, 935 .dss_fck_multiplier = 1, 936 .parent_clk_name = "dpll4_ck", 937 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 938 .ports = omap2plus_ports, 939 .num_ports = ARRAY_SIZE(omap2plus_ports), 940 }; 941 942 static const struct dss_features omap44xx_dss_feats = { 943 .fck_div_max = 32, 944 .dss_fck_multiplier = 1, 945 .parent_clk_name = "dpll_per_x2_ck", 946 .dpi_select_source = &dss_dpi_select_source_omap4, 947 .ports = omap2plus_ports, 948 .num_ports = ARRAY_SIZE(omap2plus_ports), 949 .select_lcd_source = &dss_lcd_clk_mux_omap4, 950 }; 951 952 static const struct dss_features omap54xx_dss_feats = { 953 .fck_div_max = 64, 954 .dss_fck_multiplier = 1, 955 .parent_clk_name = "dpll_per_x2_ck", 956 .dpi_select_source = &dss_dpi_select_source_omap5, 957 .ports = omap2plus_ports, 958 .num_ports = ARRAY_SIZE(omap2plus_ports), 959 .select_lcd_source = &dss_lcd_clk_mux_omap5, 960 }; 961 962 static const struct dss_features am43xx_dss_feats = { 963 .fck_div_max = 0, 964 .dss_fck_multiplier = 0, 965 .parent_clk_name = NULL, 966 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 967 .ports = omap2plus_ports, 968 .num_ports = ARRAY_SIZE(omap2plus_ports), 969 }; 970 971 static const struct dss_features dra7xx_dss_feats = { 972 .fck_div_max = 64, 973 .dss_fck_multiplier = 1, 974 .parent_clk_name = "dpll_per_x2_ck", 975 .dpi_select_source = &dss_dpi_select_source_dra7xx, 976 .ports = dra7xx_ports, 977 .num_ports = ARRAY_SIZE(dra7xx_ports), 978 .select_lcd_source = &dss_lcd_clk_mux_dra7, 979 }; 980 981 static int dss_init_features(struct platform_device *pdev) 982 { 983 const struct dss_features *src; 984 struct dss_features *dst; 985 986 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); 987 if (!dst) { 988 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n"); 989 return -ENOMEM; 990 } 991 992 switch (omapdss_get_version()) { 993 case OMAPDSS_VER_OMAP24xx: 994 src = &omap24xx_dss_feats; 995 break; 996 997 case OMAPDSS_VER_OMAP34xx_ES1: 998 case OMAPDSS_VER_OMAP34xx_ES3: 999 case OMAPDSS_VER_AM35xx: 1000 src = &omap34xx_dss_feats; 1001 break; 1002 1003 case OMAPDSS_VER_OMAP3630: 1004 src = &omap3630_dss_feats; 1005 break; 1006 1007 case OMAPDSS_VER_OMAP4430_ES1: 1008 case OMAPDSS_VER_OMAP4430_ES2: 1009 case OMAPDSS_VER_OMAP4: 1010 src = &omap44xx_dss_feats; 1011 break; 1012 1013 case OMAPDSS_VER_OMAP5: 1014 src = &omap54xx_dss_feats; 1015 break; 1016 1017 case OMAPDSS_VER_AM43xx: 1018 src = &am43xx_dss_feats; 1019 break; 1020 1021 case OMAPDSS_VER_DRA7xx: 1022 src = &dra7xx_dss_feats; 1023 break; 1024 1025 default: 1026 return -ENODEV; 1027 } 1028 1029 memcpy(dst, src, sizeof(*dst)); 1030 dss.feat = dst; 1031 1032 return 0; 1033 } 1034 1035 static int dss_init_ports(struct platform_device *pdev) 1036 { 1037 struct device_node *parent = pdev->dev.of_node; 1038 struct device_node *port; 1039 int i; 1040 1041 for (i = 0; i < dss.feat->num_ports; i++) { 1042 port = of_graph_get_port_by_id(parent, i); 1043 if (!port) 1044 continue; 1045 1046 switch (dss.feat->ports[i]) { 1047 case OMAP_DISPLAY_TYPE_DPI: 1048 dpi_init_port(pdev, port); 1049 break; 1050 case OMAP_DISPLAY_TYPE_SDI: 1051 sdi_init_port(pdev, port); 1052 break; 1053 default: 1054 break; 1055 } 1056 } 1057 1058 return 0; 1059 } 1060 1061 static void dss_uninit_ports(struct platform_device *pdev) 1062 { 1063 struct device_node *parent = pdev->dev.of_node; 1064 struct device_node *port; 1065 int i; 1066 1067 for (i = 0; i < dss.feat->num_ports; i++) { 1068 port = of_graph_get_port_by_id(parent, i); 1069 if (!port) 1070 continue; 1071 1072 switch (dss.feat->ports[i]) { 1073 case OMAP_DISPLAY_TYPE_DPI: 1074 dpi_uninit_port(port); 1075 break; 1076 case OMAP_DISPLAY_TYPE_SDI: 1077 sdi_uninit_port(port); 1078 break; 1079 default: 1080 break; 1081 } 1082 } 1083 } 1084 1085 static int dss_video_pll_probe(struct platform_device *pdev) 1086 { 1087 struct device_node *np = pdev->dev.of_node; 1088 struct regulator *pll_regulator; 1089 int r; 1090 1091 if (!np) 1092 return 0; 1093 1094 if (of_property_read_bool(np, "syscon-pll-ctrl")) { 1095 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, 1096 "syscon-pll-ctrl"); 1097 if (IS_ERR(dss.syscon_pll_ctrl)) { 1098 dev_err(&pdev->dev, 1099 "failed to get syscon-pll-ctrl regmap\n"); 1100 return PTR_ERR(dss.syscon_pll_ctrl); 1101 } 1102 1103 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, 1104 &dss.syscon_pll_ctrl_offset)) { 1105 dev_err(&pdev->dev, 1106 "failed to get syscon-pll-ctrl offset\n"); 1107 return -EINVAL; 1108 } 1109 } 1110 1111 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); 1112 if (IS_ERR(pll_regulator)) { 1113 r = PTR_ERR(pll_regulator); 1114 1115 switch (r) { 1116 case -ENOENT: 1117 pll_regulator = NULL; 1118 break; 1119 1120 case -EPROBE_DEFER: 1121 return -EPROBE_DEFER; 1122 1123 default: 1124 DSSERR("can't get DPLL VDDA regulator\n"); 1125 return r; 1126 } 1127 } 1128 1129 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { 1130 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); 1131 if (IS_ERR(dss.video1_pll)) 1132 return PTR_ERR(dss.video1_pll); 1133 } 1134 1135 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { 1136 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); 1137 if (IS_ERR(dss.video2_pll)) { 1138 dss_video_pll_uninit(dss.video1_pll); 1139 return PTR_ERR(dss.video2_pll); 1140 } 1141 } 1142 1143 return 0; 1144 } 1145 1146 /* DSS HW IP initialisation */ 1147 static int dss_bind(struct device *dev) 1148 { 1149 struct platform_device *pdev = to_platform_device(dev); 1150 struct resource *dss_mem; 1151 u32 rev; 1152 int r; 1153 1154 dss.pdev = pdev; 1155 1156 r = dss_init_features(dss.pdev); 1157 if (r) 1158 return r; 1159 1160 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); 1161 if (!dss_mem) { 1162 DSSERR("can't get IORESOURCE_MEM DSS\n"); 1163 return -EINVAL; 1164 } 1165 1166 dss.base = devm_ioremap(&pdev->dev, dss_mem->start, 1167 resource_size(dss_mem)); 1168 if (!dss.base) { 1169 DSSERR("can't ioremap DSS\n"); 1170 return -ENOMEM; 1171 } 1172 1173 r = dss_get_clocks(); 1174 if (r) 1175 return r; 1176 1177 r = dss_setup_default_clock(); 1178 if (r) 1179 goto err_setup_clocks; 1180 1181 r = dss_video_pll_probe(pdev); 1182 if (r) 1183 goto err_pll_init; 1184 1185 r = dss_init_ports(pdev); 1186 if (r) 1187 goto err_init_ports; 1188 1189 pm_runtime_enable(&pdev->dev); 1190 1191 r = dss_runtime_get(); 1192 if (r) 1193 goto err_runtime_get; 1194 1195 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 1196 1197 /* Select DPLL */ 1198 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); 1199 1200 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); 1201 1202 #ifdef CONFIG_OMAP2_DSS_VENC 1203 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 1204 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 1205 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 1206 #endif 1207 dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; 1208 dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; 1209 dss.dispc_clk_source = DSS_CLK_SRC_FCK; 1210 dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; 1211 dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; 1212 1213 rev = dss_read_reg(DSS_REVISION); 1214 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 1215 1216 dss_runtime_put(); 1217 1218 r = component_bind_all(&pdev->dev, NULL); 1219 if (r) 1220 goto err_component; 1221 1222 dss_debugfs_create_file("dss", dss_dump_regs); 1223 1224 pm_set_vt_switch(0); 1225 1226 omapdss_gather_components(dev); 1227 omapdss_set_is_initialized(true); 1228 1229 return 0; 1230 1231 err_component: 1232 err_runtime_get: 1233 pm_runtime_disable(&pdev->dev); 1234 dss_uninit_ports(pdev); 1235 err_init_ports: 1236 if (dss.video1_pll) 1237 dss_video_pll_uninit(dss.video1_pll); 1238 1239 if (dss.video2_pll) 1240 dss_video_pll_uninit(dss.video2_pll); 1241 err_pll_init: 1242 err_setup_clocks: 1243 dss_put_clocks(); 1244 return r; 1245 } 1246 1247 static void dss_unbind(struct device *dev) 1248 { 1249 struct platform_device *pdev = to_platform_device(dev); 1250 1251 omapdss_set_is_initialized(false); 1252 1253 component_unbind_all(&pdev->dev, NULL); 1254 1255 if (dss.video1_pll) 1256 dss_video_pll_uninit(dss.video1_pll); 1257 1258 if (dss.video2_pll) 1259 dss_video_pll_uninit(dss.video2_pll); 1260 1261 dss_uninit_ports(pdev); 1262 1263 pm_runtime_disable(&pdev->dev); 1264 1265 dss_put_clocks(); 1266 } 1267 1268 static const struct component_master_ops dss_component_ops = { 1269 .bind = dss_bind, 1270 .unbind = dss_unbind, 1271 }; 1272 1273 static int dss_component_compare(struct device *dev, void *data) 1274 { 1275 struct device *child = data; 1276 return dev == child; 1277 } 1278 1279 static int dss_add_child_component(struct device *dev, void *data) 1280 { 1281 struct component_match **match = data; 1282 1283 /* 1284 * HACK 1285 * We don't have a working driver for rfbi, so skip it here always. 1286 * Otherwise dss will never get probed successfully, as it will wait 1287 * for rfbi to get probed. 1288 */ 1289 if (strstr(dev_name(dev), "rfbi")) 1290 return 0; 1291 1292 component_match_add(dev->parent, match, dss_component_compare, dev); 1293 1294 return 0; 1295 } 1296 1297 static int dss_probe(struct platform_device *pdev) 1298 { 1299 struct component_match *match = NULL; 1300 int r; 1301 1302 /* add all the child devices as components */ 1303 device_for_each_child(&pdev->dev, &match, dss_add_child_component); 1304 1305 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); 1306 if (r) 1307 return r; 1308 1309 return 0; 1310 } 1311 1312 static int dss_remove(struct platform_device *pdev) 1313 { 1314 component_master_del(&pdev->dev, &dss_component_ops); 1315 return 0; 1316 } 1317 1318 static int dss_runtime_suspend(struct device *dev) 1319 { 1320 dss_save_context(); 1321 dss_set_min_bus_tput(dev, 0); 1322 1323 pinctrl_pm_select_sleep_state(dev); 1324 1325 return 0; 1326 } 1327 1328 static int dss_runtime_resume(struct device *dev) 1329 { 1330 int r; 1331 1332 pinctrl_pm_select_default_state(dev); 1333 1334 /* 1335 * Set an arbitrarily high tput request to ensure OPP100. 1336 * What we should really do is to make a request to stay in OPP100, 1337 * without any tput requirements, but that is not currently possible 1338 * via the PM layer. 1339 */ 1340 1341 r = dss_set_min_bus_tput(dev, 1000000000); 1342 if (r) 1343 return r; 1344 1345 dss_restore_context(); 1346 return 0; 1347 } 1348 1349 static const struct dev_pm_ops dss_pm_ops = { 1350 .runtime_suspend = dss_runtime_suspend, 1351 .runtime_resume = dss_runtime_resume, 1352 }; 1353 1354 static const struct of_device_id dss_of_match[] = { 1355 { .compatible = "ti,omap2-dss", }, 1356 { .compatible = "ti,omap3-dss", }, 1357 { .compatible = "ti,omap4-dss", }, 1358 { .compatible = "ti,omap5-dss", }, 1359 { .compatible = "ti,dra7-dss", }, 1360 {}, 1361 }; 1362 1363 MODULE_DEVICE_TABLE(of, dss_of_match); 1364 1365 static struct platform_driver omap_dsshw_driver = { 1366 .probe = dss_probe, 1367 .remove = dss_remove, 1368 .driver = { 1369 .name = "omapdss_dss", 1370 .pm = &dss_pm_ops, 1371 .of_match_table = dss_of_match, 1372 .suppress_bind_attrs = true, 1373 }, 1374 }; 1375 1376 int __init dss_init_platform_driver(void) 1377 { 1378 return platform_driver_register(&omap_dsshw_driver); 1379 } 1380 1381 void dss_uninit_platform_driver(void) 1382 { 1383 platform_driver_unregister(&omap_dsshw_driver); 1384 } 1385