1 /* 2 * linux/drivers/video/omap2/dss/dsi.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "DSI" 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/device.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/mutex.h> 30 #include <linux/module.h> 31 #include <linux/semaphore.h> 32 #include <linux/seq_file.h> 33 #include <linux/platform_device.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/wait.h> 36 #include <linux/workqueue.h> 37 #include <linux/sched.h> 38 #include <linux/slab.h> 39 #include <linux/debugfs.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/of_platform.h> 43 #include <linux/component.h> 44 45 #include <video/mipi_display.h> 46 47 #include "omapdss.h" 48 #include "dss.h" 49 #include "dss_features.h" 50 51 #define DSI_CATCH_MISSING_TE 52 53 struct dsi_reg { u16 module; u16 idx; }; 54 55 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 56 57 /* DSI Protocol Engine */ 58 59 #define DSI_PROTO 0 60 #define DSI_PROTO_SZ 0x200 61 62 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 63 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 64 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 65 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 66 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 67 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 68 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 69 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 70 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 71 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 72 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 73 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 74 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 75 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 76 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 77 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 78 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 79 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 80 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 81 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 82 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 83 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 84 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 85 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 86 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 87 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 88 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 89 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 90 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 91 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 92 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 93 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 94 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 95 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 96 97 /* DSIPHY_SCP */ 98 99 #define DSI_PHY 1 100 #define DSI_PHY_OFFSET 0x200 101 #define DSI_PHY_SZ 0x40 102 103 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 104 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 105 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 106 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 107 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 108 109 /* DSI_PLL_CTRL_SCP */ 110 111 #define DSI_PLL 2 112 #define DSI_PLL_OFFSET 0x300 113 #define DSI_PLL_SZ 0x20 114 115 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 116 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 117 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 118 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 119 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 120 121 #define REG_GET(dsidev, idx, start, end) \ 122 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 123 124 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ 125 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 126 127 /* Global interrupts */ 128 #define DSI_IRQ_VC0 (1 << 0) 129 #define DSI_IRQ_VC1 (1 << 1) 130 #define DSI_IRQ_VC2 (1 << 2) 131 #define DSI_IRQ_VC3 (1 << 3) 132 #define DSI_IRQ_WAKEUP (1 << 4) 133 #define DSI_IRQ_RESYNC (1 << 5) 134 #define DSI_IRQ_PLL_LOCK (1 << 7) 135 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 136 #define DSI_IRQ_PLL_RECALL (1 << 9) 137 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 138 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 139 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 140 #define DSI_IRQ_TE_TRIGGER (1 << 16) 141 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 142 #define DSI_IRQ_SYNC_LOST (1 << 18) 143 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 144 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 145 #define DSI_IRQ_ERROR_MASK \ 146 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 147 DSI_IRQ_TA_TIMEOUT) 148 #define DSI_IRQ_CHANNEL_MASK 0xf 149 150 /* Virtual channel interrupts */ 151 #define DSI_VC_IRQ_CS (1 << 0) 152 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 153 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 154 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 155 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 156 #define DSI_VC_IRQ_BTA (1 << 5) 157 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 158 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 159 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 160 #define DSI_VC_IRQ_ERROR_MASK \ 161 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 162 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 163 DSI_VC_IRQ_FIFO_TX_UDF) 164 165 /* ComplexIO interrupts */ 166 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 167 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 168 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 169 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 170 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 171 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 172 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 173 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 174 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 175 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 176 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 177 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 178 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 179 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 180 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 181 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 182 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 183 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 184 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 185 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 186 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 187 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 188 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 189 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 190 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 191 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 192 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 193 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 194 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 195 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 198 #define DSI_CIO_IRQ_ERROR_MASK \ 199 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 200 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 201 DSI_CIO_IRQ_ERRSYNCESC5 | \ 202 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 203 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 204 DSI_CIO_IRQ_ERRESC5 | \ 205 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 206 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 207 DSI_CIO_IRQ_ERRCONTROL5 | \ 208 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 209 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 210 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 211 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 212 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 213 214 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 215 216 static int dsi_display_init_dispc(struct platform_device *dsidev, 217 enum omap_channel channel); 218 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 219 enum omap_channel channel); 220 221 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 222 223 /* DSI PLL HSDIV indices */ 224 #define HSDIV_DISPC 0 225 #define HSDIV_DSI 1 226 227 #define DSI_MAX_NR_ISRS 2 228 #define DSI_MAX_NR_LANES 5 229 230 enum dsi_lane_function { 231 DSI_LANE_UNUSED = 0, 232 DSI_LANE_CLK, 233 DSI_LANE_DATA1, 234 DSI_LANE_DATA2, 235 DSI_LANE_DATA3, 236 DSI_LANE_DATA4, 237 }; 238 239 struct dsi_lane_config { 240 enum dsi_lane_function function; 241 u8 polarity; 242 }; 243 244 struct dsi_isr_data { 245 omap_dsi_isr_t isr; 246 void *arg; 247 u32 mask; 248 }; 249 250 enum fifo_size { 251 DSI_FIFO_SIZE_0 = 0, 252 DSI_FIFO_SIZE_32 = 1, 253 DSI_FIFO_SIZE_64 = 2, 254 DSI_FIFO_SIZE_96 = 3, 255 DSI_FIFO_SIZE_128 = 4, 256 }; 257 258 enum dsi_vc_source { 259 DSI_VC_SOURCE_L4 = 0, 260 DSI_VC_SOURCE_VP, 261 }; 262 263 struct dsi_irq_stats { 264 unsigned long last_reset; 265 unsigned irq_count; 266 unsigned dsi_irqs[32]; 267 unsigned vc_irqs[4][32]; 268 unsigned cio_irqs[32]; 269 }; 270 271 struct dsi_isr_tables { 272 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 273 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 274 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 275 }; 276 277 struct dsi_clk_calc_ctx { 278 struct platform_device *dsidev; 279 struct dss_pll *pll; 280 281 /* inputs */ 282 283 const struct omap_dss_dsi_config *config; 284 285 unsigned long req_pck_min, req_pck_nom, req_pck_max; 286 287 /* outputs */ 288 289 struct dss_pll_clock_info dsi_cinfo; 290 struct dispc_clock_info dispc_cinfo; 291 292 struct videomode vm; 293 struct omap_dss_dsi_videomode_timings dsi_vm; 294 }; 295 296 struct dsi_lp_clock_info { 297 unsigned long lp_clk; 298 u16 lp_clk_div; 299 }; 300 301 struct dsi_data { 302 struct platform_device *pdev; 303 void __iomem *proto_base; 304 void __iomem *phy_base; 305 void __iomem *pll_base; 306 307 int module_id; 308 309 int irq; 310 311 bool is_enabled; 312 313 struct clk *dss_clk; 314 315 struct dispc_clock_info user_dispc_cinfo; 316 struct dss_pll_clock_info user_dsi_cinfo; 317 318 struct dsi_lp_clock_info user_lp_cinfo; 319 struct dsi_lp_clock_info current_lp_cinfo; 320 321 struct dss_pll pll; 322 323 bool vdds_dsi_enabled; 324 struct regulator *vdds_dsi_reg; 325 326 struct { 327 enum dsi_vc_source source; 328 struct omap_dss_device *dssdev; 329 enum fifo_size tx_fifo_size; 330 enum fifo_size rx_fifo_size; 331 int vc_id; 332 } vc[4]; 333 334 struct mutex lock; 335 struct semaphore bus_lock; 336 337 spinlock_t irq_lock; 338 struct dsi_isr_tables isr_tables; 339 /* space for a copy used by the interrupt handler */ 340 struct dsi_isr_tables isr_tables_copy; 341 342 int update_channel; 343 #ifdef DSI_PERF_MEASURE 344 unsigned update_bytes; 345 #endif 346 347 bool te_enabled; 348 bool ulps_enabled; 349 350 void (*framedone_callback)(int, void *); 351 void *framedone_data; 352 353 struct delayed_work framedone_timeout_work; 354 355 #ifdef DSI_CATCH_MISSING_TE 356 struct timer_list te_timer; 357 #endif 358 359 unsigned long cache_req_pck; 360 unsigned long cache_clk_freq; 361 struct dss_pll_clock_info cache_cinfo; 362 363 u32 errors; 364 spinlock_t errors_lock; 365 #ifdef DSI_PERF_MEASURE 366 ktime_t perf_setup_time; 367 ktime_t perf_start_time; 368 #endif 369 int debug_read; 370 int debug_write; 371 372 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 373 spinlock_t irq_stats_lock; 374 struct dsi_irq_stats irq_stats; 375 #endif 376 377 unsigned num_lanes_supported; 378 unsigned line_buffer_size; 379 380 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 381 unsigned num_lanes_used; 382 383 unsigned scp_clk_refcount; 384 385 struct dss_lcd_mgr_config mgr_config; 386 struct videomode vm; 387 enum omap_dss_dsi_pixel_format pix_fmt; 388 enum omap_dss_dsi_mode mode; 389 struct omap_dss_dsi_videomode_timings vm_timings; 390 391 struct omap_dss_device output; 392 }; 393 394 struct dsi_packet_sent_handler_data { 395 struct platform_device *dsidev; 396 struct completion *completion; 397 }; 398 399 struct dsi_module_id_data { 400 u32 address; 401 int id; 402 }; 403 404 static const struct of_device_id dsi_of_match[]; 405 406 #ifdef DSI_PERF_MEASURE 407 static bool dsi_perf; 408 module_param(dsi_perf, bool, 0644); 409 #endif 410 411 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 412 { 413 return dev_get_drvdata(&dsidev->dev); 414 } 415 416 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 417 { 418 return to_platform_device(dssdev->dev); 419 } 420 421 static struct platform_device *dsi_get_dsidev_from_id(int module) 422 { 423 struct omap_dss_device *out; 424 enum omap_dss_output_id id; 425 426 switch (module) { 427 case 0: 428 id = OMAP_DSS_OUTPUT_DSI1; 429 break; 430 case 1: 431 id = OMAP_DSS_OUTPUT_DSI2; 432 break; 433 default: 434 return NULL; 435 } 436 437 out = omap_dss_get_output(id); 438 439 return out ? to_platform_device(out->dev) : NULL; 440 } 441 442 static inline void dsi_write_reg(struct platform_device *dsidev, 443 const struct dsi_reg idx, u32 val) 444 { 445 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 446 void __iomem *base; 447 448 switch(idx.module) { 449 case DSI_PROTO: base = dsi->proto_base; break; 450 case DSI_PHY: base = dsi->phy_base; break; 451 case DSI_PLL: base = dsi->pll_base; break; 452 default: return; 453 } 454 455 __raw_writel(val, base + idx.idx); 456 } 457 458 static inline u32 dsi_read_reg(struct platform_device *dsidev, 459 const struct dsi_reg idx) 460 { 461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 462 void __iomem *base; 463 464 switch(idx.module) { 465 case DSI_PROTO: base = dsi->proto_base; break; 466 case DSI_PHY: base = dsi->phy_base; break; 467 case DSI_PLL: base = dsi->pll_base; break; 468 default: return 0; 469 } 470 471 return __raw_readl(base + idx.idx); 472 } 473 474 static void dsi_bus_lock(struct omap_dss_device *dssdev) 475 { 476 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 478 479 down(&dsi->bus_lock); 480 } 481 482 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 483 { 484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 486 487 up(&dsi->bus_lock); 488 } 489 490 static bool dsi_bus_is_locked(struct platform_device *dsidev) 491 { 492 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 493 494 return dsi->bus_lock.count == 0; 495 } 496 497 static void dsi_completion_handler(void *data, u32 mask) 498 { 499 complete((struct completion *)data); 500 } 501 502 static inline int wait_for_bit_change(struct platform_device *dsidev, 503 const struct dsi_reg idx, int bitnum, int value) 504 { 505 unsigned long timeout; 506 ktime_t wait; 507 int t; 508 509 /* first busyloop to see if the bit changes right away */ 510 t = 100; 511 while (t-- > 0) { 512 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 513 return value; 514 } 515 516 /* then loop for 500ms, sleeping for 1ms in between */ 517 timeout = jiffies + msecs_to_jiffies(500); 518 while (time_before(jiffies, timeout)) { 519 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 520 return value; 521 522 wait = ns_to_ktime(1000 * 1000); 523 set_current_state(TASK_UNINTERRUPTIBLE); 524 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 525 } 526 527 return !value; 528 } 529 530 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 531 { 532 switch (fmt) { 533 case OMAP_DSS_DSI_FMT_RGB888: 534 case OMAP_DSS_DSI_FMT_RGB666: 535 return 24; 536 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 537 return 18; 538 case OMAP_DSS_DSI_FMT_RGB565: 539 return 16; 540 default: 541 BUG(); 542 return 0; 543 } 544 } 545 546 #ifdef DSI_PERF_MEASURE 547 static void dsi_perf_mark_setup(struct platform_device *dsidev) 548 { 549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 550 dsi->perf_setup_time = ktime_get(); 551 } 552 553 static void dsi_perf_mark_start(struct platform_device *dsidev) 554 { 555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 556 dsi->perf_start_time = ktime_get(); 557 } 558 559 static void dsi_perf_show(struct platform_device *dsidev, const char *name) 560 { 561 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 562 ktime_t t, setup_time, trans_time; 563 u32 total_bytes; 564 u32 setup_us, trans_us, total_us; 565 566 if (!dsi_perf) 567 return; 568 569 t = ktime_get(); 570 571 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 572 setup_us = (u32)ktime_to_us(setup_time); 573 if (setup_us == 0) 574 setup_us = 1; 575 576 trans_time = ktime_sub(t, dsi->perf_start_time); 577 trans_us = (u32)ktime_to_us(trans_time); 578 if (trans_us == 0) 579 trans_us = 1; 580 581 total_us = setup_us + trans_us; 582 583 total_bytes = dsi->update_bytes; 584 585 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 586 name, 587 setup_us, 588 trans_us, 589 total_us, 590 1000 * 1000 / total_us, 591 total_bytes, 592 total_bytes * 1000 / total_us); 593 } 594 #else 595 static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 596 { 597 } 598 599 static inline void dsi_perf_mark_start(struct platform_device *dsidev) 600 { 601 } 602 603 static inline void dsi_perf_show(struct platform_device *dsidev, 604 const char *name) 605 { 606 } 607 #endif 608 609 static int verbose_irq; 610 611 static void print_irq_status(u32 status) 612 { 613 if (status == 0) 614 return; 615 616 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 617 return; 618 619 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 620 621 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 622 status, 623 verbose_irq ? PIS(VC0) : "", 624 verbose_irq ? PIS(VC1) : "", 625 verbose_irq ? PIS(VC2) : "", 626 verbose_irq ? PIS(VC3) : "", 627 PIS(WAKEUP), 628 PIS(RESYNC), 629 PIS(PLL_LOCK), 630 PIS(PLL_UNLOCK), 631 PIS(PLL_RECALL), 632 PIS(COMPLEXIO_ERR), 633 PIS(HS_TX_TIMEOUT), 634 PIS(LP_RX_TIMEOUT), 635 PIS(TE_TRIGGER), 636 PIS(ACK_TRIGGER), 637 PIS(SYNC_LOST), 638 PIS(LDO_POWER_GOOD), 639 PIS(TA_TIMEOUT)); 640 #undef PIS 641 } 642 643 static void print_irq_status_vc(int channel, u32 status) 644 { 645 if (status == 0) 646 return; 647 648 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 649 return; 650 651 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 652 653 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 654 channel, 655 status, 656 PIS(CS), 657 PIS(ECC_CORR), 658 PIS(ECC_NO_CORR), 659 verbose_irq ? PIS(PACKET_SENT) : "", 660 PIS(BTA), 661 PIS(FIFO_TX_OVF), 662 PIS(FIFO_RX_OVF), 663 PIS(FIFO_TX_UDF), 664 PIS(PP_BUSY_CHANGE)); 665 #undef PIS 666 } 667 668 static void print_irq_status_cio(u32 status) 669 { 670 if (status == 0) 671 return; 672 673 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 674 675 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 676 status, 677 PIS(ERRSYNCESC1), 678 PIS(ERRSYNCESC2), 679 PIS(ERRSYNCESC3), 680 PIS(ERRESC1), 681 PIS(ERRESC2), 682 PIS(ERRESC3), 683 PIS(ERRCONTROL1), 684 PIS(ERRCONTROL2), 685 PIS(ERRCONTROL3), 686 PIS(STATEULPS1), 687 PIS(STATEULPS2), 688 PIS(STATEULPS3), 689 PIS(ERRCONTENTIONLP0_1), 690 PIS(ERRCONTENTIONLP1_1), 691 PIS(ERRCONTENTIONLP0_2), 692 PIS(ERRCONTENTIONLP1_2), 693 PIS(ERRCONTENTIONLP0_3), 694 PIS(ERRCONTENTIONLP1_3), 695 PIS(ULPSACTIVENOT_ALL0), 696 PIS(ULPSACTIVENOT_ALL1)); 697 #undef PIS 698 } 699 700 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 701 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 702 u32 *vcstatus, u32 ciostatus) 703 { 704 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 705 int i; 706 707 spin_lock(&dsi->irq_stats_lock); 708 709 dsi->irq_stats.irq_count++; 710 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 711 712 for (i = 0; i < 4; ++i) 713 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 714 715 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 716 717 spin_unlock(&dsi->irq_stats_lock); 718 } 719 #else 720 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 721 #endif 722 723 static int debug_irq; 724 725 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 726 u32 *vcstatus, u32 ciostatus) 727 { 728 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 729 int i; 730 731 if (irqstatus & DSI_IRQ_ERROR_MASK) { 732 DSSERR("DSI error, irqstatus %x\n", irqstatus); 733 print_irq_status(irqstatus); 734 spin_lock(&dsi->errors_lock); 735 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 736 spin_unlock(&dsi->errors_lock); 737 } else if (debug_irq) { 738 print_irq_status(irqstatus); 739 } 740 741 for (i = 0; i < 4; ++i) { 742 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 743 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 744 i, vcstatus[i]); 745 print_irq_status_vc(i, vcstatus[i]); 746 } else if (debug_irq) { 747 print_irq_status_vc(i, vcstatus[i]); 748 } 749 } 750 751 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 752 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 753 print_irq_status_cio(ciostatus); 754 } else if (debug_irq) { 755 print_irq_status_cio(ciostatus); 756 } 757 } 758 759 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 760 unsigned isr_array_size, u32 irqstatus) 761 { 762 struct dsi_isr_data *isr_data; 763 int i; 764 765 for (i = 0; i < isr_array_size; i++) { 766 isr_data = &isr_array[i]; 767 if (isr_data->isr && isr_data->mask & irqstatus) 768 isr_data->isr(isr_data->arg, irqstatus); 769 } 770 } 771 772 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 773 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 774 { 775 int i; 776 777 dsi_call_isrs(isr_tables->isr_table, 778 ARRAY_SIZE(isr_tables->isr_table), 779 irqstatus); 780 781 for (i = 0; i < 4; ++i) { 782 if (vcstatus[i] == 0) 783 continue; 784 dsi_call_isrs(isr_tables->isr_table_vc[i], 785 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 786 vcstatus[i]); 787 } 788 789 if (ciostatus != 0) 790 dsi_call_isrs(isr_tables->isr_table_cio, 791 ARRAY_SIZE(isr_tables->isr_table_cio), 792 ciostatus); 793 } 794 795 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 796 { 797 struct platform_device *dsidev; 798 struct dsi_data *dsi; 799 u32 irqstatus, vcstatus[4], ciostatus; 800 int i; 801 802 dsidev = (struct platform_device *) arg; 803 dsi = dsi_get_dsidrv_data(dsidev); 804 805 if (!dsi->is_enabled) 806 return IRQ_NONE; 807 808 spin_lock(&dsi->irq_lock); 809 810 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 811 812 /* IRQ is not for us */ 813 if (!irqstatus) { 814 spin_unlock(&dsi->irq_lock); 815 return IRQ_NONE; 816 } 817 818 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 819 /* flush posted write */ 820 dsi_read_reg(dsidev, DSI_IRQSTATUS); 821 822 for (i = 0; i < 4; ++i) { 823 if ((irqstatus & (1 << i)) == 0) { 824 vcstatus[i] = 0; 825 continue; 826 } 827 828 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 829 830 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 831 /* flush posted write */ 832 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 833 } 834 835 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 836 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 837 838 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 839 /* flush posted write */ 840 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 841 } else { 842 ciostatus = 0; 843 } 844 845 #ifdef DSI_CATCH_MISSING_TE 846 if (irqstatus & DSI_IRQ_TE_TRIGGER) 847 del_timer(&dsi->te_timer); 848 #endif 849 850 /* make a copy and unlock, so that isrs can unregister 851 * themselves */ 852 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 853 sizeof(dsi->isr_tables)); 854 855 spin_unlock(&dsi->irq_lock); 856 857 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 858 859 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 860 861 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 862 863 return IRQ_HANDLED; 864 } 865 866 /* dsi->irq_lock has to be locked by the caller */ 867 static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 868 struct dsi_isr_data *isr_array, 869 unsigned isr_array_size, u32 default_mask, 870 const struct dsi_reg enable_reg, 871 const struct dsi_reg status_reg) 872 { 873 struct dsi_isr_data *isr_data; 874 u32 mask; 875 u32 old_mask; 876 int i; 877 878 mask = default_mask; 879 880 for (i = 0; i < isr_array_size; i++) { 881 isr_data = &isr_array[i]; 882 883 if (isr_data->isr == NULL) 884 continue; 885 886 mask |= isr_data->mask; 887 } 888 889 old_mask = dsi_read_reg(dsidev, enable_reg); 890 /* clear the irqstatus for newly enabled irqs */ 891 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 892 dsi_write_reg(dsidev, enable_reg, mask); 893 894 /* flush posted writes */ 895 dsi_read_reg(dsidev, enable_reg); 896 dsi_read_reg(dsidev, status_reg); 897 } 898 899 /* dsi->irq_lock has to be locked by the caller */ 900 static void _omap_dsi_set_irqs(struct platform_device *dsidev) 901 { 902 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 903 u32 mask = DSI_IRQ_ERROR_MASK; 904 #ifdef DSI_CATCH_MISSING_TE 905 mask |= DSI_IRQ_TE_TRIGGER; 906 #endif 907 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 908 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 909 DSI_IRQENABLE, DSI_IRQSTATUS); 910 } 911 912 /* dsi->irq_lock has to be locked by the caller */ 913 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 914 { 915 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 916 917 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], 918 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 919 DSI_VC_IRQ_ERROR_MASK, 920 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 921 } 922 923 /* dsi->irq_lock has to be locked by the caller */ 924 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 925 { 926 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 927 928 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, 929 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 930 DSI_CIO_IRQ_ERROR_MASK, 931 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 932 } 933 934 static void _dsi_initialize_irq(struct platform_device *dsidev) 935 { 936 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 937 unsigned long flags; 938 int vc; 939 940 spin_lock_irqsave(&dsi->irq_lock, flags); 941 942 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 943 944 _omap_dsi_set_irqs(dsidev); 945 for (vc = 0; vc < 4; ++vc) 946 _omap_dsi_set_irqs_vc(dsidev, vc); 947 _omap_dsi_set_irqs_cio(dsidev); 948 949 spin_unlock_irqrestore(&dsi->irq_lock, flags); 950 } 951 952 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 953 struct dsi_isr_data *isr_array, unsigned isr_array_size) 954 { 955 struct dsi_isr_data *isr_data; 956 int free_idx; 957 int i; 958 959 BUG_ON(isr == NULL); 960 961 /* check for duplicate entry and find a free slot */ 962 free_idx = -1; 963 for (i = 0; i < isr_array_size; i++) { 964 isr_data = &isr_array[i]; 965 966 if (isr_data->isr == isr && isr_data->arg == arg && 967 isr_data->mask == mask) { 968 return -EINVAL; 969 } 970 971 if (isr_data->isr == NULL && free_idx == -1) 972 free_idx = i; 973 } 974 975 if (free_idx == -1) 976 return -EBUSY; 977 978 isr_data = &isr_array[free_idx]; 979 isr_data->isr = isr; 980 isr_data->arg = arg; 981 isr_data->mask = mask; 982 983 return 0; 984 } 985 986 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 987 struct dsi_isr_data *isr_array, unsigned isr_array_size) 988 { 989 struct dsi_isr_data *isr_data; 990 int i; 991 992 for (i = 0; i < isr_array_size; i++) { 993 isr_data = &isr_array[i]; 994 if (isr_data->isr != isr || isr_data->arg != arg || 995 isr_data->mask != mask) 996 continue; 997 998 isr_data->isr = NULL; 999 isr_data->arg = NULL; 1000 isr_data->mask = 0; 1001 1002 return 0; 1003 } 1004 1005 return -EINVAL; 1006 } 1007 1008 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 1009 void *arg, u32 mask) 1010 { 1011 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1012 unsigned long flags; 1013 int r; 1014 1015 spin_lock_irqsave(&dsi->irq_lock, flags); 1016 1017 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1018 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1019 1020 if (r == 0) 1021 _omap_dsi_set_irqs(dsidev); 1022 1023 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1024 1025 return r; 1026 } 1027 1028 static int dsi_unregister_isr(struct platform_device *dsidev, 1029 omap_dsi_isr_t isr, void *arg, u32 mask) 1030 { 1031 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1032 unsigned long flags; 1033 int r; 1034 1035 spin_lock_irqsave(&dsi->irq_lock, flags); 1036 1037 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1038 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1039 1040 if (r == 0) 1041 _omap_dsi_set_irqs(dsidev); 1042 1043 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1044 1045 return r; 1046 } 1047 1048 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1049 omap_dsi_isr_t isr, void *arg, u32 mask) 1050 { 1051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1052 unsigned long flags; 1053 int r; 1054 1055 spin_lock_irqsave(&dsi->irq_lock, flags); 1056 1057 r = _dsi_register_isr(isr, arg, mask, 1058 dsi->isr_tables.isr_table_vc[channel], 1059 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1060 1061 if (r == 0) 1062 _omap_dsi_set_irqs_vc(dsidev, channel); 1063 1064 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1065 1066 return r; 1067 } 1068 1069 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1070 omap_dsi_isr_t isr, void *arg, u32 mask) 1071 { 1072 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1073 unsigned long flags; 1074 int r; 1075 1076 spin_lock_irqsave(&dsi->irq_lock, flags); 1077 1078 r = _dsi_unregister_isr(isr, arg, mask, 1079 dsi->isr_tables.isr_table_vc[channel], 1080 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1081 1082 if (r == 0) 1083 _omap_dsi_set_irqs_vc(dsidev, channel); 1084 1085 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1086 1087 return r; 1088 } 1089 1090 static int dsi_register_isr_cio(struct platform_device *dsidev, 1091 omap_dsi_isr_t isr, void *arg, u32 mask) 1092 { 1093 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1094 unsigned long flags; 1095 int r; 1096 1097 spin_lock_irqsave(&dsi->irq_lock, flags); 1098 1099 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1100 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1101 1102 if (r == 0) 1103 _omap_dsi_set_irqs_cio(dsidev); 1104 1105 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1106 1107 return r; 1108 } 1109 1110 static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1111 omap_dsi_isr_t isr, void *arg, u32 mask) 1112 { 1113 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1114 unsigned long flags; 1115 int r; 1116 1117 spin_lock_irqsave(&dsi->irq_lock, flags); 1118 1119 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1120 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1121 1122 if (r == 0) 1123 _omap_dsi_set_irqs_cio(dsidev); 1124 1125 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1126 1127 return r; 1128 } 1129 1130 static u32 dsi_get_errors(struct platform_device *dsidev) 1131 { 1132 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1133 unsigned long flags; 1134 u32 e; 1135 spin_lock_irqsave(&dsi->errors_lock, flags); 1136 e = dsi->errors; 1137 dsi->errors = 0; 1138 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1139 return e; 1140 } 1141 1142 static int dsi_runtime_get(struct platform_device *dsidev) 1143 { 1144 int r; 1145 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1146 1147 DSSDBG("dsi_runtime_get\n"); 1148 1149 r = pm_runtime_get_sync(&dsi->pdev->dev); 1150 WARN_ON(r < 0); 1151 return r < 0 ? r : 0; 1152 } 1153 1154 static void dsi_runtime_put(struct platform_device *dsidev) 1155 { 1156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1157 int r; 1158 1159 DSSDBG("dsi_runtime_put\n"); 1160 1161 r = pm_runtime_put_sync(&dsi->pdev->dev); 1162 WARN_ON(r < 0 && r != -ENOSYS); 1163 } 1164 1165 static int dsi_regulator_init(struct platform_device *dsidev) 1166 { 1167 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1168 struct regulator *vdds_dsi; 1169 1170 if (dsi->vdds_dsi_reg != NULL) 1171 return 0; 1172 1173 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1174 1175 if (IS_ERR(vdds_dsi)) { 1176 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1177 DSSERR("can't get DSI VDD regulator\n"); 1178 return PTR_ERR(vdds_dsi); 1179 } 1180 1181 dsi->vdds_dsi_reg = vdds_dsi; 1182 1183 return 0; 1184 } 1185 1186 static void _dsi_print_reset_status(struct platform_device *dsidev) 1187 { 1188 u32 l; 1189 int b0, b1, b2; 1190 1191 /* A dummy read using the SCP interface to any DSIPHY register is 1192 * required after DSIPHY reset to complete the reset of the DSI complex 1193 * I/O. */ 1194 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1195 1196 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { 1197 b0 = 28; 1198 b1 = 27; 1199 b2 = 26; 1200 } else { 1201 b0 = 24; 1202 b1 = 25; 1203 b2 = 26; 1204 } 1205 1206 #define DSI_FLD_GET(fld, start, end)\ 1207 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1208 1209 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1210 DSI_FLD_GET(PLL_STATUS, 0, 0), 1211 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1212 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1213 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1214 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1215 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1216 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1217 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1218 1219 #undef DSI_FLD_GET 1220 } 1221 1222 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1223 { 1224 DSSDBG("dsi_if_enable(%d)\n", enable); 1225 1226 enable = enable ? 1 : 0; 1227 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1228 1229 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1230 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1231 return -EIO; 1232 } 1233 1234 return 0; 1235 } 1236 1237 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1238 { 1239 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1240 1241 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1242 } 1243 1244 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1245 { 1246 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1247 1248 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1249 } 1250 1251 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1252 { 1253 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1254 1255 return dsi->pll.cinfo.clkdco / 16; 1256 } 1257 1258 static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1259 { 1260 unsigned long r; 1261 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1262 1263 if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) { 1264 /* DSI FCLK source is DSS_CLK_FCK */ 1265 r = clk_get_rate(dsi->dss_clk); 1266 } else { 1267 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1268 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1269 } 1270 1271 return r; 1272 } 1273 1274 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1275 unsigned long lp_clk_min, unsigned long lp_clk_max, 1276 struct dsi_lp_clock_info *lp_cinfo) 1277 { 1278 unsigned lp_clk_div; 1279 unsigned long lp_clk; 1280 1281 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1282 lp_clk = dsi_fclk / 2 / lp_clk_div; 1283 1284 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1285 return -EINVAL; 1286 1287 lp_cinfo->lp_clk_div = lp_clk_div; 1288 lp_cinfo->lp_clk = lp_clk; 1289 1290 return 0; 1291 } 1292 1293 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1294 { 1295 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1296 unsigned long dsi_fclk; 1297 unsigned lp_clk_div; 1298 unsigned long lp_clk; 1299 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); 1300 1301 1302 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1303 1304 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1305 return -EINVAL; 1306 1307 dsi_fclk = dsi_fclk_rate(dsidev); 1308 1309 lp_clk = dsi_fclk / 2 / lp_clk_div; 1310 1311 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1312 dsi->current_lp_cinfo.lp_clk = lp_clk; 1313 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1314 1315 /* LP_CLK_DIVISOR */ 1316 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1317 1318 /* LP_RX_SYNCHRO_ENABLE */ 1319 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1320 1321 return 0; 1322 } 1323 1324 static void dsi_enable_scp_clk(struct platform_device *dsidev) 1325 { 1326 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1327 1328 if (dsi->scp_clk_refcount++ == 0) 1329 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1330 } 1331 1332 static void dsi_disable_scp_clk(struct platform_device *dsidev) 1333 { 1334 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1335 1336 WARN_ON(dsi->scp_clk_refcount == 0); 1337 if (--dsi->scp_clk_refcount == 0) 1338 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1339 } 1340 1341 enum dsi_pll_power_state { 1342 DSI_PLL_POWER_OFF = 0x0, 1343 DSI_PLL_POWER_ON_HSCLK = 0x1, 1344 DSI_PLL_POWER_ON_ALL = 0x2, 1345 DSI_PLL_POWER_ON_DIV = 0x3, 1346 }; 1347 1348 static int dsi_pll_power(struct platform_device *dsidev, 1349 enum dsi_pll_power_state state) 1350 { 1351 int t = 0; 1352 1353 /* DSI-PLL power command 0x3 is not working */ 1354 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && 1355 state == DSI_PLL_POWER_ON_DIV) 1356 state = DSI_PLL_POWER_ON_ALL; 1357 1358 /* PLL_PWR_CMD */ 1359 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1360 1361 /* PLL_PWR_STATUS */ 1362 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1363 if (++t > 1000) { 1364 DSSERR("Failed to set DSI PLL power mode to %d\n", 1365 state); 1366 return -ENODEV; 1367 } 1368 udelay(1); 1369 } 1370 1371 return 0; 1372 } 1373 1374 1375 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) 1376 { 1377 unsigned long max_dsi_fck; 1378 1379 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); 1380 1381 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1382 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1383 } 1384 1385 static int dsi_pll_enable(struct dss_pll *pll) 1386 { 1387 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1388 struct platform_device *dsidev = dsi->pdev; 1389 int r = 0; 1390 1391 DSSDBG("PLL init\n"); 1392 1393 r = dsi_regulator_init(dsidev); 1394 if (r) 1395 return r; 1396 1397 r = dsi_runtime_get(dsidev); 1398 if (r) 1399 return r; 1400 1401 /* 1402 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1403 */ 1404 dsi_enable_scp_clk(dsidev); 1405 1406 if (!dsi->vdds_dsi_enabled) { 1407 r = regulator_enable(dsi->vdds_dsi_reg); 1408 if (r) 1409 goto err0; 1410 dsi->vdds_dsi_enabled = true; 1411 } 1412 1413 /* XXX PLL does not come out of reset without this... */ 1414 dispc_pck_free_enable(1); 1415 1416 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1417 DSSERR("PLL not coming out of reset.\n"); 1418 r = -ENODEV; 1419 dispc_pck_free_enable(0); 1420 goto err1; 1421 } 1422 1423 /* XXX ... but if left on, we get problems when planes do not 1424 * fill the whole display. No idea about this */ 1425 dispc_pck_free_enable(0); 1426 1427 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1428 1429 if (r) 1430 goto err1; 1431 1432 DSSDBG("PLL init done\n"); 1433 1434 return 0; 1435 err1: 1436 if (dsi->vdds_dsi_enabled) { 1437 regulator_disable(dsi->vdds_dsi_reg); 1438 dsi->vdds_dsi_enabled = false; 1439 } 1440 err0: 1441 dsi_disable_scp_clk(dsidev); 1442 dsi_runtime_put(dsidev); 1443 return r; 1444 } 1445 1446 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1447 { 1448 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1449 1450 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); 1451 if (disconnect_lanes) { 1452 WARN_ON(!dsi->vdds_dsi_enabled); 1453 regulator_disable(dsi->vdds_dsi_reg); 1454 dsi->vdds_dsi_enabled = false; 1455 } 1456 1457 dsi_disable_scp_clk(dsidev); 1458 dsi_runtime_put(dsidev); 1459 1460 DSSDBG("PLL uninit done\n"); 1461 } 1462 1463 static void dsi_pll_disable(struct dss_pll *pll) 1464 { 1465 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1466 struct platform_device *dsidev = dsi->pdev; 1467 1468 dsi_pll_uninit(dsidev, true); 1469 } 1470 1471 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1472 struct seq_file *s) 1473 { 1474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1475 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1476 enum dss_clk_source dispc_clk_src, dsi_clk_src; 1477 int dsi_module = dsi->module_id; 1478 struct dss_pll *pll = &dsi->pll; 1479 1480 dispc_clk_src = dss_get_dispc_clk_source(); 1481 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1482 1483 if (dsi_runtime_get(dsidev)) 1484 return; 1485 1486 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1487 1488 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1489 1490 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1491 1492 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1493 cinfo->clkdco, cinfo->m); 1494 1495 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1496 dss_get_clk_source_name(dsi_module == 0 ? 1497 DSS_CLK_SRC_PLL1_1 : 1498 DSS_CLK_SRC_PLL2_1), 1499 cinfo->clkout[HSDIV_DISPC], 1500 cinfo->mX[HSDIV_DISPC], 1501 dispc_clk_src == DSS_CLK_SRC_FCK ? 1502 "off" : "on"); 1503 1504 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1505 dss_get_clk_source_name(dsi_module == 0 ? 1506 DSS_CLK_SRC_PLL1_2 : 1507 DSS_CLK_SRC_PLL2_2), 1508 cinfo->clkout[HSDIV_DSI], 1509 cinfo->mX[HSDIV_DSI], 1510 dsi_clk_src == DSS_CLK_SRC_FCK ? 1511 "off" : "on"); 1512 1513 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1514 1515 seq_printf(s, "dsi fclk source = %s\n", 1516 dss_get_clk_source_name(dsi_clk_src)); 1517 1518 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1519 1520 seq_printf(s, "DDR_CLK\t\t%lu\n", 1521 cinfo->clkdco / 4); 1522 1523 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1524 1525 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1526 1527 dsi_runtime_put(dsidev); 1528 } 1529 1530 void dsi_dump_clocks(struct seq_file *s) 1531 { 1532 struct platform_device *dsidev; 1533 int i; 1534 1535 for (i = 0; i < MAX_NUM_DSI; i++) { 1536 dsidev = dsi_get_dsidev_from_id(i); 1537 if (dsidev) 1538 dsi_dump_dsidev_clocks(dsidev, s); 1539 } 1540 } 1541 1542 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1543 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1544 struct seq_file *s) 1545 { 1546 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1547 unsigned long flags; 1548 struct dsi_irq_stats stats; 1549 1550 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1551 1552 stats = dsi->irq_stats; 1553 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1554 dsi->irq_stats.last_reset = jiffies; 1555 1556 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1557 1558 seq_printf(s, "period %u ms\n", 1559 jiffies_to_msecs(jiffies - stats.last_reset)); 1560 1561 seq_printf(s, "irqs %d\n", stats.irq_count); 1562 #define PIS(x) \ 1563 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1564 1565 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1566 PIS(VC0); 1567 PIS(VC1); 1568 PIS(VC2); 1569 PIS(VC3); 1570 PIS(WAKEUP); 1571 PIS(RESYNC); 1572 PIS(PLL_LOCK); 1573 PIS(PLL_UNLOCK); 1574 PIS(PLL_RECALL); 1575 PIS(COMPLEXIO_ERR); 1576 PIS(HS_TX_TIMEOUT); 1577 PIS(LP_RX_TIMEOUT); 1578 PIS(TE_TRIGGER); 1579 PIS(ACK_TRIGGER); 1580 PIS(SYNC_LOST); 1581 PIS(LDO_POWER_GOOD); 1582 PIS(TA_TIMEOUT); 1583 #undef PIS 1584 1585 #define PIS(x) \ 1586 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1587 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1588 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1589 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1590 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1591 1592 seq_printf(s, "-- VC interrupts --\n"); 1593 PIS(CS); 1594 PIS(ECC_CORR); 1595 PIS(PACKET_SENT); 1596 PIS(FIFO_TX_OVF); 1597 PIS(FIFO_RX_OVF); 1598 PIS(BTA); 1599 PIS(ECC_NO_CORR); 1600 PIS(FIFO_TX_UDF); 1601 PIS(PP_BUSY_CHANGE); 1602 #undef PIS 1603 1604 #define PIS(x) \ 1605 seq_printf(s, "%-20s %10d\n", #x, \ 1606 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1607 1608 seq_printf(s, "-- CIO interrupts --\n"); 1609 PIS(ERRSYNCESC1); 1610 PIS(ERRSYNCESC2); 1611 PIS(ERRSYNCESC3); 1612 PIS(ERRESC1); 1613 PIS(ERRESC2); 1614 PIS(ERRESC3); 1615 PIS(ERRCONTROL1); 1616 PIS(ERRCONTROL2); 1617 PIS(ERRCONTROL3); 1618 PIS(STATEULPS1); 1619 PIS(STATEULPS2); 1620 PIS(STATEULPS3); 1621 PIS(ERRCONTENTIONLP0_1); 1622 PIS(ERRCONTENTIONLP1_1); 1623 PIS(ERRCONTENTIONLP0_2); 1624 PIS(ERRCONTENTIONLP1_2); 1625 PIS(ERRCONTENTIONLP0_3); 1626 PIS(ERRCONTENTIONLP1_3); 1627 PIS(ULPSACTIVENOT_ALL0); 1628 PIS(ULPSACTIVENOT_ALL1); 1629 #undef PIS 1630 } 1631 1632 static void dsi1_dump_irqs(struct seq_file *s) 1633 { 1634 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1635 1636 dsi_dump_dsidev_irqs(dsidev, s); 1637 } 1638 1639 static void dsi2_dump_irqs(struct seq_file *s) 1640 { 1641 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1642 1643 dsi_dump_dsidev_irqs(dsidev, s); 1644 } 1645 #endif 1646 1647 static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1648 struct seq_file *s) 1649 { 1650 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1651 1652 if (dsi_runtime_get(dsidev)) 1653 return; 1654 dsi_enable_scp_clk(dsidev); 1655 1656 DUMPREG(DSI_REVISION); 1657 DUMPREG(DSI_SYSCONFIG); 1658 DUMPREG(DSI_SYSSTATUS); 1659 DUMPREG(DSI_IRQSTATUS); 1660 DUMPREG(DSI_IRQENABLE); 1661 DUMPREG(DSI_CTRL); 1662 DUMPREG(DSI_COMPLEXIO_CFG1); 1663 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1664 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1665 DUMPREG(DSI_CLK_CTRL); 1666 DUMPREG(DSI_TIMING1); 1667 DUMPREG(DSI_TIMING2); 1668 DUMPREG(DSI_VM_TIMING1); 1669 DUMPREG(DSI_VM_TIMING2); 1670 DUMPREG(DSI_VM_TIMING3); 1671 DUMPREG(DSI_CLK_TIMING); 1672 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1673 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1674 DUMPREG(DSI_COMPLEXIO_CFG2); 1675 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1676 DUMPREG(DSI_VM_TIMING4); 1677 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1678 DUMPREG(DSI_VM_TIMING5); 1679 DUMPREG(DSI_VM_TIMING6); 1680 DUMPREG(DSI_VM_TIMING7); 1681 DUMPREG(DSI_STOPCLK_TIMING); 1682 1683 DUMPREG(DSI_VC_CTRL(0)); 1684 DUMPREG(DSI_VC_TE(0)); 1685 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1686 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1687 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1688 DUMPREG(DSI_VC_IRQSTATUS(0)); 1689 DUMPREG(DSI_VC_IRQENABLE(0)); 1690 1691 DUMPREG(DSI_VC_CTRL(1)); 1692 DUMPREG(DSI_VC_TE(1)); 1693 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1694 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1695 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1696 DUMPREG(DSI_VC_IRQSTATUS(1)); 1697 DUMPREG(DSI_VC_IRQENABLE(1)); 1698 1699 DUMPREG(DSI_VC_CTRL(2)); 1700 DUMPREG(DSI_VC_TE(2)); 1701 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1702 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1703 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1704 DUMPREG(DSI_VC_IRQSTATUS(2)); 1705 DUMPREG(DSI_VC_IRQENABLE(2)); 1706 1707 DUMPREG(DSI_VC_CTRL(3)); 1708 DUMPREG(DSI_VC_TE(3)); 1709 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1710 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1711 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1712 DUMPREG(DSI_VC_IRQSTATUS(3)); 1713 DUMPREG(DSI_VC_IRQENABLE(3)); 1714 1715 DUMPREG(DSI_DSIPHY_CFG0); 1716 DUMPREG(DSI_DSIPHY_CFG1); 1717 DUMPREG(DSI_DSIPHY_CFG2); 1718 DUMPREG(DSI_DSIPHY_CFG5); 1719 1720 DUMPREG(DSI_PLL_CONTROL); 1721 DUMPREG(DSI_PLL_STATUS); 1722 DUMPREG(DSI_PLL_GO); 1723 DUMPREG(DSI_PLL_CONFIGURATION1); 1724 DUMPREG(DSI_PLL_CONFIGURATION2); 1725 1726 dsi_disable_scp_clk(dsidev); 1727 dsi_runtime_put(dsidev); 1728 #undef DUMPREG 1729 } 1730 1731 static void dsi1_dump_regs(struct seq_file *s) 1732 { 1733 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1734 1735 dsi_dump_dsidev_regs(dsidev, s); 1736 } 1737 1738 static void dsi2_dump_regs(struct seq_file *s) 1739 { 1740 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1741 1742 dsi_dump_dsidev_regs(dsidev, s); 1743 } 1744 1745 enum dsi_cio_power_state { 1746 DSI_COMPLEXIO_POWER_OFF = 0x0, 1747 DSI_COMPLEXIO_POWER_ON = 0x1, 1748 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1749 }; 1750 1751 static int dsi_cio_power(struct platform_device *dsidev, 1752 enum dsi_cio_power_state state) 1753 { 1754 int t = 0; 1755 1756 /* PWR_CMD */ 1757 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1758 1759 /* PWR_STATUS */ 1760 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1761 26, 25) != state) { 1762 if (++t > 1000) { 1763 DSSERR("failed to set complexio power state to " 1764 "%d\n", state); 1765 return -ENODEV; 1766 } 1767 udelay(1); 1768 } 1769 1770 return 0; 1771 } 1772 1773 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1774 { 1775 int val; 1776 1777 /* line buffer on OMAP3 is 1024 x 24bits */ 1778 /* XXX: for some reason using full buffer size causes 1779 * considerable TX slowdown with update sizes that fill the 1780 * whole buffer */ 1781 if (!dss_has_feature(FEAT_DSI_GNQ)) 1782 return 1023 * 3; 1783 1784 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1785 1786 switch (val) { 1787 case 1: 1788 return 512 * 3; /* 512x24 bits */ 1789 case 2: 1790 return 682 * 3; /* 682x24 bits */ 1791 case 3: 1792 return 853 * 3; /* 853x24 bits */ 1793 case 4: 1794 return 1024 * 3; /* 1024x24 bits */ 1795 case 5: 1796 return 1194 * 3; /* 1194x24 bits */ 1797 case 6: 1798 return 1365 * 3; /* 1365x24 bits */ 1799 case 7: 1800 return 1920 * 3; /* 1920x24 bits */ 1801 default: 1802 BUG(); 1803 return 0; 1804 } 1805 } 1806 1807 static int dsi_set_lane_config(struct platform_device *dsidev) 1808 { 1809 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1810 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1811 static const enum dsi_lane_function functions[] = { 1812 DSI_LANE_CLK, 1813 DSI_LANE_DATA1, 1814 DSI_LANE_DATA2, 1815 DSI_LANE_DATA3, 1816 DSI_LANE_DATA4, 1817 }; 1818 u32 r; 1819 int i; 1820 1821 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1822 1823 for (i = 0; i < dsi->num_lanes_used; ++i) { 1824 unsigned offset = offsets[i]; 1825 unsigned polarity, lane_number; 1826 unsigned t; 1827 1828 for (t = 0; t < dsi->num_lanes_supported; ++t) 1829 if (dsi->lanes[t].function == functions[i]) 1830 break; 1831 1832 if (t == dsi->num_lanes_supported) 1833 return -EINVAL; 1834 1835 lane_number = t; 1836 polarity = dsi->lanes[t].polarity; 1837 1838 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1839 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1840 } 1841 1842 /* clear the unused lanes */ 1843 for (; i < dsi->num_lanes_supported; ++i) { 1844 unsigned offset = offsets[i]; 1845 1846 r = FLD_MOD(r, 0, offset + 2, offset); 1847 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1848 } 1849 1850 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1851 1852 return 0; 1853 } 1854 1855 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1856 { 1857 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1858 1859 /* convert time in ns to ddr ticks, rounding up */ 1860 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1861 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1862 } 1863 1864 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1865 { 1866 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1867 1868 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1869 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1870 } 1871 1872 static void dsi_cio_timings(struct platform_device *dsidev) 1873 { 1874 u32 r; 1875 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1876 u32 tlpx_half, tclk_trail, tclk_zero; 1877 u32 tclk_prepare; 1878 1879 /* calculate timings */ 1880 1881 /* 1 * DDR_CLK = 2 * UI */ 1882 1883 /* min 40ns + 4*UI max 85ns + 6*UI */ 1884 ths_prepare = ns2ddr(dsidev, 70) + 2; 1885 1886 /* min 145ns + 10*UI */ 1887 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1888 1889 /* min max(8*UI, 60ns+4*UI) */ 1890 ths_trail = ns2ddr(dsidev, 60) + 5; 1891 1892 /* min 100ns */ 1893 ths_exit = ns2ddr(dsidev, 145); 1894 1895 /* tlpx min 50n */ 1896 tlpx_half = ns2ddr(dsidev, 25); 1897 1898 /* min 60ns */ 1899 tclk_trail = ns2ddr(dsidev, 60) + 2; 1900 1901 /* min 38ns, max 95ns */ 1902 tclk_prepare = ns2ddr(dsidev, 65); 1903 1904 /* min tclk-prepare + tclk-zero = 300ns */ 1905 tclk_zero = ns2ddr(dsidev, 260); 1906 1907 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1908 ths_prepare, ddr2ns(dsidev, ths_prepare), 1909 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1910 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1911 ths_trail, ddr2ns(dsidev, ths_trail), 1912 ths_exit, ddr2ns(dsidev, ths_exit)); 1913 1914 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1915 "tclk_zero %u (%uns)\n", 1916 tlpx_half, ddr2ns(dsidev, tlpx_half), 1917 tclk_trail, ddr2ns(dsidev, tclk_trail), 1918 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1919 DSSDBG("tclk_prepare %u (%uns)\n", 1920 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1921 1922 /* program timings */ 1923 1924 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1925 r = FLD_MOD(r, ths_prepare, 31, 24); 1926 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1927 r = FLD_MOD(r, ths_trail, 15, 8); 1928 r = FLD_MOD(r, ths_exit, 7, 0); 1929 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1930 1931 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1932 r = FLD_MOD(r, tlpx_half, 20, 16); 1933 r = FLD_MOD(r, tclk_trail, 15, 8); 1934 r = FLD_MOD(r, tclk_zero, 7, 0); 1935 1936 if (dss_has_feature(FEAT_DSI_PHY_DCC)) { 1937 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1938 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1939 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1940 } 1941 1942 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1943 1944 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1945 r = FLD_MOD(r, tclk_prepare, 7, 0); 1946 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1947 } 1948 1949 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1950 static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1951 unsigned mask_p, unsigned mask_n) 1952 { 1953 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1954 int i; 1955 u32 l; 1956 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1957 1958 l = 0; 1959 1960 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1961 unsigned p = dsi->lanes[i].polarity; 1962 1963 if (mask_p & (1 << i)) 1964 l |= 1 << (i * 2 + (p ? 0 : 1)); 1965 1966 if (mask_n & (1 << i)) 1967 l |= 1 << (i * 2 + (p ? 1 : 0)); 1968 } 1969 1970 /* 1971 * Bits in REGLPTXSCPDAT4TO0DXDY: 1972 * 17: DY0 18: DX0 1973 * 19: DY1 20: DX1 1974 * 21: DY2 22: DX2 1975 * 23: DY3 24: DX3 1976 * 25: DY4 26: DX4 1977 */ 1978 1979 /* Set the lane override configuration */ 1980 1981 /* REGLPTXSCPDAT4TO0DXDY */ 1982 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1983 1984 /* Enable lane override */ 1985 1986 /* ENLPTXSCPDAT */ 1987 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 1988 } 1989 1990 static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 1991 { 1992 /* Disable lane override */ 1993 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1994 /* Reset the lane override configuration */ 1995 /* REGLPTXSCPDAT4TO0DXDY */ 1996 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 1997 } 1998 1999 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 2000 { 2001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2002 int t, i; 2003 bool in_use[DSI_MAX_NR_LANES]; 2004 static const u8 offsets_old[] = { 28, 27, 26 }; 2005 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 2006 const u8 *offsets; 2007 2008 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) 2009 offsets = offsets_old; 2010 else 2011 offsets = offsets_new; 2012 2013 for (i = 0; i < dsi->num_lanes_supported; ++i) 2014 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 2015 2016 t = 100000; 2017 while (true) { 2018 u32 l; 2019 int ok; 2020 2021 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2022 2023 ok = 0; 2024 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2025 if (!in_use[i] || (l & (1 << offsets[i]))) 2026 ok++; 2027 } 2028 2029 if (ok == dsi->num_lanes_supported) 2030 break; 2031 2032 if (--t == 0) { 2033 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2034 if (!in_use[i] || (l & (1 << offsets[i]))) 2035 continue; 2036 2037 DSSERR("CIO TXCLKESC%d domain not coming " \ 2038 "out of reset\n", i); 2039 } 2040 return -EIO; 2041 } 2042 } 2043 2044 return 0; 2045 } 2046 2047 /* return bitmask of enabled lanes, lane0 being the lsb */ 2048 static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2049 { 2050 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2051 unsigned mask = 0; 2052 int i; 2053 2054 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2055 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 2056 mask |= 1 << i; 2057 } 2058 2059 return mask; 2060 } 2061 2062 static int dsi_cio_init(struct platform_device *dsidev) 2063 { 2064 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2065 int r; 2066 u32 l; 2067 2068 DSSDBG("DSI CIO init starts"); 2069 2070 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2071 if (r) 2072 return r; 2073 2074 dsi_enable_scp_clk(dsidev); 2075 2076 /* A dummy read using the SCP interface to any DSIPHY register is 2077 * required after DSIPHY reset to complete the reset of the DSI complex 2078 * I/O. */ 2079 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2080 2081 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2082 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2083 r = -EIO; 2084 goto err_scp_clk_dom; 2085 } 2086 2087 r = dsi_set_lane_config(dsidev); 2088 if (r) 2089 goto err_scp_clk_dom; 2090 2091 /* set TX STOP MODE timer to maximum for this operation */ 2092 l = dsi_read_reg(dsidev, DSI_TIMING1); 2093 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2094 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2095 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2096 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2097 dsi_write_reg(dsidev, DSI_TIMING1, l); 2098 2099 if (dsi->ulps_enabled) { 2100 unsigned mask_p; 2101 int i; 2102 2103 DSSDBG("manual ulps exit\n"); 2104 2105 /* ULPS is exited by Mark-1 state for 1ms, followed by 2106 * stop state. DSS HW cannot do this via the normal 2107 * ULPS exit sequence, as after reset the DSS HW thinks 2108 * that we are not in ULPS mode, and refuses to send the 2109 * sequence. So we need to send the ULPS exit sequence 2110 * manually by setting positive lines high and negative lines 2111 * low for 1ms. 2112 */ 2113 2114 mask_p = 0; 2115 2116 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2117 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2118 continue; 2119 mask_p |= 1 << i; 2120 } 2121 2122 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2123 } 2124 2125 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2126 if (r) 2127 goto err_cio_pwr; 2128 2129 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2130 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2131 r = -ENODEV; 2132 goto err_cio_pwr_dom; 2133 } 2134 2135 dsi_if_enable(dsidev, true); 2136 dsi_if_enable(dsidev, false); 2137 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2138 2139 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2140 if (r) 2141 goto err_tx_clk_esc_rst; 2142 2143 if (dsi->ulps_enabled) { 2144 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2145 ktime_t wait = ns_to_ktime(1000 * 1000); 2146 set_current_state(TASK_UNINTERRUPTIBLE); 2147 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2148 2149 /* Disable the override. The lanes should be set to Mark-11 2150 * state by the HW */ 2151 dsi_cio_disable_lane_override(dsidev); 2152 } 2153 2154 /* FORCE_TX_STOP_MODE_IO */ 2155 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2156 2157 dsi_cio_timings(dsidev); 2158 2159 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2160 /* DDR_CLK_ALWAYS_ON */ 2161 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2162 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2163 } 2164 2165 dsi->ulps_enabled = false; 2166 2167 DSSDBG("CIO init done\n"); 2168 2169 return 0; 2170 2171 err_tx_clk_esc_rst: 2172 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2173 err_cio_pwr_dom: 2174 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2175 err_cio_pwr: 2176 if (dsi->ulps_enabled) 2177 dsi_cio_disable_lane_override(dsidev); 2178 err_scp_clk_dom: 2179 dsi_disable_scp_clk(dsidev); 2180 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2181 return r; 2182 } 2183 2184 static void dsi_cio_uninit(struct platform_device *dsidev) 2185 { 2186 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2187 2188 /* DDR_CLK_ALWAYS_ON */ 2189 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2190 2191 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2192 dsi_disable_scp_clk(dsidev); 2193 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2194 } 2195 2196 static void dsi_config_tx_fifo(struct platform_device *dsidev, 2197 enum fifo_size size1, enum fifo_size size2, 2198 enum fifo_size size3, enum fifo_size size4) 2199 { 2200 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2201 u32 r = 0; 2202 int add = 0; 2203 int i; 2204 2205 dsi->vc[0].tx_fifo_size = size1; 2206 dsi->vc[1].tx_fifo_size = size2; 2207 dsi->vc[2].tx_fifo_size = size3; 2208 dsi->vc[3].tx_fifo_size = size4; 2209 2210 for (i = 0; i < 4; i++) { 2211 u8 v; 2212 int size = dsi->vc[i].tx_fifo_size; 2213 2214 if (add + size > 4) { 2215 DSSERR("Illegal FIFO configuration\n"); 2216 BUG(); 2217 return; 2218 } 2219 2220 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2221 r |= v << (8 * i); 2222 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2223 add += size; 2224 } 2225 2226 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2227 } 2228 2229 static void dsi_config_rx_fifo(struct platform_device *dsidev, 2230 enum fifo_size size1, enum fifo_size size2, 2231 enum fifo_size size3, enum fifo_size size4) 2232 { 2233 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2234 u32 r = 0; 2235 int add = 0; 2236 int i; 2237 2238 dsi->vc[0].rx_fifo_size = size1; 2239 dsi->vc[1].rx_fifo_size = size2; 2240 dsi->vc[2].rx_fifo_size = size3; 2241 dsi->vc[3].rx_fifo_size = size4; 2242 2243 for (i = 0; i < 4; i++) { 2244 u8 v; 2245 int size = dsi->vc[i].rx_fifo_size; 2246 2247 if (add + size > 4) { 2248 DSSERR("Illegal FIFO configuration\n"); 2249 BUG(); 2250 return; 2251 } 2252 2253 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2254 r |= v << (8 * i); 2255 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2256 add += size; 2257 } 2258 2259 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2260 } 2261 2262 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2263 { 2264 u32 r; 2265 2266 r = dsi_read_reg(dsidev, DSI_TIMING1); 2267 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2268 dsi_write_reg(dsidev, DSI_TIMING1, r); 2269 2270 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2271 DSSERR("TX_STOP bit not going down\n"); 2272 return -EIO; 2273 } 2274 2275 return 0; 2276 } 2277 2278 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2279 { 2280 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2281 } 2282 2283 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2284 { 2285 struct dsi_packet_sent_handler_data *vp_data = 2286 (struct dsi_packet_sent_handler_data *) data; 2287 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2288 const int channel = dsi->update_channel; 2289 u8 bit = dsi->te_enabled ? 30 : 31; 2290 2291 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2292 complete(vp_data->completion); 2293 } 2294 2295 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2296 { 2297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2298 DECLARE_COMPLETION_ONSTACK(completion); 2299 struct dsi_packet_sent_handler_data vp_data = { 2300 .dsidev = dsidev, 2301 .completion = &completion 2302 }; 2303 int r = 0; 2304 u8 bit; 2305 2306 bit = dsi->te_enabled ? 30 : 31; 2307 2308 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2309 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2310 if (r) 2311 goto err0; 2312 2313 /* Wait for completion only if TE_EN/TE_START is still set */ 2314 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2315 if (wait_for_completion_timeout(&completion, 2316 msecs_to_jiffies(10)) == 0) { 2317 DSSERR("Failed to complete previous frame transfer\n"); 2318 r = -EIO; 2319 goto err1; 2320 } 2321 } 2322 2323 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2324 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2325 2326 return 0; 2327 err1: 2328 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2329 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2330 err0: 2331 return r; 2332 } 2333 2334 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2335 { 2336 struct dsi_packet_sent_handler_data *l4_data = 2337 (struct dsi_packet_sent_handler_data *) data; 2338 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2339 const int channel = dsi->update_channel; 2340 2341 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2342 complete(l4_data->completion); 2343 } 2344 2345 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2346 { 2347 DECLARE_COMPLETION_ONSTACK(completion); 2348 struct dsi_packet_sent_handler_data l4_data = { 2349 .dsidev = dsidev, 2350 .completion = &completion 2351 }; 2352 int r = 0; 2353 2354 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2355 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2356 if (r) 2357 goto err0; 2358 2359 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2360 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2361 if (wait_for_completion_timeout(&completion, 2362 msecs_to_jiffies(10)) == 0) { 2363 DSSERR("Failed to complete previous l4 transfer\n"); 2364 r = -EIO; 2365 goto err1; 2366 } 2367 } 2368 2369 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2370 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2371 2372 return 0; 2373 err1: 2374 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2375 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2376 err0: 2377 return r; 2378 } 2379 2380 static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2381 { 2382 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2383 2384 WARN_ON(!dsi_bus_is_locked(dsidev)); 2385 2386 WARN_ON(in_interrupt()); 2387 2388 if (!dsi_vc_is_enabled(dsidev, channel)) 2389 return 0; 2390 2391 switch (dsi->vc[channel].source) { 2392 case DSI_VC_SOURCE_VP: 2393 return dsi_sync_vc_vp(dsidev, channel); 2394 case DSI_VC_SOURCE_L4: 2395 return dsi_sync_vc_l4(dsidev, channel); 2396 default: 2397 BUG(); 2398 return -EINVAL; 2399 } 2400 } 2401 2402 static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2403 bool enable) 2404 { 2405 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2406 channel, enable); 2407 2408 enable = enable ? 1 : 0; 2409 2410 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2411 2412 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2413 0, enable) != enable) { 2414 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2415 return -EIO; 2416 } 2417 2418 return 0; 2419 } 2420 2421 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2422 { 2423 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2424 u32 r; 2425 2426 DSSDBG("Initial config of virtual channel %d", channel); 2427 2428 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2429 2430 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2431 DSSERR("VC(%d) busy when trying to configure it!\n", 2432 channel); 2433 2434 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2435 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2436 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2437 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2438 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2439 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2440 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2441 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) 2442 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2443 2444 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2445 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2446 2447 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2448 2449 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2450 } 2451 2452 static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2453 enum dsi_vc_source source) 2454 { 2455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2456 2457 if (dsi->vc[channel].source == source) 2458 return 0; 2459 2460 DSSDBG("Source config of virtual channel %d", channel); 2461 2462 dsi_sync_vc(dsidev, channel); 2463 2464 dsi_vc_enable(dsidev, channel, 0); 2465 2466 /* VC_BUSY */ 2467 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2468 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2469 return -EIO; 2470 } 2471 2472 /* SOURCE, 0 = L4, 1 = video port */ 2473 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2474 2475 /* DCS_CMD_ENABLE */ 2476 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 2477 bool enable = source == DSI_VC_SOURCE_VP; 2478 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2479 } 2480 2481 dsi_vc_enable(dsidev, channel, 1); 2482 2483 dsi->vc[channel].source = source; 2484 2485 return 0; 2486 } 2487 2488 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2489 bool enable) 2490 { 2491 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2492 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2493 2494 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2495 2496 WARN_ON(!dsi_bus_is_locked(dsidev)); 2497 2498 dsi_vc_enable(dsidev, channel, 0); 2499 dsi_if_enable(dsidev, 0); 2500 2501 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2502 2503 dsi_vc_enable(dsidev, channel, 1); 2504 dsi_if_enable(dsidev, 1); 2505 2506 dsi_force_tx_stop_mode_io(dsidev); 2507 2508 /* start the DDR clock by sending a NULL packet */ 2509 if (dsi->vm_timings.ddr_clk_always_on && enable) 2510 dsi_vc_send_null(dssdev, channel); 2511 } 2512 2513 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2514 { 2515 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2516 u32 val; 2517 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2518 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2519 (val >> 0) & 0xff, 2520 (val >> 8) & 0xff, 2521 (val >> 16) & 0xff, 2522 (val >> 24) & 0xff); 2523 } 2524 } 2525 2526 static void dsi_show_rx_ack_with_err(u16 err) 2527 { 2528 DSSERR("\tACK with ERROR (%#x):\n", err); 2529 if (err & (1 << 0)) 2530 DSSERR("\t\tSoT Error\n"); 2531 if (err & (1 << 1)) 2532 DSSERR("\t\tSoT Sync Error\n"); 2533 if (err & (1 << 2)) 2534 DSSERR("\t\tEoT Sync Error\n"); 2535 if (err & (1 << 3)) 2536 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2537 if (err & (1 << 4)) 2538 DSSERR("\t\tLP Transmit Sync Error\n"); 2539 if (err & (1 << 5)) 2540 DSSERR("\t\tHS Receive Timeout Error\n"); 2541 if (err & (1 << 6)) 2542 DSSERR("\t\tFalse Control Error\n"); 2543 if (err & (1 << 7)) 2544 DSSERR("\t\t(reserved7)\n"); 2545 if (err & (1 << 8)) 2546 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2547 if (err & (1 << 9)) 2548 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2549 if (err & (1 << 10)) 2550 DSSERR("\t\tChecksum Error\n"); 2551 if (err & (1 << 11)) 2552 DSSERR("\t\tData type not recognized\n"); 2553 if (err & (1 << 12)) 2554 DSSERR("\t\tInvalid VC ID\n"); 2555 if (err & (1 << 13)) 2556 DSSERR("\t\tInvalid Transmission Length\n"); 2557 if (err & (1 << 14)) 2558 DSSERR("\t\t(reserved14)\n"); 2559 if (err & (1 << 15)) 2560 DSSERR("\t\tDSI Protocol Violation\n"); 2561 } 2562 2563 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2564 int channel) 2565 { 2566 /* RX_FIFO_NOT_EMPTY */ 2567 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2568 u32 val; 2569 u8 dt; 2570 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2571 DSSERR("\trawval %#08x\n", val); 2572 dt = FLD_GET(val, 5, 0); 2573 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2574 u16 err = FLD_GET(val, 23, 8); 2575 dsi_show_rx_ack_with_err(err); 2576 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2577 DSSERR("\tDCS short response, 1 byte: %#x\n", 2578 FLD_GET(val, 23, 8)); 2579 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2580 DSSERR("\tDCS short response, 2 byte: %#x\n", 2581 FLD_GET(val, 23, 8)); 2582 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2583 DSSERR("\tDCS long response, len %d\n", 2584 FLD_GET(val, 23, 8)); 2585 dsi_vc_flush_long_data(dsidev, channel); 2586 } else { 2587 DSSERR("\tunknown datatype 0x%02x\n", dt); 2588 } 2589 } 2590 return 0; 2591 } 2592 2593 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2594 { 2595 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2596 2597 if (dsi->debug_write || dsi->debug_read) 2598 DSSDBG("dsi_vc_send_bta %d\n", channel); 2599 2600 WARN_ON(!dsi_bus_is_locked(dsidev)); 2601 2602 /* RX_FIFO_NOT_EMPTY */ 2603 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2604 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2605 dsi_vc_flush_receive_data(dsidev, channel); 2606 } 2607 2608 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2609 2610 /* flush posted write */ 2611 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2612 2613 return 0; 2614 } 2615 2616 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2617 { 2618 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2619 DECLARE_COMPLETION_ONSTACK(completion); 2620 int r = 0; 2621 u32 err; 2622 2623 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2624 &completion, DSI_VC_IRQ_BTA); 2625 if (r) 2626 goto err0; 2627 2628 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2629 DSI_IRQ_ERROR_MASK); 2630 if (r) 2631 goto err1; 2632 2633 r = dsi_vc_send_bta(dsidev, channel); 2634 if (r) 2635 goto err2; 2636 2637 if (wait_for_completion_timeout(&completion, 2638 msecs_to_jiffies(500)) == 0) { 2639 DSSERR("Failed to receive BTA\n"); 2640 r = -EIO; 2641 goto err2; 2642 } 2643 2644 err = dsi_get_errors(dsidev); 2645 if (err) { 2646 DSSERR("Error while sending BTA: %x\n", err); 2647 r = -EIO; 2648 goto err2; 2649 } 2650 err2: 2651 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2652 DSI_IRQ_ERROR_MASK); 2653 err1: 2654 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2655 &completion, DSI_VC_IRQ_BTA); 2656 err0: 2657 return r; 2658 } 2659 2660 static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2661 int channel, u8 data_type, u16 len, u8 ecc) 2662 { 2663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2664 u32 val; 2665 u8 data_id; 2666 2667 WARN_ON(!dsi_bus_is_locked(dsidev)); 2668 2669 data_id = data_type | dsi->vc[channel].vc_id << 6; 2670 2671 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2672 FLD_VAL(ecc, 31, 24); 2673 2674 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2675 } 2676 2677 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2678 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2679 { 2680 u32 val; 2681 2682 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2683 2684 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2685 b1, b2, b3, b4, val); */ 2686 2687 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2688 } 2689 2690 static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2691 u8 data_type, u8 *data, u16 len, u8 ecc) 2692 { 2693 /*u32 val; */ 2694 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2695 int i; 2696 u8 *p; 2697 int r = 0; 2698 u8 b1, b2, b3, b4; 2699 2700 if (dsi->debug_write) 2701 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2702 2703 /* len + header */ 2704 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2705 DSSERR("unable to send long packet: packet too long.\n"); 2706 return -EINVAL; 2707 } 2708 2709 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2710 2711 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2712 2713 p = data; 2714 for (i = 0; i < len >> 2; i++) { 2715 if (dsi->debug_write) 2716 DSSDBG("\tsending full packet %d\n", i); 2717 2718 b1 = *p++; 2719 b2 = *p++; 2720 b3 = *p++; 2721 b4 = *p++; 2722 2723 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2724 } 2725 2726 i = len % 4; 2727 if (i) { 2728 b1 = 0; b2 = 0; b3 = 0; 2729 2730 if (dsi->debug_write) 2731 DSSDBG("\tsending remainder bytes %d\n", i); 2732 2733 switch (i) { 2734 case 3: 2735 b1 = *p++; 2736 b2 = *p++; 2737 b3 = *p++; 2738 break; 2739 case 2: 2740 b1 = *p++; 2741 b2 = *p++; 2742 break; 2743 case 1: 2744 b1 = *p++; 2745 break; 2746 } 2747 2748 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2749 } 2750 2751 return r; 2752 } 2753 2754 static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2755 u8 data_type, u16 data, u8 ecc) 2756 { 2757 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2758 u32 r; 2759 u8 data_id; 2760 2761 WARN_ON(!dsi_bus_is_locked(dsidev)); 2762 2763 if (dsi->debug_write) 2764 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2765 channel, 2766 data_type, data & 0xff, (data >> 8) & 0xff); 2767 2768 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2769 2770 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2771 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2772 return -EINVAL; 2773 } 2774 2775 data_id = data_type | dsi->vc[channel].vc_id << 6; 2776 2777 r = (data_id << 0) | (data << 8) | (ecc << 24); 2778 2779 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2780 2781 return 0; 2782 } 2783 2784 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2785 { 2786 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2787 2788 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, 2789 0, 0); 2790 } 2791 2792 static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2793 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2794 { 2795 int r; 2796 2797 if (len == 0) { 2798 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2799 r = dsi_vc_send_short(dsidev, channel, 2800 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2801 } else if (len == 1) { 2802 r = dsi_vc_send_short(dsidev, channel, 2803 type == DSS_DSI_CONTENT_GENERIC ? 2804 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2805 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2806 } else if (len == 2) { 2807 r = dsi_vc_send_short(dsidev, channel, 2808 type == DSS_DSI_CONTENT_GENERIC ? 2809 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2810 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2811 data[0] | (data[1] << 8), 0); 2812 } else { 2813 r = dsi_vc_send_long(dsidev, channel, 2814 type == DSS_DSI_CONTENT_GENERIC ? 2815 MIPI_DSI_GENERIC_LONG_WRITE : 2816 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2817 } 2818 2819 return r; 2820 } 2821 2822 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2823 u8 *data, int len) 2824 { 2825 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2826 2827 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2828 DSS_DSI_CONTENT_DCS); 2829 } 2830 2831 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2832 u8 *data, int len) 2833 { 2834 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2835 2836 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2837 DSS_DSI_CONTENT_GENERIC); 2838 } 2839 2840 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2841 u8 *data, int len, enum dss_dsi_content_type type) 2842 { 2843 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2844 int r; 2845 2846 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2847 if (r) 2848 goto err; 2849 2850 r = dsi_vc_send_bta_sync(dssdev, channel); 2851 if (r) 2852 goto err; 2853 2854 /* RX_FIFO_NOT_EMPTY */ 2855 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2856 DSSERR("rx fifo not empty after write, dumping data:\n"); 2857 dsi_vc_flush_receive_data(dsidev, channel); 2858 r = -EIO; 2859 goto err; 2860 } 2861 2862 return 0; 2863 err: 2864 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2865 channel, data[0], len); 2866 return r; 2867 } 2868 2869 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2870 int len) 2871 { 2872 return dsi_vc_write_common(dssdev, channel, data, len, 2873 DSS_DSI_CONTENT_DCS); 2874 } 2875 2876 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2877 int len) 2878 { 2879 return dsi_vc_write_common(dssdev, channel, data, len, 2880 DSS_DSI_CONTENT_GENERIC); 2881 } 2882 2883 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2884 int channel, u8 dcs_cmd) 2885 { 2886 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2887 int r; 2888 2889 if (dsi->debug_read) 2890 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2891 channel, dcs_cmd); 2892 2893 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2894 if (r) { 2895 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2896 " failed\n", channel, dcs_cmd); 2897 return r; 2898 } 2899 2900 return 0; 2901 } 2902 2903 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 2904 int channel, u8 *reqdata, int reqlen) 2905 { 2906 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2907 u16 data; 2908 u8 data_type; 2909 int r; 2910 2911 if (dsi->debug_read) 2912 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2913 channel, reqlen); 2914 2915 if (reqlen == 0) { 2916 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2917 data = 0; 2918 } else if (reqlen == 1) { 2919 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2920 data = reqdata[0]; 2921 } else if (reqlen == 2) { 2922 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2923 data = reqdata[0] | (reqdata[1] << 8); 2924 } else { 2925 BUG(); 2926 return -EINVAL; 2927 } 2928 2929 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 2930 if (r) { 2931 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2932 " failed\n", channel, reqlen); 2933 return r; 2934 } 2935 2936 return 0; 2937 } 2938 2939 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 2940 u8 *buf, int buflen, enum dss_dsi_content_type type) 2941 { 2942 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2943 u32 val; 2944 u8 dt; 2945 int r; 2946 2947 /* RX_FIFO_NOT_EMPTY */ 2948 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 2949 DSSERR("RX fifo empty when trying to read.\n"); 2950 r = -EIO; 2951 goto err; 2952 } 2953 2954 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2955 if (dsi->debug_read) 2956 DSSDBG("\theader: %08x\n", val); 2957 dt = FLD_GET(val, 5, 0); 2958 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2959 u16 err = FLD_GET(val, 23, 8); 2960 dsi_show_rx_ack_with_err(err); 2961 r = -EIO; 2962 goto err; 2963 2964 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2965 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2966 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2967 u8 data = FLD_GET(val, 15, 8); 2968 if (dsi->debug_read) 2969 DSSDBG("\t%s short response, 1 byte: %02x\n", 2970 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2971 "DCS", data); 2972 2973 if (buflen < 1) { 2974 r = -EIO; 2975 goto err; 2976 } 2977 2978 buf[0] = data; 2979 2980 return 1; 2981 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2982 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2983 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2984 u16 data = FLD_GET(val, 23, 8); 2985 if (dsi->debug_read) 2986 DSSDBG("\t%s short response, 2 byte: %04x\n", 2987 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2988 "DCS", data); 2989 2990 if (buflen < 2) { 2991 r = -EIO; 2992 goto err; 2993 } 2994 2995 buf[0] = data & 0xff; 2996 buf[1] = (data >> 8) & 0xff; 2997 2998 return 2; 2999 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 3000 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 3001 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 3002 int w; 3003 int len = FLD_GET(val, 23, 8); 3004 if (dsi->debug_read) 3005 DSSDBG("\t%s long response, len %d\n", 3006 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3007 "DCS", len); 3008 3009 if (len > buflen) { 3010 r = -EIO; 3011 goto err; 3012 } 3013 3014 /* two byte checksum ends the packet, not included in len */ 3015 for (w = 0; w < len + 2;) { 3016 int b; 3017 val = dsi_read_reg(dsidev, 3018 DSI_VC_SHORT_PACKET_HEADER(channel)); 3019 if (dsi->debug_read) 3020 DSSDBG("\t\t%02x %02x %02x %02x\n", 3021 (val >> 0) & 0xff, 3022 (val >> 8) & 0xff, 3023 (val >> 16) & 0xff, 3024 (val >> 24) & 0xff); 3025 3026 for (b = 0; b < 4; ++b) { 3027 if (w < len) 3028 buf[w] = (val >> (b * 8)) & 0xff; 3029 /* we discard the 2 byte checksum */ 3030 ++w; 3031 } 3032 } 3033 3034 return len; 3035 } else { 3036 DSSERR("\tunknown datatype 0x%02x\n", dt); 3037 r = -EIO; 3038 goto err; 3039 } 3040 3041 err: 3042 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 3043 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 3044 3045 return r; 3046 } 3047 3048 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3049 u8 *buf, int buflen) 3050 { 3051 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3052 int r; 3053 3054 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3055 if (r) 3056 goto err; 3057 3058 r = dsi_vc_send_bta_sync(dssdev, channel); 3059 if (r) 3060 goto err; 3061 3062 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3063 DSS_DSI_CONTENT_DCS); 3064 if (r < 0) 3065 goto err; 3066 3067 if (r != buflen) { 3068 r = -EIO; 3069 goto err; 3070 } 3071 3072 return 0; 3073 err: 3074 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3075 return r; 3076 } 3077 3078 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3079 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3080 { 3081 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3082 int r; 3083 3084 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3085 if (r) 3086 return r; 3087 3088 r = dsi_vc_send_bta_sync(dssdev, channel); 3089 if (r) 3090 return r; 3091 3092 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3093 DSS_DSI_CONTENT_GENERIC); 3094 if (r < 0) 3095 return r; 3096 3097 if (r != buflen) { 3098 r = -EIO; 3099 return r; 3100 } 3101 3102 return 0; 3103 } 3104 3105 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3106 u16 len) 3107 { 3108 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3109 3110 return dsi_vc_send_short(dsidev, channel, 3111 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3112 } 3113 3114 static int dsi_enter_ulps(struct platform_device *dsidev) 3115 { 3116 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3117 DECLARE_COMPLETION_ONSTACK(completion); 3118 int r, i; 3119 unsigned mask; 3120 3121 DSSDBG("Entering ULPS"); 3122 3123 WARN_ON(!dsi_bus_is_locked(dsidev)); 3124 3125 WARN_ON(dsi->ulps_enabled); 3126 3127 if (dsi->ulps_enabled) 3128 return 0; 3129 3130 /* DDR_CLK_ALWAYS_ON */ 3131 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3132 dsi_if_enable(dsidev, 0); 3133 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3134 dsi_if_enable(dsidev, 1); 3135 } 3136 3137 dsi_sync_vc(dsidev, 0); 3138 dsi_sync_vc(dsidev, 1); 3139 dsi_sync_vc(dsidev, 2); 3140 dsi_sync_vc(dsidev, 3); 3141 3142 dsi_force_tx_stop_mode_io(dsidev); 3143 3144 dsi_vc_enable(dsidev, 0, false); 3145 dsi_vc_enable(dsidev, 1, false); 3146 dsi_vc_enable(dsidev, 2, false); 3147 dsi_vc_enable(dsidev, 3, false); 3148 3149 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3150 DSSERR("HS busy when enabling ULPS\n"); 3151 return -EIO; 3152 } 3153 3154 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3155 DSSERR("LP busy when enabling ULPS\n"); 3156 return -EIO; 3157 } 3158 3159 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3160 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3161 if (r) 3162 return r; 3163 3164 mask = 0; 3165 3166 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3167 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3168 continue; 3169 mask |= 1 << i; 3170 } 3171 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3172 /* LANEx_ULPS_SIG2 */ 3173 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3174 3175 /* flush posted write and wait for SCP interface to finish the write */ 3176 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3177 3178 if (wait_for_completion_timeout(&completion, 3179 msecs_to_jiffies(1000)) == 0) { 3180 DSSERR("ULPS enable timeout\n"); 3181 r = -EIO; 3182 goto err; 3183 } 3184 3185 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3186 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3187 3188 /* Reset LANEx_ULPS_SIG2 */ 3189 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3190 3191 /* flush posted write and wait for SCP interface to finish the write */ 3192 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3193 3194 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3195 3196 dsi_if_enable(dsidev, false); 3197 3198 dsi->ulps_enabled = true; 3199 3200 return 0; 3201 3202 err: 3203 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3204 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3205 return r; 3206 } 3207 3208 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3209 unsigned ticks, bool x4, bool x16) 3210 { 3211 unsigned long fck; 3212 unsigned long total_ticks; 3213 u32 r; 3214 3215 BUG_ON(ticks > 0x1fff); 3216 3217 /* ticks in DSI_FCK */ 3218 fck = dsi_fclk_rate(dsidev); 3219 3220 r = dsi_read_reg(dsidev, DSI_TIMING2); 3221 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3222 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3223 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3224 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3225 dsi_write_reg(dsidev, DSI_TIMING2, r); 3226 3227 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3228 3229 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3230 total_ticks, 3231 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3232 (total_ticks * 1000) / (fck / 1000 / 1000)); 3233 } 3234 3235 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3236 bool x8, bool x16) 3237 { 3238 unsigned long fck; 3239 unsigned long total_ticks; 3240 u32 r; 3241 3242 BUG_ON(ticks > 0x1fff); 3243 3244 /* ticks in DSI_FCK */ 3245 fck = dsi_fclk_rate(dsidev); 3246 3247 r = dsi_read_reg(dsidev, DSI_TIMING1); 3248 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3249 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3250 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3251 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3252 dsi_write_reg(dsidev, DSI_TIMING1, r); 3253 3254 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3255 3256 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3257 total_ticks, 3258 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3259 (total_ticks * 1000) / (fck / 1000 / 1000)); 3260 } 3261 3262 static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3263 unsigned ticks, bool x4, bool x16) 3264 { 3265 unsigned long fck; 3266 unsigned long total_ticks; 3267 u32 r; 3268 3269 BUG_ON(ticks > 0x1fff); 3270 3271 /* ticks in DSI_FCK */ 3272 fck = dsi_fclk_rate(dsidev); 3273 3274 r = dsi_read_reg(dsidev, DSI_TIMING1); 3275 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3276 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3277 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3278 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3279 dsi_write_reg(dsidev, DSI_TIMING1, r); 3280 3281 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3282 3283 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3284 total_ticks, 3285 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3286 (total_ticks * 1000) / (fck / 1000 / 1000)); 3287 } 3288 3289 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3290 unsigned ticks, bool x4, bool x16) 3291 { 3292 unsigned long fck; 3293 unsigned long total_ticks; 3294 u32 r; 3295 3296 BUG_ON(ticks > 0x1fff); 3297 3298 /* ticks in TxByteClkHS */ 3299 fck = dsi_get_txbyteclkhs(dsidev); 3300 3301 r = dsi_read_reg(dsidev, DSI_TIMING2); 3302 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3303 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3304 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3305 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3306 dsi_write_reg(dsidev, DSI_TIMING2, r); 3307 3308 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3309 3310 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3311 total_ticks, 3312 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3313 (total_ticks * 1000) / (fck / 1000 / 1000)); 3314 } 3315 3316 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3317 { 3318 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3319 int num_line_buffers; 3320 3321 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3322 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3323 struct videomode *vm = &dsi->vm; 3324 /* 3325 * Don't use line buffers if width is greater than the video 3326 * port's line buffer size 3327 */ 3328 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 3329 num_line_buffers = 0; 3330 else 3331 num_line_buffers = 2; 3332 } else { 3333 /* Use maximum number of line buffers in command mode */ 3334 num_line_buffers = 2; 3335 } 3336 3337 /* LINE_BUFFER */ 3338 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3339 } 3340 3341 static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3342 { 3343 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3344 bool sync_end; 3345 u32 r; 3346 3347 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3348 sync_end = true; 3349 else 3350 sync_end = false; 3351 3352 r = dsi_read_reg(dsidev, DSI_CTRL); 3353 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3354 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3355 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3356 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3357 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3358 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3359 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3360 dsi_write_reg(dsidev, DSI_CTRL, r); 3361 } 3362 3363 static void dsi_config_blanking_modes(struct platform_device *dsidev) 3364 { 3365 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3366 int blanking_mode = dsi->vm_timings.blanking_mode; 3367 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3368 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3369 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3370 u32 r; 3371 3372 /* 3373 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3374 * 1 = Long blanking packets are sent in corresponding blanking periods 3375 */ 3376 r = dsi_read_reg(dsidev, DSI_CTRL); 3377 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3378 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3379 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3380 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3381 dsi_write_reg(dsidev, DSI_CTRL, r); 3382 } 3383 3384 /* 3385 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3386 * results in maximum transition time for data and clock lanes to enter and 3387 * exit HS mode. Hence, this is the scenario where the least amount of command 3388 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3389 * clock cycles that can be used to interleave command mode data in HS so that 3390 * all scenarios are satisfied. 3391 */ 3392 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3393 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3394 { 3395 int transition; 3396 3397 /* 3398 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3399 * time of data lanes only, if it isn't set, we need to consider HS 3400 * transition time of both data and clock lanes. HS transition time 3401 * of Scenario 3 is considered. 3402 */ 3403 if (ddr_alwon) { 3404 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3405 } else { 3406 int trans1, trans2; 3407 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3408 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3409 enter_hs + 1; 3410 transition = max(trans1, trans2); 3411 } 3412 3413 return blank > transition ? blank - transition : 0; 3414 } 3415 3416 /* 3417 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3418 * results in maximum transition time for data lanes to enter and exit LP mode. 3419 * Hence, this is the scenario where the least amount of command mode data can 3420 * be interleaved. We program the minimum amount of bytes that can be 3421 * interleaved in LP so that all scenarios are satisfied. 3422 */ 3423 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3424 int lp_clk_div, int tdsi_fclk) 3425 { 3426 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3427 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3428 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3429 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3430 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3431 3432 /* maximum LP transition time according to Scenario 1 */ 3433 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3434 3435 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3436 tlp_avail = thsbyte_clk * (blank - trans_lp); 3437 3438 ttxclkesc = tdsi_fclk * lp_clk_div; 3439 3440 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3441 26) / 16; 3442 3443 return max(lp_inter, 0); 3444 } 3445 3446 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3447 { 3448 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3449 int blanking_mode; 3450 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3451 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3452 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3453 int tclk_trail, ths_exit, exiths_clk; 3454 bool ddr_alwon; 3455 struct videomode *vm = &dsi->vm; 3456 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3457 int ndl = dsi->num_lanes_used - 1; 3458 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3459 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3460 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3461 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3462 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3463 u32 r; 3464 3465 r = dsi_read_reg(dsidev, DSI_CTRL); 3466 blanking_mode = FLD_GET(r, 20, 20); 3467 hfp_blanking_mode = FLD_GET(r, 21, 21); 3468 hbp_blanking_mode = FLD_GET(r, 22, 22); 3469 hsa_blanking_mode = FLD_GET(r, 23, 23); 3470 3471 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3472 hbp = FLD_GET(r, 11, 0); 3473 hfp = FLD_GET(r, 23, 12); 3474 hsa = FLD_GET(r, 31, 24); 3475 3476 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3477 ddr_clk_post = FLD_GET(r, 7, 0); 3478 ddr_clk_pre = FLD_GET(r, 15, 8); 3479 3480 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3481 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3482 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3483 3484 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3485 lp_clk_div = FLD_GET(r, 12, 0); 3486 ddr_alwon = FLD_GET(r, 13, 13); 3487 3488 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3489 ths_exit = FLD_GET(r, 7, 0); 3490 3491 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3492 tclk_trail = FLD_GET(r, 15, 8); 3493 3494 exiths_clk = ths_exit + tclk_trail; 3495 3496 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3497 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3498 3499 if (!hsa_blanking_mode) { 3500 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3501 enter_hs_mode_lat, exit_hs_mode_lat, 3502 exiths_clk, ddr_clk_pre, ddr_clk_post); 3503 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3504 enter_hs_mode_lat, exit_hs_mode_lat, 3505 lp_clk_div, dsi_fclk_hsdiv); 3506 } 3507 3508 if (!hfp_blanking_mode) { 3509 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3510 enter_hs_mode_lat, exit_hs_mode_lat, 3511 exiths_clk, ddr_clk_pre, ddr_clk_post); 3512 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3513 enter_hs_mode_lat, exit_hs_mode_lat, 3514 lp_clk_div, dsi_fclk_hsdiv); 3515 } 3516 3517 if (!hbp_blanking_mode) { 3518 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3519 enter_hs_mode_lat, exit_hs_mode_lat, 3520 exiths_clk, ddr_clk_pre, ddr_clk_post); 3521 3522 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3523 enter_hs_mode_lat, exit_hs_mode_lat, 3524 lp_clk_div, dsi_fclk_hsdiv); 3525 } 3526 3527 if (!blanking_mode) { 3528 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3529 enter_hs_mode_lat, exit_hs_mode_lat, 3530 exiths_clk, ddr_clk_pre, ddr_clk_post); 3531 3532 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3533 enter_hs_mode_lat, exit_hs_mode_lat, 3534 lp_clk_div, dsi_fclk_hsdiv); 3535 } 3536 3537 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3538 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3539 bl_interleave_hs); 3540 3541 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3542 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3543 bl_interleave_lp); 3544 3545 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3546 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3547 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3548 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3549 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3550 3551 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3552 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3553 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3554 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3555 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3556 3557 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3558 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3559 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3560 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3561 } 3562 3563 static int dsi_proto_config(struct platform_device *dsidev) 3564 { 3565 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3566 u32 r; 3567 int buswidth = 0; 3568 3569 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3570 DSI_FIFO_SIZE_32, 3571 DSI_FIFO_SIZE_32, 3572 DSI_FIFO_SIZE_32); 3573 3574 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3575 DSI_FIFO_SIZE_32, 3576 DSI_FIFO_SIZE_32, 3577 DSI_FIFO_SIZE_32); 3578 3579 /* XXX what values for the timeouts? */ 3580 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3581 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3582 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3583 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3584 3585 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3586 case 16: 3587 buswidth = 0; 3588 break; 3589 case 18: 3590 buswidth = 1; 3591 break; 3592 case 24: 3593 buswidth = 2; 3594 break; 3595 default: 3596 BUG(); 3597 return -EINVAL; 3598 } 3599 3600 r = dsi_read_reg(dsidev, DSI_CTRL); 3601 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3602 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3603 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3604 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3605 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3606 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3607 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3608 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3609 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 3610 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3611 /* DCS_CMD_CODE, 1=start, 0=continue */ 3612 r = FLD_MOD(r, 0, 25, 25); 3613 } 3614 3615 dsi_write_reg(dsidev, DSI_CTRL, r); 3616 3617 dsi_config_vp_num_line_buffers(dsidev); 3618 3619 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3620 dsi_config_vp_sync_events(dsidev); 3621 dsi_config_blanking_modes(dsidev); 3622 dsi_config_cmd_mode_interleaving(dsidev); 3623 } 3624 3625 dsi_vc_initial_config(dsidev, 0); 3626 dsi_vc_initial_config(dsidev, 1); 3627 dsi_vc_initial_config(dsidev, 2); 3628 dsi_vc_initial_config(dsidev, 3); 3629 3630 return 0; 3631 } 3632 3633 static void dsi_proto_timings(struct platform_device *dsidev) 3634 { 3635 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3636 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; 3637 unsigned tclk_pre, tclk_post; 3638 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3639 unsigned ths_trail, ths_exit; 3640 unsigned ddr_clk_pre, ddr_clk_post; 3641 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3642 unsigned ths_eot; 3643 int ndl = dsi->num_lanes_used - 1; 3644 u32 r; 3645 3646 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3647 ths_prepare = FLD_GET(r, 31, 24); 3648 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3649 ths_zero = ths_prepare_ths_zero - ths_prepare; 3650 ths_trail = FLD_GET(r, 15, 8); 3651 ths_exit = FLD_GET(r, 7, 0); 3652 3653 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3654 tlpx = FLD_GET(r, 20, 16) * 2; 3655 tclk_trail = FLD_GET(r, 15, 8); 3656 tclk_zero = FLD_GET(r, 7, 0); 3657 3658 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3659 tclk_prepare = FLD_GET(r, 7, 0); 3660 3661 /* min 8*UI */ 3662 tclk_pre = 20; 3663 /* min 60ns + 52*UI */ 3664 tclk_post = ns2ddr(dsidev, 60) + 26; 3665 3666 ths_eot = DIV_ROUND_UP(4, ndl); 3667 3668 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3669 4); 3670 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3671 3672 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3673 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3674 3675 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3676 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3677 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3678 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3679 3680 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3681 ddr_clk_pre, 3682 ddr_clk_post); 3683 3684 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3685 DIV_ROUND_UP(ths_prepare, 4) + 3686 DIV_ROUND_UP(ths_zero + 3, 4); 3687 3688 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3689 3690 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3691 FLD_VAL(exit_hs_mode_lat, 15, 0); 3692 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3693 3694 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3695 enter_hs_mode_lat, exit_hs_mode_lat); 3696 3697 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3698 /* TODO: Implement a video mode check_timings function */ 3699 int hsa = dsi->vm_timings.hsa; 3700 int hfp = dsi->vm_timings.hfp; 3701 int hbp = dsi->vm_timings.hbp; 3702 int vsa = dsi->vm_timings.vsa; 3703 int vfp = dsi->vm_timings.vfp; 3704 int vbp = dsi->vm_timings.vbp; 3705 int window_sync = dsi->vm_timings.window_sync; 3706 bool hsync_end; 3707 struct videomode *vm = &dsi->vm; 3708 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3709 int tl, t_he, width_bytes; 3710 3711 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3712 t_he = hsync_end ? 3713 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3714 3715 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3716 3717 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3718 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3719 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3720 3721 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3722 hfp, hsync_end ? hsa : 0, tl); 3723 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3724 vsa, vm->vactive); 3725 3726 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3727 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3728 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3729 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3730 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3731 3732 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3733 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3734 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3735 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3736 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3737 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3738 3739 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3740 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 3741 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3742 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3743 } 3744 } 3745 3746 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3747 const struct omap_dsi_pin_config *pin_cfg) 3748 { 3749 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3750 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3751 int num_pins; 3752 const int *pins; 3753 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3754 int num_lanes; 3755 int i; 3756 3757 static const enum dsi_lane_function functions[] = { 3758 DSI_LANE_CLK, 3759 DSI_LANE_DATA1, 3760 DSI_LANE_DATA2, 3761 DSI_LANE_DATA3, 3762 DSI_LANE_DATA4, 3763 }; 3764 3765 num_pins = pin_cfg->num_pins; 3766 pins = pin_cfg->pins; 3767 3768 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3769 || num_pins % 2 != 0) 3770 return -EINVAL; 3771 3772 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3773 lanes[i].function = DSI_LANE_UNUSED; 3774 3775 num_lanes = 0; 3776 3777 for (i = 0; i < num_pins; i += 2) { 3778 u8 lane, pol; 3779 int dx, dy; 3780 3781 dx = pins[i]; 3782 dy = pins[i + 1]; 3783 3784 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3785 return -EINVAL; 3786 3787 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3788 return -EINVAL; 3789 3790 if (dx & 1) { 3791 if (dy != dx - 1) 3792 return -EINVAL; 3793 pol = 1; 3794 } else { 3795 if (dy != dx + 1) 3796 return -EINVAL; 3797 pol = 0; 3798 } 3799 3800 lane = dx / 2; 3801 3802 lanes[lane].function = functions[i / 2]; 3803 lanes[lane].polarity = pol; 3804 num_lanes++; 3805 } 3806 3807 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3808 dsi->num_lanes_used = num_lanes; 3809 3810 return 0; 3811 } 3812 3813 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3814 { 3815 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3816 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3817 enum omap_channel dispc_channel = dssdev->dispc_channel; 3818 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3819 struct omap_dss_device *out = &dsi->output; 3820 u8 data_type; 3821 u16 word_count; 3822 int r; 3823 3824 if (!out->dispc_channel_connected) { 3825 DSSERR("failed to enable display: no output/manager\n"); 3826 return -ENODEV; 3827 } 3828 3829 r = dsi_display_init_dispc(dsidev, dispc_channel); 3830 if (r) 3831 goto err_init_dispc; 3832 3833 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3834 switch (dsi->pix_fmt) { 3835 case OMAP_DSS_DSI_FMT_RGB888: 3836 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3837 break; 3838 case OMAP_DSS_DSI_FMT_RGB666: 3839 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3840 break; 3841 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3842 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3843 break; 3844 case OMAP_DSS_DSI_FMT_RGB565: 3845 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3846 break; 3847 default: 3848 r = -EINVAL; 3849 goto err_pix_fmt; 3850 } 3851 3852 dsi_if_enable(dsidev, false); 3853 dsi_vc_enable(dsidev, channel, false); 3854 3855 /* MODE, 1 = video mode */ 3856 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3857 3858 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3859 3860 dsi_vc_write_long_header(dsidev, channel, data_type, 3861 word_count, 0); 3862 3863 dsi_vc_enable(dsidev, channel, true); 3864 dsi_if_enable(dsidev, true); 3865 } 3866 3867 r = dss_mgr_enable(dispc_channel); 3868 if (r) 3869 goto err_mgr_enable; 3870 3871 return 0; 3872 3873 err_mgr_enable: 3874 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3875 dsi_if_enable(dsidev, false); 3876 dsi_vc_enable(dsidev, channel, false); 3877 } 3878 err_pix_fmt: 3879 dsi_display_uninit_dispc(dsidev, dispc_channel); 3880 err_init_dispc: 3881 return r; 3882 } 3883 3884 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3885 { 3886 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3887 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3888 enum omap_channel dispc_channel = dssdev->dispc_channel; 3889 3890 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3891 dsi_if_enable(dsidev, false); 3892 dsi_vc_enable(dsidev, channel, false); 3893 3894 /* MODE, 0 = command mode */ 3895 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 3896 3897 dsi_vc_enable(dsidev, channel, true); 3898 dsi_if_enable(dsidev, true); 3899 } 3900 3901 dss_mgr_disable(dispc_channel); 3902 3903 dsi_display_uninit_dispc(dsidev, dispc_channel); 3904 } 3905 3906 static void dsi_update_screen_dispc(struct platform_device *dsidev) 3907 { 3908 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3909 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3910 unsigned bytespp; 3911 unsigned bytespl; 3912 unsigned bytespf; 3913 unsigned total_len; 3914 unsigned packet_payload; 3915 unsigned packet_len; 3916 u32 l; 3917 int r; 3918 const unsigned channel = dsi->update_channel; 3919 const unsigned line_buf_size = dsi->line_buffer_size; 3920 u16 w = dsi->vm.hactive; 3921 u16 h = dsi->vm.vactive; 3922 3923 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3924 3925 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 3926 3927 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3928 bytespl = w * bytespp; 3929 bytespf = bytespl * h; 3930 3931 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3932 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3933 3934 if (bytespf < line_buf_size) 3935 packet_payload = bytespf; 3936 else 3937 packet_payload = (line_buf_size) / bytespl * bytespl; 3938 3939 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3940 total_len = (bytespf / packet_payload) * packet_len; 3941 3942 if (bytespf % packet_payload) 3943 total_len += (bytespf % packet_payload) + 1; 3944 3945 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3946 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3947 3948 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 3949 packet_len, 0); 3950 3951 if (dsi->te_enabled) 3952 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3953 else 3954 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3955 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3956 3957 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3958 * because DSS interrupts are not capable of waking up the CPU and the 3959 * framedone interrupt could be delayed for quite a long time. I think 3960 * the same goes for any DSS interrupts, but for some reason I have not 3961 * seen the problem anywhere else than here. 3962 */ 3963 dispc_disable_sidle(); 3964 3965 dsi_perf_mark_start(dsidev); 3966 3967 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3968 msecs_to_jiffies(250)); 3969 BUG_ON(r == 0); 3970 3971 dss_mgr_set_timings(dispc_channel, &dsi->vm); 3972 3973 dss_mgr_start_update(dispc_channel); 3974 3975 if (dsi->te_enabled) { 3976 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3977 * for TE is longer than the timer allows */ 3978 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3979 3980 dsi_vc_send_bta(dsidev, channel); 3981 3982 #ifdef DSI_CATCH_MISSING_TE 3983 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3984 #endif 3985 } 3986 } 3987 3988 #ifdef DSI_CATCH_MISSING_TE 3989 static void dsi_te_timeout(unsigned long arg) 3990 { 3991 DSSERR("TE not received for 250ms!\n"); 3992 } 3993 #endif 3994 3995 static void dsi_handle_framedone(struct platform_device *dsidev, int error) 3996 { 3997 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3998 3999 /* SIDLEMODE back to smart-idle */ 4000 dispc_enable_sidle(); 4001 4002 if (dsi->te_enabled) { 4003 /* enable LP_RX_TO again after the TE */ 4004 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 4005 } 4006 4007 dsi->framedone_callback(error, dsi->framedone_data); 4008 4009 if (!error) 4010 dsi_perf_show(dsidev, "DISPC"); 4011 } 4012 4013 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4014 { 4015 struct dsi_data *dsi = container_of(work, struct dsi_data, 4016 framedone_timeout_work.work); 4017 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 4018 * 250ms which would conflict with this timeout work. What should be 4019 * done is first cancel the transfer on the HW, and then cancel the 4020 * possibly scheduled framedone work. However, cancelling the transfer 4021 * on the HW is buggy, and would probably require resetting the whole 4022 * DSI */ 4023 4024 DSSERR("Framedone not received for 250ms!\n"); 4025 4026 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4027 } 4028 4029 static void dsi_framedone_irq_callback(void *data) 4030 { 4031 struct platform_device *dsidev = (struct platform_device *) data; 4032 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4033 4034 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4035 * turns itself off. However, DSI still has the pixels in its buffers, 4036 * and is sending the data. 4037 */ 4038 4039 cancel_delayed_work(&dsi->framedone_timeout_work); 4040 4041 dsi_handle_framedone(dsidev, 0); 4042 } 4043 4044 static int dsi_update(struct omap_dss_device *dssdev, int channel, 4045 void (*callback)(int, void *), void *data) 4046 { 4047 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4048 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4049 u16 dw, dh; 4050 4051 dsi_perf_mark_setup(dsidev); 4052 4053 dsi->update_channel = channel; 4054 4055 dsi->framedone_callback = callback; 4056 dsi->framedone_data = data; 4057 4058 dw = dsi->vm.hactive; 4059 dh = dsi->vm.vactive; 4060 4061 #ifdef DSI_PERF_MEASURE 4062 dsi->update_bytes = dw * dh * 4063 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4064 #endif 4065 dsi_update_screen_dispc(dsidev); 4066 4067 return 0; 4068 } 4069 4070 /* Display funcs */ 4071 4072 static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4073 { 4074 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4075 struct dispc_clock_info dispc_cinfo; 4076 int r; 4077 unsigned long fck; 4078 4079 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4080 4081 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4082 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4083 4084 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4085 if (r) { 4086 DSSERR("Failed to calc dispc clocks\n"); 4087 return r; 4088 } 4089 4090 dsi->mgr_config.clock_info = dispc_cinfo; 4091 4092 return 0; 4093 } 4094 4095 static int dsi_display_init_dispc(struct platform_device *dsidev, 4096 enum omap_channel channel) 4097 { 4098 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4099 int r; 4100 4101 dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? 4102 DSS_CLK_SRC_PLL1_1 : 4103 DSS_CLK_SRC_PLL2_1); 4104 4105 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4106 r = dss_mgr_register_framedone_handler(channel, 4107 dsi_framedone_irq_callback, dsidev); 4108 if (r) { 4109 DSSERR("can't register FRAMEDONE handler\n"); 4110 goto err; 4111 } 4112 4113 dsi->mgr_config.stallmode = true; 4114 dsi->mgr_config.fifohandcheck = true; 4115 } else { 4116 dsi->mgr_config.stallmode = false; 4117 dsi->mgr_config.fifohandcheck = false; 4118 } 4119 4120 /* 4121 * override interlace, logic level and edge related parameters in 4122 * videomode with default values 4123 */ 4124 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4125 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4126 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4127 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4128 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4129 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4130 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4131 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4132 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4133 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4134 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4135 4136 dss_mgr_set_timings(channel, &dsi->vm); 4137 4138 r = dsi_configure_dispc_clocks(dsidev); 4139 if (r) 4140 goto err1; 4141 4142 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4143 dsi->mgr_config.video_port_width = 4144 dsi_get_pixel_size(dsi->pix_fmt); 4145 dsi->mgr_config.lcden_sig_polarity = 0; 4146 4147 dss_mgr_set_lcd_config(channel, &dsi->mgr_config); 4148 4149 return 0; 4150 err1: 4151 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4152 dss_mgr_unregister_framedone_handler(channel, 4153 dsi_framedone_irq_callback, dsidev); 4154 err: 4155 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4156 return r; 4157 } 4158 4159 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4160 enum omap_channel channel) 4161 { 4162 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4163 4164 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4165 dss_mgr_unregister_framedone_handler(channel, 4166 dsi_framedone_irq_callback, dsidev); 4167 4168 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4169 } 4170 4171 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4172 { 4173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4174 struct dss_pll_clock_info cinfo; 4175 int r; 4176 4177 cinfo = dsi->user_dsi_cinfo; 4178 4179 r = dss_pll_set_config(&dsi->pll, &cinfo); 4180 if (r) { 4181 DSSERR("Failed to set dsi clocks\n"); 4182 return r; 4183 } 4184 4185 return 0; 4186 } 4187 4188 static int dsi_display_init_dsi(struct platform_device *dsidev) 4189 { 4190 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4191 int r; 4192 4193 r = dss_pll_enable(&dsi->pll); 4194 if (r) 4195 goto err0; 4196 4197 r = dsi_configure_dsi_clocks(dsidev); 4198 if (r) 4199 goto err1; 4200 4201 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4202 DSS_CLK_SRC_PLL1_2 : 4203 DSS_CLK_SRC_PLL2_2); 4204 4205 DSSDBG("PLL OK\n"); 4206 4207 r = dsi_cio_init(dsidev); 4208 if (r) 4209 goto err2; 4210 4211 _dsi_print_reset_status(dsidev); 4212 4213 dsi_proto_timings(dsidev); 4214 dsi_set_lp_clk_divisor(dsidev); 4215 4216 if (1) 4217 _dsi_print_reset_status(dsidev); 4218 4219 r = dsi_proto_config(dsidev); 4220 if (r) 4221 goto err3; 4222 4223 /* enable interface */ 4224 dsi_vc_enable(dsidev, 0, 1); 4225 dsi_vc_enable(dsidev, 1, 1); 4226 dsi_vc_enable(dsidev, 2, 1); 4227 dsi_vc_enable(dsidev, 3, 1); 4228 dsi_if_enable(dsidev, 1); 4229 dsi_force_tx_stop_mode_io(dsidev); 4230 4231 return 0; 4232 err3: 4233 dsi_cio_uninit(dsidev); 4234 err2: 4235 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4236 err1: 4237 dss_pll_disable(&dsi->pll); 4238 err0: 4239 return r; 4240 } 4241 4242 static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4243 bool disconnect_lanes, bool enter_ulps) 4244 { 4245 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4246 4247 if (enter_ulps && !dsi->ulps_enabled) 4248 dsi_enter_ulps(dsidev); 4249 4250 /* disable interface */ 4251 dsi_if_enable(dsidev, 0); 4252 dsi_vc_enable(dsidev, 0, 0); 4253 dsi_vc_enable(dsidev, 1, 0); 4254 dsi_vc_enable(dsidev, 2, 0); 4255 dsi_vc_enable(dsidev, 3, 0); 4256 4257 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4258 dsi_cio_uninit(dsidev); 4259 dsi_pll_uninit(dsidev, disconnect_lanes); 4260 } 4261 4262 static int dsi_display_enable(struct omap_dss_device *dssdev) 4263 { 4264 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4265 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4266 int r = 0; 4267 4268 DSSDBG("dsi_display_enable\n"); 4269 4270 WARN_ON(!dsi_bus_is_locked(dsidev)); 4271 4272 mutex_lock(&dsi->lock); 4273 4274 r = dsi_runtime_get(dsidev); 4275 if (r) 4276 goto err_get_dsi; 4277 4278 _dsi_initialize_irq(dsidev); 4279 4280 r = dsi_display_init_dsi(dsidev); 4281 if (r) 4282 goto err_init_dsi; 4283 4284 mutex_unlock(&dsi->lock); 4285 4286 return 0; 4287 4288 err_init_dsi: 4289 dsi_runtime_put(dsidev); 4290 err_get_dsi: 4291 mutex_unlock(&dsi->lock); 4292 DSSDBG("dsi_display_enable FAILED\n"); 4293 return r; 4294 } 4295 4296 static void dsi_display_disable(struct omap_dss_device *dssdev, 4297 bool disconnect_lanes, bool enter_ulps) 4298 { 4299 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4300 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4301 4302 DSSDBG("dsi_display_disable\n"); 4303 4304 WARN_ON(!dsi_bus_is_locked(dsidev)); 4305 4306 mutex_lock(&dsi->lock); 4307 4308 dsi_sync_vc(dsidev, 0); 4309 dsi_sync_vc(dsidev, 1); 4310 dsi_sync_vc(dsidev, 2); 4311 dsi_sync_vc(dsidev, 3); 4312 4313 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4314 4315 dsi_runtime_put(dsidev); 4316 4317 mutex_unlock(&dsi->lock); 4318 } 4319 4320 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4321 { 4322 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4323 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4324 4325 dsi->te_enabled = enable; 4326 return 0; 4327 } 4328 4329 #ifdef PRINT_VERBOSE_VM_TIMINGS 4330 static void print_dsi_vm(const char *str, 4331 const struct omap_dss_dsi_videomode_timings *t) 4332 { 4333 unsigned long byteclk = t->hsclk / 4; 4334 int bl, wc, pps, tot; 4335 4336 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4337 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4338 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4339 tot = bl + pps; 4340 4341 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4342 4343 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4344 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4345 str, 4346 byteclk, 4347 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4348 bl, pps, tot, 4349 TO_DSI_T(t->hss), 4350 TO_DSI_T(t->hsa), 4351 TO_DSI_T(t->hse), 4352 TO_DSI_T(t->hbp), 4353 TO_DSI_T(pps), 4354 TO_DSI_T(t->hfp), 4355 4356 TO_DSI_T(bl), 4357 TO_DSI_T(pps), 4358 4359 TO_DSI_T(tot)); 4360 #undef TO_DSI_T 4361 } 4362 4363 static void print_dispc_vm(const char *str, const struct videomode *vm) 4364 { 4365 unsigned long pck = vm->pixelclock; 4366 int hact, bl, tot; 4367 4368 hact = vm->hactive; 4369 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 4370 tot = hact + bl; 4371 4372 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4373 4374 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4375 "%u/%u/%u/%u = %u + %u = %u\n", 4376 str, 4377 pck, 4378 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 4379 bl, hact, tot, 4380 TO_DISPC_T(vm->hsync_len), 4381 TO_DISPC_T(vm->hback_porch), 4382 TO_DISPC_T(hact), 4383 TO_DISPC_T(vm->hfront_porch), 4384 TO_DISPC_T(bl), 4385 TO_DISPC_T(hact), 4386 TO_DISPC_T(tot)); 4387 #undef TO_DISPC_T 4388 } 4389 4390 /* note: this is not quite accurate */ 4391 static void print_dsi_dispc_vm(const char *str, 4392 const struct omap_dss_dsi_videomode_timings *t) 4393 { 4394 struct videomode vm = { 0 }; 4395 unsigned long byteclk = t->hsclk / 4; 4396 unsigned long pck; 4397 u64 dsi_tput; 4398 int dsi_hact, dsi_htot; 4399 4400 dsi_tput = (u64)byteclk * t->ndl * 8; 4401 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4402 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4403 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4404 4405 vm.pixelclock = pck; 4406 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4407 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 4408 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 4409 vm.hactive = t->hact; 4410 4411 print_dispc_vm(str, &vm); 4412 } 4413 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4414 4415 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4416 unsigned long pck, void *data) 4417 { 4418 struct dsi_clk_calc_ctx *ctx = data; 4419 struct videomode *vm = &ctx->vm; 4420 4421 ctx->dispc_cinfo.lck_div = lckd; 4422 ctx->dispc_cinfo.pck_div = pckd; 4423 ctx->dispc_cinfo.lck = lck; 4424 ctx->dispc_cinfo.pck = pck; 4425 4426 *vm = *ctx->config->vm; 4427 vm->pixelclock = pck; 4428 vm->hactive = ctx->config->vm->hactive; 4429 vm->vactive = ctx->config->vm->vactive; 4430 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 4431 vm->vfront_porch = vm->vback_porch = 0; 4432 4433 return true; 4434 } 4435 4436 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4437 void *data) 4438 { 4439 struct dsi_clk_calc_ctx *ctx = data; 4440 4441 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4442 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4443 4444 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4445 dsi_cm_calc_dispc_cb, ctx); 4446 } 4447 4448 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4449 unsigned long clkdco, void *data) 4450 { 4451 struct dsi_clk_calc_ctx *ctx = data; 4452 4453 ctx->dsi_cinfo.n = n; 4454 ctx->dsi_cinfo.m = m; 4455 ctx->dsi_cinfo.fint = fint; 4456 ctx->dsi_cinfo.clkdco = clkdco; 4457 4458 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4459 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4460 dsi_cm_calc_hsdiv_cb, ctx); 4461 } 4462 4463 static bool dsi_cm_calc(struct dsi_data *dsi, 4464 const struct omap_dss_dsi_config *cfg, 4465 struct dsi_clk_calc_ctx *ctx) 4466 { 4467 unsigned long clkin; 4468 int bitspp, ndl; 4469 unsigned long pll_min, pll_max; 4470 unsigned long pck, txbyteclk; 4471 4472 clkin = clk_get_rate(dsi->pll.clkin); 4473 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4474 ndl = dsi->num_lanes_used - 1; 4475 4476 /* 4477 * Here we should calculate minimum txbyteclk to be able to send the 4478 * frame in time, and also to handle TE. That's not very simple, though, 4479 * especially as we go to LP between each pixel packet due to HW 4480 * "feature". So let's just estimate very roughly and multiply by 1.5. 4481 */ 4482 pck = cfg->vm->pixelclock; 4483 pck = pck * 3 / 2; 4484 txbyteclk = pck * bitspp / 8 / ndl; 4485 4486 memset(ctx, 0, sizeof(*ctx)); 4487 ctx->dsidev = dsi->pdev; 4488 ctx->pll = &dsi->pll; 4489 ctx->config = cfg; 4490 ctx->req_pck_min = pck; 4491 ctx->req_pck_nom = pck; 4492 ctx->req_pck_max = pck * 3 / 2; 4493 4494 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4495 pll_max = cfg->hs_clk_max * 4; 4496 4497 return dss_pll_calc_a(ctx->pll, clkin, 4498 pll_min, pll_max, 4499 dsi_cm_calc_pll_cb, ctx); 4500 } 4501 4502 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4503 { 4504 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4505 const struct omap_dss_dsi_config *cfg = ctx->config; 4506 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4507 int ndl = dsi->num_lanes_used - 1; 4508 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4509 unsigned long byteclk = hsclk / 4; 4510 4511 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4512 int xres; 4513 int panel_htot, panel_hbl; /* pixels */ 4514 int dispc_htot, dispc_hbl; /* pixels */ 4515 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4516 int hfp, hsa, hbp; 4517 const struct videomode *req_vm; 4518 struct videomode *dispc_vm; 4519 struct omap_dss_dsi_videomode_timings *dsi_vm; 4520 u64 dsi_tput, dispc_tput; 4521 4522 dsi_tput = (u64)byteclk * ndl * 8; 4523 4524 req_vm = cfg->vm; 4525 req_pck_min = ctx->req_pck_min; 4526 req_pck_max = ctx->req_pck_max; 4527 req_pck_nom = ctx->req_pck_nom; 4528 4529 dispc_pck = ctx->dispc_cinfo.pck; 4530 dispc_tput = (u64)dispc_pck * bitspp; 4531 4532 xres = req_vm->hactive; 4533 4534 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 4535 req_vm->hsync_len; 4536 panel_htot = xres + panel_hbl; 4537 4538 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4539 4540 /* 4541 * When there are no line buffers, DISPC and DSI must have the 4542 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4543 */ 4544 if (dsi->line_buffer_size < xres * bitspp / 8) { 4545 if (dispc_tput != dsi_tput) 4546 return false; 4547 } else { 4548 if (dispc_tput < dsi_tput) 4549 return false; 4550 } 4551 4552 /* DSI tput must be over the min requirement */ 4553 if (dsi_tput < (u64)bitspp * req_pck_min) 4554 return false; 4555 4556 /* When non-burst mode, DSI tput must be below max requirement. */ 4557 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4558 if (dsi_tput > (u64)bitspp * req_pck_max) 4559 return false; 4560 } 4561 4562 hss = DIV_ROUND_UP(4, ndl); 4563 4564 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4565 if (ndl == 3 && req_vm->hsync_len == 0) 4566 hse = 1; 4567 else 4568 hse = DIV_ROUND_UP(4, ndl); 4569 } else { 4570 hse = 0; 4571 } 4572 4573 /* DSI htot to match the panel's nominal pck */ 4574 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4575 4576 /* fail if there would be no time for blanking */ 4577 if (dsi_htot < hss + hse + dsi_hact) 4578 return false; 4579 4580 /* total DSI blanking needed to achieve panel's TL */ 4581 dsi_hbl = dsi_htot - dsi_hact; 4582 4583 /* DISPC htot to match the DSI TL */ 4584 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4585 4586 /* verify that the DSI and DISPC TLs are the same */ 4587 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4588 return false; 4589 4590 dispc_hbl = dispc_htot - xres; 4591 4592 /* setup DSI videomode */ 4593 4594 dsi_vm = &ctx->dsi_vm; 4595 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4596 4597 dsi_vm->hsclk = hsclk; 4598 4599 dsi_vm->ndl = ndl; 4600 dsi_vm->bitspp = bitspp; 4601 4602 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4603 hsa = 0; 4604 } else if (ndl == 3 && req_vm->hsync_len == 0) { 4605 hsa = 0; 4606 } else { 4607 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 4608 hsa = max(hsa - hse, 1); 4609 } 4610 4611 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 4612 hbp = max(hbp, 1); 4613 4614 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4615 if (hfp < 1) { 4616 int t; 4617 /* we need to take cycles from hbp */ 4618 4619 t = 1 - hfp; 4620 hbp = max(hbp - t, 1); 4621 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4622 4623 if (hfp < 1 && hsa > 0) { 4624 /* we need to take cycles from hsa */ 4625 t = 1 - hfp; 4626 hsa = max(hsa - t, 1); 4627 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4628 } 4629 } 4630 4631 if (hfp < 1) 4632 return false; 4633 4634 dsi_vm->hss = hss; 4635 dsi_vm->hsa = hsa; 4636 dsi_vm->hse = hse; 4637 dsi_vm->hbp = hbp; 4638 dsi_vm->hact = xres; 4639 dsi_vm->hfp = hfp; 4640 4641 dsi_vm->vsa = req_vm->vsync_len; 4642 dsi_vm->vbp = req_vm->vback_porch; 4643 dsi_vm->vact = req_vm->vactive; 4644 dsi_vm->vfp = req_vm->vfront_porch; 4645 4646 dsi_vm->trans_mode = cfg->trans_mode; 4647 4648 dsi_vm->blanking_mode = 0; 4649 dsi_vm->hsa_blanking_mode = 1; 4650 dsi_vm->hfp_blanking_mode = 1; 4651 dsi_vm->hbp_blanking_mode = 1; 4652 4653 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4654 dsi_vm->window_sync = 4; 4655 4656 /* setup DISPC videomode */ 4657 4658 dispc_vm = &ctx->vm; 4659 *dispc_vm = *req_vm; 4660 dispc_vm->pixelclock = dispc_pck; 4661 4662 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4663 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 4664 req_pck_nom); 4665 hsa = max(hsa, 1); 4666 } else { 4667 hsa = 1; 4668 } 4669 4670 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 4671 hbp = max(hbp, 1); 4672 4673 hfp = dispc_hbl - hsa - hbp; 4674 if (hfp < 1) { 4675 int t; 4676 /* we need to take cycles from hbp */ 4677 4678 t = 1 - hfp; 4679 hbp = max(hbp - t, 1); 4680 hfp = dispc_hbl - hsa - hbp; 4681 4682 if (hfp < 1) { 4683 /* we need to take cycles from hsa */ 4684 t = 1 - hfp; 4685 hsa = max(hsa - t, 1); 4686 hfp = dispc_hbl - hsa - hbp; 4687 } 4688 } 4689 4690 if (hfp < 1) 4691 return false; 4692 4693 dispc_vm->hfront_porch = hfp; 4694 dispc_vm->hsync_len = hsa; 4695 dispc_vm->hback_porch = hbp; 4696 4697 return true; 4698 } 4699 4700 4701 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4702 unsigned long pck, void *data) 4703 { 4704 struct dsi_clk_calc_ctx *ctx = data; 4705 4706 ctx->dispc_cinfo.lck_div = lckd; 4707 ctx->dispc_cinfo.pck_div = pckd; 4708 ctx->dispc_cinfo.lck = lck; 4709 ctx->dispc_cinfo.pck = pck; 4710 4711 if (dsi_vm_calc_blanking(ctx) == false) 4712 return false; 4713 4714 #ifdef PRINT_VERBOSE_VM_TIMINGS 4715 print_dispc_vm("dispc", &ctx->vm); 4716 print_dsi_vm("dsi ", &ctx->dsi_vm); 4717 print_dispc_vm("req ", ctx->config->vm); 4718 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4719 #endif 4720 4721 return true; 4722 } 4723 4724 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4725 void *data) 4726 { 4727 struct dsi_clk_calc_ctx *ctx = data; 4728 unsigned long pck_max; 4729 4730 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4731 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4732 4733 /* 4734 * In burst mode we can let the dispc pck be arbitrarily high, but it 4735 * limits our scaling abilities. So for now, don't aim too high. 4736 */ 4737 4738 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4739 pck_max = ctx->req_pck_max + 10000000; 4740 else 4741 pck_max = ctx->req_pck_max; 4742 4743 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4744 dsi_vm_calc_dispc_cb, ctx); 4745 } 4746 4747 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4748 unsigned long clkdco, void *data) 4749 { 4750 struct dsi_clk_calc_ctx *ctx = data; 4751 4752 ctx->dsi_cinfo.n = n; 4753 ctx->dsi_cinfo.m = m; 4754 ctx->dsi_cinfo.fint = fint; 4755 ctx->dsi_cinfo.clkdco = clkdco; 4756 4757 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4758 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4759 dsi_vm_calc_hsdiv_cb, ctx); 4760 } 4761 4762 static bool dsi_vm_calc(struct dsi_data *dsi, 4763 const struct omap_dss_dsi_config *cfg, 4764 struct dsi_clk_calc_ctx *ctx) 4765 { 4766 const struct videomode *vm = cfg->vm; 4767 unsigned long clkin; 4768 unsigned long pll_min; 4769 unsigned long pll_max; 4770 int ndl = dsi->num_lanes_used - 1; 4771 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4772 unsigned long byteclk_min; 4773 4774 clkin = clk_get_rate(dsi->pll.clkin); 4775 4776 memset(ctx, 0, sizeof(*ctx)); 4777 ctx->dsidev = dsi->pdev; 4778 ctx->pll = &dsi->pll; 4779 ctx->config = cfg; 4780 4781 /* these limits should come from the panel driver */ 4782 ctx->req_pck_min = vm->pixelclock - 1000; 4783 ctx->req_pck_nom = vm->pixelclock; 4784 ctx->req_pck_max = vm->pixelclock + 1000; 4785 4786 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4787 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4788 4789 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4790 pll_max = cfg->hs_clk_max * 4; 4791 } else { 4792 unsigned long byteclk_max; 4793 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4794 ndl * 8); 4795 4796 pll_max = byteclk_max * 4 * 4; 4797 } 4798 4799 return dss_pll_calc_a(ctx->pll, clkin, 4800 pll_min, pll_max, 4801 dsi_vm_calc_pll_cb, ctx); 4802 } 4803 4804 static int dsi_set_config(struct omap_dss_device *dssdev, 4805 const struct omap_dss_dsi_config *config) 4806 { 4807 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4808 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4809 struct dsi_clk_calc_ctx ctx; 4810 bool ok; 4811 int r; 4812 4813 mutex_lock(&dsi->lock); 4814 4815 dsi->pix_fmt = config->pixel_format; 4816 dsi->mode = config->mode; 4817 4818 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4819 ok = dsi_vm_calc(dsi, config, &ctx); 4820 else 4821 ok = dsi_cm_calc(dsi, config, &ctx); 4822 4823 if (!ok) { 4824 DSSERR("failed to find suitable DSI clock settings\n"); 4825 r = -EINVAL; 4826 goto err; 4827 } 4828 4829 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); 4830 4831 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4832 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4833 if (r) { 4834 DSSERR("failed to find suitable DSI LP clock settings\n"); 4835 goto err; 4836 } 4837 4838 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4839 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4840 4841 dsi->vm = ctx.vm; 4842 dsi->vm_timings = ctx.dsi_vm; 4843 4844 mutex_unlock(&dsi->lock); 4845 4846 return 0; 4847 err: 4848 mutex_unlock(&dsi->lock); 4849 4850 return r; 4851 } 4852 4853 /* 4854 * Return a hardcoded channel for the DSI output. This should work for 4855 * current use cases, but this can be later expanded to either resolve 4856 * the channel in some more dynamic manner, or get the channel as a user 4857 * parameter. 4858 */ 4859 static enum omap_channel dsi_get_channel(int module_id) 4860 { 4861 switch (omapdss_get_version()) { 4862 case OMAPDSS_VER_OMAP24xx: 4863 case OMAPDSS_VER_AM43xx: 4864 DSSWARN("DSI not supported\n"); 4865 return OMAP_DSS_CHANNEL_LCD; 4866 4867 case OMAPDSS_VER_OMAP34xx_ES1: 4868 case OMAPDSS_VER_OMAP34xx_ES3: 4869 case OMAPDSS_VER_OMAP3630: 4870 case OMAPDSS_VER_AM35xx: 4871 return OMAP_DSS_CHANNEL_LCD; 4872 4873 case OMAPDSS_VER_OMAP4430_ES1: 4874 case OMAPDSS_VER_OMAP4430_ES2: 4875 case OMAPDSS_VER_OMAP4: 4876 switch (module_id) { 4877 case 0: 4878 return OMAP_DSS_CHANNEL_LCD; 4879 case 1: 4880 return OMAP_DSS_CHANNEL_LCD2; 4881 default: 4882 DSSWARN("unsupported module id\n"); 4883 return OMAP_DSS_CHANNEL_LCD; 4884 } 4885 4886 case OMAPDSS_VER_OMAP5: 4887 switch (module_id) { 4888 case 0: 4889 return OMAP_DSS_CHANNEL_LCD; 4890 case 1: 4891 return OMAP_DSS_CHANNEL_LCD3; 4892 default: 4893 DSSWARN("unsupported module id\n"); 4894 return OMAP_DSS_CHANNEL_LCD; 4895 } 4896 4897 default: 4898 DSSWARN("unsupported DSS version\n"); 4899 return OMAP_DSS_CHANNEL_LCD; 4900 } 4901 } 4902 4903 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4904 { 4905 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4906 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4907 int i; 4908 4909 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4910 if (!dsi->vc[i].dssdev) { 4911 dsi->vc[i].dssdev = dssdev; 4912 *channel = i; 4913 return 0; 4914 } 4915 } 4916 4917 DSSERR("cannot get VC for display %s", dssdev->name); 4918 return -ENOSPC; 4919 } 4920 4921 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4922 { 4923 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4924 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4925 4926 if (vc_id < 0 || vc_id > 3) { 4927 DSSERR("VC ID out of range\n"); 4928 return -EINVAL; 4929 } 4930 4931 if (channel < 0 || channel > 3) { 4932 DSSERR("Virtual Channel out of range\n"); 4933 return -EINVAL; 4934 } 4935 4936 if (dsi->vc[channel].dssdev != dssdev) { 4937 DSSERR("Virtual Channel not allocated to display %s\n", 4938 dssdev->name); 4939 return -EINVAL; 4940 } 4941 4942 dsi->vc[channel].vc_id = vc_id; 4943 4944 return 0; 4945 } 4946 4947 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4948 { 4949 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4950 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4951 4952 if ((channel >= 0 && channel <= 3) && 4953 dsi->vc[channel].dssdev == dssdev) { 4954 dsi->vc[channel].dssdev = NULL; 4955 dsi->vc[channel].vc_id = 0; 4956 } 4957 } 4958 4959 4960 static int dsi_get_clocks(struct platform_device *dsidev) 4961 { 4962 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4963 struct clk *clk; 4964 4965 clk = devm_clk_get(&dsidev->dev, "fck"); 4966 if (IS_ERR(clk)) { 4967 DSSERR("can't get fck\n"); 4968 return PTR_ERR(clk); 4969 } 4970 4971 dsi->dss_clk = clk; 4972 4973 return 0; 4974 } 4975 4976 static int dsi_connect(struct omap_dss_device *dssdev, 4977 struct omap_dss_device *dst) 4978 { 4979 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4980 enum omap_channel dispc_channel = dssdev->dispc_channel; 4981 int r; 4982 4983 r = dsi_regulator_init(dsidev); 4984 if (r) 4985 return r; 4986 4987 r = dss_mgr_connect(dispc_channel, dssdev); 4988 if (r) 4989 return r; 4990 4991 r = omapdss_output_set_device(dssdev, dst); 4992 if (r) { 4993 DSSERR("failed to connect output to new device: %s\n", 4994 dssdev->name); 4995 dss_mgr_disconnect(dispc_channel, dssdev); 4996 return r; 4997 } 4998 4999 return 0; 5000 } 5001 5002 static void dsi_disconnect(struct omap_dss_device *dssdev, 5003 struct omap_dss_device *dst) 5004 { 5005 enum omap_channel dispc_channel = dssdev->dispc_channel; 5006 5007 WARN_ON(dst != dssdev->dst); 5008 5009 if (dst != dssdev->dst) 5010 return; 5011 5012 omapdss_output_unset_device(dssdev); 5013 5014 dss_mgr_disconnect(dispc_channel, dssdev); 5015 } 5016 5017 static const struct omapdss_dsi_ops dsi_ops = { 5018 .connect = dsi_connect, 5019 .disconnect = dsi_disconnect, 5020 5021 .bus_lock = dsi_bus_lock, 5022 .bus_unlock = dsi_bus_unlock, 5023 5024 .enable = dsi_display_enable, 5025 .disable = dsi_display_disable, 5026 5027 .enable_hs = dsi_vc_enable_hs, 5028 5029 .configure_pins = dsi_configure_pins, 5030 .set_config = dsi_set_config, 5031 5032 .enable_video_output = dsi_enable_video_output, 5033 .disable_video_output = dsi_disable_video_output, 5034 5035 .update = dsi_update, 5036 5037 .enable_te = dsi_enable_te, 5038 5039 .request_vc = dsi_request_vc, 5040 .set_vc_id = dsi_set_vc_id, 5041 .release_vc = dsi_release_vc, 5042 5043 .dcs_write = dsi_vc_dcs_write, 5044 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 5045 .dcs_read = dsi_vc_dcs_read, 5046 5047 .gen_write = dsi_vc_generic_write, 5048 .gen_write_nosync = dsi_vc_generic_write_nosync, 5049 .gen_read = dsi_vc_generic_read, 5050 5051 .bta_sync = dsi_vc_send_bta_sync, 5052 5053 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5054 }; 5055 5056 static void dsi_init_output(struct platform_device *dsidev) 5057 { 5058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5059 struct omap_dss_device *out = &dsi->output; 5060 5061 out->dev = &dsidev->dev; 5062 out->id = dsi->module_id == 0 ? 5063 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5064 5065 out->output_type = OMAP_DISPLAY_TYPE_DSI; 5066 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5067 out->dispc_channel = dsi_get_channel(dsi->module_id); 5068 out->ops.dsi = &dsi_ops; 5069 out->owner = THIS_MODULE; 5070 5071 omapdss_register_output(out); 5072 } 5073 5074 static void dsi_uninit_output(struct platform_device *dsidev) 5075 { 5076 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5077 struct omap_dss_device *out = &dsi->output; 5078 5079 omapdss_unregister_output(out); 5080 } 5081 5082 static int dsi_probe_of(struct platform_device *pdev) 5083 { 5084 struct device_node *node = pdev->dev.of_node; 5085 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5086 struct property *prop; 5087 u32 lane_arr[10]; 5088 int len, num_pins; 5089 int r, i; 5090 struct device_node *ep; 5091 struct omap_dsi_pin_config pin_cfg; 5092 5093 ep = omapdss_of_get_first_endpoint(node); 5094 if (!ep) 5095 return 0; 5096 5097 prop = of_find_property(ep, "lanes", &len); 5098 if (prop == NULL) { 5099 dev_err(&pdev->dev, "failed to find lane data\n"); 5100 r = -EINVAL; 5101 goto err; 5102 } 5103 5104 num_pins = len / sizeof(u32); 5105 5106 if (num_pins < 4 || num_pins % 2 != 0 || 5107 num_pins > dsi->num_lanes_supported * 2) { 5108 dev_err(&pdev->dev, "bad number of lanes\n"); 5109 r = -EINVAL; 5110 goto err; 5111 } 5112 5113 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5114 if (r) { 5115 dev_err(&pdev->dev, "failed to read lane data\n"); 5116 goto err; 5117 } 5118 5119 pin_cfg.num_pins = num_pins; 5120 for (i = 0; i < num_pins; ++i) 5121 pin_cfg.pins[i] = (int)lane_arr[i]; 5122 5123 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5124 if (r) { 5125 dev_err(&pdev->dev, "failed to configure pins"); 5126 goto err; 5127 } 5128 5129 of_node_put(ep); 5130 5131 return 0; 5132 5133 err: 5134 of_node_put(ep); 5135 return r; 5136 } 5137 5138 static const struct dss_pll_ops dsi_pll_ops = { 5139 .enable = dsi_pll_enable, 5140 .disable = dsi_pll_disable, 5141 .set_config = dss_pll_write_config_type_a, 5142 }; 5143 5144 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5145 .type = DSS_PLL_TYPE_A, 5146 5147 .n_max = (1 << 7) - 1, 5148 .m_max = (1 << 11) - 1, 5149 .mX_max = (1 << 4) - 1, 5150 .fint_min = 750000, 5151 .fint_max = 2100000, 5152 .clkdco_low = 1000000000, 5153 .clkdco_max = 1800000000, 5154 5155 .n_msb = 7, 5156 .n_lsb = 1, 5157 .m_msb = 18, 5158 .m_lsb = 8, 5159 5160 .mX_msb[0] = 22, 5161 .mX_lsb[0] = 19, 5162 .mX_msb[1] = 26, 5163 .mX_lsb[1] = 23, 5164 5165 .has_stopmode = true, 5166 .has_freqsel = true, 5167 .has_selfreqdco = false, 5168 .has_refsel = false, 5169 }; 5170 5171 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5172 .type = DSS_PLL_TYPE_A, 5173 5174 .n_max = (1 << 8) - 1, 5175 .m_max = (1 << 12) - 1, 5176 .mX_max = (1 << 5) - 1, 5177 .fint_min = 500000, 5178 .fint_max = 2500000, 5179 .clkdco_low = 1000000000, 5180 .clkdco_max = 1800000000, 5181 5182 .n_msb = 8, 5183 .n_lsb = 1, 5184 .m_msb = 20, 5185 .m_lsb = 9, 5186 5187 .mX_msb[0] = 25, 5188 .mX_lsb[0] = 21, 5189 .mX_msb[1] = 30, 5190 .mX_lsb[1] = 26, 5191 5192 .has_stopmode = true, 5193 .has_freqsel = false, 5194 .has_selfreqdco = false, 5195 .has_refsel = false, 5196 }; 5197 5198 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5199 .type = DSS_PLL_TYPE_A, 5200 5201 .n_max = (1 << 8) - 1, 5202 .m_max = (1 << 12) - 1, 5203 .mX_max = (1 << 5) - 1, 5204 .fint_min = 150000, 5205 .fint_max = 52000000, 5206 .clkdco_low = 1000000000, 5207 .clkdco_max = 1800000000, 5208 5209 .n_msb = 8, 5210 .n_lsb = 1, 5211 .m_msb = 20, 5212 .m_lsb = 9, 5213 5214 .mX_msb[0] = 25, 5215 .mX_lsb[0] = 21, 5216 .mX_msb[1] = 30, 5217 .mX_lsb[1] = 26, 5218 5219 .has_stopmode = true, 5220 .has_freqsel = false, 5221 .has_selfreqdco = true, 5222 .has_refsel = true, 5223 }; 5224 5225 static int dsi_init_pll_data(struct platform_device *dsidev) 5226 { 5227 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5228 struct dss_pll *pll = &dsi->pll; 5229 struct clk *clk; 5230 int r; 5231 5232 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5233 if (IS_ERR(clk)) { 5234 DSSERR("can't get sys_clk\n"); 5235 return PTR_ERR(clk); 5236 } 5237 5238 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5239 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5240 pll->clkin = clk; 5241 pll->base = dsi->pll_base; 5242 5243 switch (omapdss_get_version()) { 5244 case OMAPDSS_VER_OMAP34xx_ES1: 5245 case OMAPDSS_VER_OMAP34xx_ES3: 5246 case OMAPDSS_VER_OMAP3630: 5247 case OMAPDSS_VER_AM35xx: 5248 pll->hw = &dss_omap3_dsi_pll_hw; 5249 break; 5250 5251 case OMAPDSS_VER_OMAP4430_ES1: 5252 case OMAPDSS_VER_OMAP4430_ES2: 5253 case OMAPDSS_VER_OMAP4: 5254 pll->hw = &dss_omap4_dsi_pll_hw; 5255 break; 5256 5257 case OMAPDSS_VER_OMAP5: 5258 pll->hw = &dss_omap5_dsi_pll_hw; 5259 break; 5260 5261 default: 5262 return -ENODEV; 5263 } 5264 5265 pll->ops = &dsi_pll_ops; 5266 5267 r = dss_pll_register(pll); 5268 if (r) 5269 return r; 5270 5271 return 0; 5272 } 5273 5274 /* DSI1 HW IP initialisation */ 5275 static int dsi_bind(struct device *dev, struct device *master, void *data) 5276 { 5277 struct platform_device *dsidev = to_platform_device(dev); 5278 u32 rev; 5279 int r, i; 5280 struct dsi_data *dsi; 5281 struct resource *dsi_mem; 5282 struct resource *res; 5283 struct resource temp_res; 5284 5285 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5286 if (!dsi) 5287 return -ENOMEM; 5288 5289 dsi->pdev = dsidev; 5290 dev_set_drvdata(&dsidev->dev, dsi); 5291 5292 spin_lock_init(&dsi->irq_lock); 5293 spin_lock_init(&dsi->errors_lock); 5294 dsi->errors = 0; 5295 5296 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5297 spin_lock_init(&dsi->irq_stats_lock); 5298 dsi->irq_stats.last_reset = jiffies; 5299 #endif 5300 5301 mutex_init(&dsi->lock); 5302 sema_init(&dsi->bus_lock, 1); 5303 5304 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5305 dsi_framedone_timeout_work_callback); 5306 5307 #ifdef DSI_CATCH_MISSING_TE 5308 init_timer(&dsi->te_timer); 5309 dsi->te_timer.function = dsi_te_timeout; 5310 dsi->te_timer.data = 0; 5311 #endif 5312 5313 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5314 if (!res) { 5315 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5316 if (!res) { 5317 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5318 return -EINVAL; 5319 } 5320 5321 temp_res.start = res->start; 5322 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; 5323 res = &temp_res; 5324 } 5325 5326 dsi_mem = res; 5327 5328 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, 5329 resource_size(res)); 5330 if (!dsi->proto_base) { 5331 DSSERR("can't ioremap DSI protocol engine\n"); 5332 return -ENOMEM; 5333 } 5334 5335 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5336 if (!res) { 5337 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5338 if (!res) { 5339 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5340 return -EINVAL; 5341 } 5342 5343 temp_res.start = res->start + DSI_PHY_OFFSET; 5344 temp_res.end = temp_res.start + DSI_PHY_SZ - 1; 5345 res = &temp_res; 5346 } 5347 5348 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, 5349 resource_size(res)); 5350 if (!dsi->phy_base) { 5351 DSSERR("can't ioremap DSI PHY\n"); 5352 return -ENOMEM; 5353 } 5354 5355 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5356 if (!res) { 5357 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5358 if (!res) { 5359 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5360 return -EINVAL; 5361 } 5362 5363 temp_res.start = res->start + DSI_PLL_OFFSET; 5364 temp_res.end = temp_res.start + DSI_PLL_SZ - 1; 5365 res = &temp_res; 5366 } 5367 5368 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, 5369 resource_size(res)); 5370 if (!dsi->pll_base) { 5371 DSSERR("can't ioremap DSI PLL\n"); 5372 return -ENOMEM; 5373 } 5374 5375 dsi->irq = platform_get_irq(dsi->pdev, 0); 5376 if (dsi->irq < 0) { 5377 DSSERR("platform_get_irq failed\n"); 5378 return -ENODEV; 5379 } 5380 5381 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5382 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5383 if (r < 0) { 5384 DSSERR("request_irq failed\n"); 5385 return r; 5386 } 5387 5388 if (dsidev->dev.of_node) { 5389 const struct of_device_id *match; 5390 const struct dsi_module_id_data *d; 5391 5392 match = of_match_node(dsi_of_match, dsidev->dev.of_node); 5393 if (!match) { 5394 DSSERR("unsupported DSI module\n"); 5395 return -ENODEV; 5396 } 5397 5398 d = match->data; 5399 5400 while (d->address != 0 && d->address != dsi_mem->start) 5401 d++; 5402 5403 if (d->address == 0) { 5404 DSSERR("unsupported DSI module\n"); 5405 return -ENODEV; 5406 } 5407 5408 dsi->module_id = d->id; 5409 } else { 5410 dsi->module_id = dsidev->id; 5411 } 5412 5413 /* DSI VCs initialization */ 5414 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5415 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5416 dsi->vc[i].dssdev = NULL; 5417 dsi->vc[i].vc_id = 0; 5418 } 5419 5420 r = dsi_get_clocks(dsidev); 5421 if (r) 5422 return r; 5423 5424 dsi_init_pll_data(dsidev); 5425 5426 pm_runtime_enable(&dsidev->dev); 5427 5428 r = dsi_runtime_get(dsidev); 5429 if (r) 5430 goto err_runtime_get; 5431 5432 rev = dsi_read_reg(dsidev, DSI_REVISION); 5433 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5434 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5435 5436 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5437 * of data to 3 by default */ 5438 if (dss_has_feature(FEAT_DSI_GNQ)) 5439 /* NB_DATA_LANES */ 5440 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5441 else 5442 dsi->num_lanes_supported = 3; 5443 5444 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5445 5446 dsi_init_output(dsidev); 5447 5448 if (dsidev->dev.of_node) { 5449 r = dsi_probe_of(dsidev); 5450 if (r) { 5451 DSSERR("Invalid DSI DT data\n"); 5452 goto err_probe_of; 5453 } 5454 5455 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, 5456 &dsidev->dev); 5457 if (r) 5458 DSSERR("Failed to populate DSI child devices: %d\n", r); 5459 } 5460 5461 dsi_runtime_put(dsidev); 5462 5463 if (dsi->module_id == 0) 5464 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5465 else if (dsi->module_id == 1) 5466 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5467 5468 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5469 if (dsi->module_id == 0) 5470 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5471 else if (dsi->module_id == 1) 5472 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5473 #endif 5474 5475 return 0; 5476 5477 err_probe_of: 5478 dsi_uninit_output(dsidev); 5479 dsi_runtime_put(dsidev); 5480 5481 err_runtime_get: 5482 pm_runtime_disable(&dsidev->dev); 5483 return r; 5484 } 5485 5486 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5487 { 5488 struct platform_device *dsidev = to_platform_device(dev); 5489 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5490 5491 of_platform_depopulate(&dsidev->dev); 5492 5493 WARN_ON(dsi->scp_clk_refcount > 0); 5494 5495 dss_pll_unregister(&dsi->pll); 5496 5497 dsi_uninit_output(dsidev); 5498 5499 pm_runtime_disable(&dsidev->dev); 5500 5501 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5502 regulator_disable(dsi->vdds_dsi_reg); 5503 dsi->vdds_dsi_enabled = false; 5504 } 5505 } 5506 5507 static const struct component_ops dsi_component_ops = { 5508 .bind = dsi_bind, 5509 .unbind = dsi_unbind, 5510 }; 5511 5512 static int dsi_probe(struct platform_device *pdev) 5513 { 5514 return component_add(&pdev->dev, &dsi_component_ops); 5515 } 5516 5517 static int dsi_remove(struct platform_device *pdev) 5518 { 5519 component_del(&pdev->dev, &dsi_component_ops); 5520 return 0; 5521 } 5522 5523 static int dsi_runtime_suspend(struct device *dev) 5524 { 5525 struct platform_device *pdev = to_platform_device(dev); 5526 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5527 5528 dsi->is_enabled = false; 5529 /* ensure the irq handler sees the is_enabled value */ 5530 smp_wmb(); 5531 /* wait for current handler to finish before turning the DSI off */ 5532 synchronize_irq(dsi->irq); 5533 5534 dispc_runtime_put(); 5535 5536 return 0; 5537 } 5538 5539 static int dsi_runtime_resume(struct device *dev) 5540 { 5541 struct platform_device *pdev = to_platform_device(dev); 5542 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5543 int r; 5544 5545 r = dispc_runtime_get(); 5546 if (r) 5547 return r; 5548 5549 dsi->is_enabled = true; 5550 /* ensure the irq handler sees the is_enabled value */ 5551 smp_wmb(); 5552 5553 return 0; 5554 } 5555 5556 static const struct dev_pm_ops dsi_pm_ops = { 5557 .runtime_suspend = dsi_runtime_suspend, 5558 .runtime_resume = dsi_runtime_resume, 5559 }; 5560 5561 static const struct dsi_module_id_data dsi_of_data_omap3[] = { 5562 { .address = 0x4804fc00, .id = 0, }, 5563 { }, 5564 }; 5565 5566 static const struct dsi_module_id_data dsi_of_data_omap4[] = { 5567 { .address = 0x58004000, .id = 0, }, 5568 { .address = 0x58005000, .id = 1, }, 5569 { }, 5570 }; 5571 5572 static const struct dsi_module_id_data dsi_of_data_omap5[] = { 5573 { .address = 0x58004000, .id = 0, }, 5574 { .address = 0x58009000, .id = 1, }, 5575 { }, 5576 }; 5577 5578 static const struct of_device_id dsi_of_match[] = { 5579 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, 5580 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, 5581 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, 5582 {}, 5583 }; 5584 5585 static struct platform_driver omap_dsihw_driver = { 5586 .probe = dsi_probe, 5587 .remove = dsi_remove, 5588 .driver = { 5589 .name = "omapdss_dsi", 5590 .pm = &dsi_pm_ops, 5591 .of_match_table = dsi_of_match, 5592 .suppress_bind_attrs = true, 5593 }, 5594 }; 5595 5596 int __init dsi_init_platform_driver(void) 5597 { 5598 return platform_driver_register(&omap_dsihw_driver); 5599 } 5600 5601 void dsi_uninit_platform_driver(void) 5602 { 5603 platform_driver_unregister(&omap_dsihw_driver); 5604 } 5605