1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define DSS_SUBSYS_NAME "DSI" 19 20 #include <linux/kernel.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/device.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/mutex.h> 30 #include <linux/module.h> 31 #include <linux/semaphore.h> 32 #include <linux/seq_file.h> 33 #include <linux/platform_device.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/wait.h> 36 #include <linux/workqueue.h> 37 #include <linux/sched.h> 38 #include <linux/slab.h> 39 #include <linux/debugfs.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/of_graph.h> 43 #include <linux/of_platform.h> 44 #include <linux/component.h> 45 #include <linux/sys_soc.h> 46 47 #include <video/mipi_display.h> 48 49 #include "omapdss.h" 50 #include "dss.h" 51 52 #define DSI_CATCH_MISSING_TE 53 54 struct dsi_reg { u16 module; u16 idx; }; 55 56 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 57 58 /* DSI Protocol Engine */ 59 60 #define DSI_PROTO 0 61 #define DSI_PROTO_SZ 0x200 62 63 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 64 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 65 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 66 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 67 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 68 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 69 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 70 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 71 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 72 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 73 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 74 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 75 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 76 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 77 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 78 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 79 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 80 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 81 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 82 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 83 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 84 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 85 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 86 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 87 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 88 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 89 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 90 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 91 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 92 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 93 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 94 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 95 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 96 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 97 98 /* DSIPHY_SCP */ 99 100 #define DSI_PHY 1 101 #define DSI_PHY_OFFSET 0x200 102 #define DSI_PHY_SZ 0x40 103 104 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 105 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 106 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 107 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 108 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 109 110 /* DSI_PLL_CTRL_SCP */ 111 112 #define DSI_PLL 2 113 #define DSI_PLL_OFFSET 0x300 114 #define DSI_PLL_SZ 0x20 115 116 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 117 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 118 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 119 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 120 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 121 122 #define REG_GET(dsi, idx, start, end) \ 123 FLD_GET(dsi_read_reg(dsi, idx), start, end) 124 125 #define REG_FLD_MOD(dsi, idx, val, start, end) \ 126 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) 127 128 /* Global interrupts */ 129 #define DSI_IRQ_VC0 (1 << 0) 130 #define DSI_IRQ_VC1 (1 << 1) 131 #define DSI_IRQ_VC2 (1 << 2) 132 #define DSI_IRQ_VC3 (1 << 3) 133 #define DSI_IRQ_WAKEUP (1 << 4) 134 #define DSI_IRQ_RESYNC (1 << 5) 135 #define DSI_IRQ_PLL_LOCK (1 << 7) 136 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 137 #define DSI_IRQ_PLL_RECALL (1 << 9) 138 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 139 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 140 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 141 #define DSI_IRQ_TE_TRIGGER (1 << 16) 142 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 143 #define DSI_IRQ_SYNC_LOST (1 << 18) 144 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 145 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 146 #define DSI_IRQ_ERROR_MASK \ 147 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 148 DSI_IRQ_TA_TIMEOUT) 149 #define DSI_IRQ_CHANNEL_MASK 0xf 150 151 /* Virtual channel interrupts */ 152 #define DSI_VC_IRQ_CS (1 << 0) 153 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 154 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 155 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 156 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 157 #define DSI_VC_IRQ_BTA (1 << 5) 158 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 159 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 160 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 161 #define DSI_VC_IRQ_ERROR_MASK \ 162 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 163 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 164 DSI_VC_IRQ_FIFO_TX_UDF) 165 166 /* ComplexIO interrupts */ 167 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 168 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 169 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 170 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 171 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 172 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 173 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 174 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 175 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 176 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 177 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 178 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 179 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 180 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 181 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 182 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 183 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 184 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 185 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 186 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 195 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 196 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 198 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 199 #define DSI_CIO_IRQ_ERROR_MASK \ 200 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 201 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 202 DSI_CIO_IRQ_ERRSYNCESC5 | \ 203 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 204 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 205 DSI_CIO_IRQ_ERRESC5 | \ 206 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 207 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 208 DSI_CIO_IRQ_ERRCONTROL5 | \ 209 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 210 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 211 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 212 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 213 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 214 215 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 216 struct dsi_data; 217 218 static int dsi_display_init_dispc(struct dsi_data *dsi); 219 static void dsi_display_uninit_dispc(struct dsi_data *dsi); 220 221 static int dsi_vc_send_null(struct dsi_data *dsi, int channel); 222 223 /* DSI PLL HSDIV indices */ 224 #define HSDIV_DISPC 0 225 #define HSDIV_DSI 1 226 227 #define DSI_MAX_NR_ISRS 2 228 #define DSI_MAX_NR_LANES 5 229 230 enum dsi_model { 231 DSI_MODEL_OMAP3, 232 DSI_MODEL_OMAP4, 233 DSI_MODEL_OMAP5, 234 }; 235 236 enum dsi_lane_function { 237 DSI_LANE_UNUSED = 0, 238 DSI_LANE_CLK, 239 DSI_LANE_DATA1, 240 DSI_LANE_DATA2, 241 DSI_LANE_DATA3, 242 DSI_LANE_DATA4, 243 }; 244 245 struct dsi_lane_config { 246 enum dsi_lane_function function; 247 u8 polarity; 248 }; 249 250 struct dsi_isr_data { 251 omap_dsi_isr_t isr; 252 void *arg; 253 u32 mask; 254 }; 255 256 enum fifo_size { 257 DSI_FIFO_SIZE_0 = 0, 258 DSI_FIFO_SIZE_32 = 1, 259 DSI_FIFO_SIZE_64 = 2, 260 DSI_FIFO_SIZE_96 = 3, 261 DSI_FIFO_SIZE_128 = 4, 262 }; 263 264 enum dsi_vc_source { 265 DSI_VC_SOURCE_L4 = 0, 266 DSI_VC_SOURCE_VP, 267 }; 268 269 struct dsi_irq_stats { 270 unsigned long last_reset; 271 unsigned int irq_count; 272 unsigned int dsi_irqs[32]; 273 unsigned int vc_irqs[4][32]; 274 unsigned int cio_irqs[32]; 275 }; 276 277 struct dsi_isr_tables { 278 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 279 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 280 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 281 }; 282 283 struct dsi_clk_calc_ctx { 284 struct dsi_data *dsi; 285 struct dss_pll *pll; 286 287 /* inputs */ 288 289 const struct omap_dss_dsi_config *config; 290 291 unsigned long req_pck_min, req_pck_nom, req_pck_max; 292 293 /* outputs */ 294 295 struct dss_pll_clock_info dsi_cinfo; 296 struct dispc_clock_info dispc_cinfo; 297 298 struct videomode vm; 299 struct omap_dss_dsi_videomode_timings dsi_vm; 300 }; 301 302 struct dsi_lp_clock_info { 303 unsigned long lp_clk; 304 u16 lp_clk_div; 305 }; 306 307 struct dsi_module_id_data { 308 u32 address; 309 int id; 310 }; 311 312 enum dsi_quirks { 313 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */ 314 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1), 315 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2), 316 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3), 317 DSI_QUIRK_GNQ = (1 << 4), 318 DSI_QUIRK_PHY_DCC = (1 << 5), 319 }; 320 321 struct dsi_of_data { 322 enum dsi_model model; 323 const struct dss_pll_hw *pll_hw; 324 const struct dsi_module_id_data *modules; 325 unsigned int max_fck_freq; 326 unsigned int max_pll_lpdiv; 327 enum dsi_quirks quirks; 328 }; 329 330 struct dsi_data { 331 struct device *dev; 332 void __iomem *proto_base; 333 void __iomem *phy_base; 334 void __iomem *pll_base; 335 336 const struct dsi_of_data *data; 337 int module_id; 338 339 int irq; 340 341 bool is_enabled; 342 343 struct clk *dss_clk; 344 struct regmap *syscon; 345 struct dss_device *dss; 346 347 struct dispc_clock_info user_dispc_cinfo; 348 struct dss_pll_clock_info user_dsi_cinfo; 349 350 struct dsi_lp_clock_info user_lp_cinfo; 351 struct dsi_lp_clock_info current_lp_cinfo; 352 353 struct dss_pll pll; 354 355 bool vdds_dsi_enabled; 356 struct regulator *vdds_dsi_reg; 357 358 struct { 359 enum dsi_vc_source source; 360 struct omap_dss_device *dssdev; 361 enum fifo_size tx_fifo_size; 362 enum fifo_size rx_fifo_size; 363 int vc_id; 364 } vc[4]; 365 366 struct mutex lock; 367 struct semaphore bus_lock; 368 369 spinlock_t irq_lock; 370 struct dsi_isr_tables isr_tables; 371 /* space for a copy used by the interrupt handler */ 372 struct dsi_isr_tables isr_tables_copy; 373 374 int update_channel; 375 #ifdef DSI_PERF_MEASURE 376 unsigned int update_bytes; 377 #endif 378 379 bool te_enabled; 380 bool ulps_enabled; 381 382 void (*framedone_callback)(int, void *); 383 void *framedone_data; 384 385 struct delayed_work framedone_timeout_work; 386 387 #ifdef DSI_CATCH_MISSING_TE 388 struct timer_list te_timer; 389 #endif 390 391 unsigned long cache_req_pck; 392 unsigned long cache_clk_freq; 393 struct dss_pll_clock_info cache_cinfo; 394 395 u32 errors; 396 spinlock_t errors_lock; 397 #ifdef DSI_PERF_MEASURE 398 ktime_t perf_setup_time; 399 ktime_t perf_start_time; 400 #endif 401 int debug_read; 402 int debug_write; 403 struct { 404 struct dss_debugfs_entry *irqs; 405 struct dss_debugfs_entry *regs; 406 struct dss_debugfs_entry *clks; 407 } debugfs; 408 409 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 410 spinlock_t irq_stats_lock; 411 struct dsi_irq_stats irq_stats; 412 #endif 413 414 unsigned int num_lanes_supported; 415 unsigned int line_buffer_size; 416 417 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 418 unsigned int num_lanes_used; 419 420 unsigned int scp_clk_refcount; 421 422 struct dss_lcd_mgr_config mgr_config; 423 struct videomode vm; 424 enum omap_dss_dsi_pixel_format pix_fmt; 425 enum omap_dss_dsi_mode mode; 426 struct omap_dss_dsi_videomode_timings vm_timings; 427 428 struct omap_dss_device output; 429 }; 430 431 struct dsi_packet_sent_handler_data { 432 struct dsi_data *dsi; 433 struct completion *completion; 434 }; 435 436 #ifdef DSI_PERF_MEASURE 437 static bool dsi_perf; 438 module_param(dsi_perf, bool, 0644); 439 #endif 440 441 static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev) 442 { 443 return dev_get_drvdata(dssdev->dev); 444 } 445 446 static inline void dsi_write_reg(struct dsi_data *dsi, 447 const struct dsi_reg idx, u32 val) 448 { 449 void __iomem *base; 450 451 switch(idx.module) { 452 case DSI_PROTO: base = dsi->proto_base; break; 453 case DSI_PHY: base = dsi->phy_base; break; 454 case DSI_PLL: base = dsi->pll_base; break; 455 default: return; 456 } 457 458 __raw_writel(val, base + idx.idx); 459 } 460 461 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx) 462 { 463 void __iomem *base; 464 465 switch(idx.module) { 466 case DSI_PROTO: base = dsi->proto_base; break; 467 case DSI_PHY: base = dsi->phy_base; break; 468 case DSI_PLL: base = dsi->pll_base; break; 469 default: return 0; 470 } 471 472 return __raw_readl(base + idx.idx); 473 } 474 475 static void dsi_bus_lock(struct omap_dss_device *dssdev) 476 { 477 struct dsi_data *dsi = to_dsi_data(dssdev); 478 479 down(&dsi->bus_lock); 480 } 481 482 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 483 { 484 struct dsi_data *dsi = to_dsi_data(dssdev); 485 486 up(&dsi->bus_lock); 487 } 488 489 static bool dsi_bus_is_locked(struct dsi_data *dsi) 490 { 491 return dsi->bus_lock.count == 0; 492 } 493 494 static void dsi_completion_handler(void *data, u32 mask) 495 { 496 complete((struct completion *)data); 497 } 498 499 static inline bool wait_for_bit_change(struct dsi_data *dsi, 500 const struct dsi_reg idx, 501 int bitnum, int value) 502 { 503 unsigned long timeout; 504 ktime_t wait; 505 int t; 506 507 /* first busyloop to see if the bit changes right away */ 508 t = 100; 509 while (t-- > 0) { 510 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 511 return true; 512 } 513 514 /* then loop for 500ms, sleeping for 1ms in between */ 515 timeout = jiffies + msecs_to_jiffies(500); 516 while (time_before(jiffies, timeout)) { 517 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 518 return true; 519 520 wait = ns_to_ktime(1000 * 1000); 521 set_current_state(TASK_UNINTERRUPTIBLE); 522 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 523 } 524 525 return false; 526 } 527 528 static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 529 { 530 switch (fmt) { 531 case OMAP_DSS_DSI_FMT_RGB888: 532 case OMAP_DSS_DSI_FMT_RGB666: 533 return 24; 534 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 535 return 18; 536 case OMAP_DSS_DSI_FMT_RGB565: 537 return 16; 538 default: 539 BUG(); 540 return 0; 541 } 542 } 543 544 #ifdef DSI_PERF_MEASURE 545 static void dsi_perf_mark_setup(struct dsi_data *dsi) 546 { 547 dsi->perf_setup_time = ktime_get(); 548 } 549 550 static void dsi_perf_mark_start(struct dsi_data *dsi) 551 { 552 dsi->perf_start_time = ktime_get(); 553 } 554 555 static void dsi_perf_show(struct dsi_data *dsi, const char *name) 556 { 557 ktime_t t, setup_time, trans_time; 558 u32 total_bytes; 559 u32 setup_us, trans_us, total_us; 560 561 if (!dsi_perf) 562 return; 563 564 t = ktime_get(); 565 566 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 567 setup_us = (u32)ktime_to_us(setup_time); 568 if (setup_us == 0) 569 setup_us = 1; 570 571 trans_time = ktime_sub(t, dsi->perf_start_time); 572 trans_us = (u32)ktime_to_us(trans_time); 573 if (trans_us == 0) 574 trans_us = 1; 575 576 total_us = setup_us + trans_us; 577 578 total_bytes = dsi->update_bytes; 579 580 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 581 name, 582 setup_us, 583 trans_us, 584 total_us, 585 1000 * 1000 / total_us, 586 total_bytes, 587 total_bytes * 1000 / total_us); 588 } 589 #else 590 static inline void dsi_perf_mark_setup(struct dsi_data *dsi) 591 { 592 } 593 594 static inline void dsi_perf_mark_start(struct dsi_data *dsi) 595 { 596 } 597 598 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name) 599 { 600 } 601 #endif 602 603 static int verbose_irq; 604 605 static void print_irq_status(u32 status) 606 { 607 if (status == 0) 608 return; 609 610 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 611 return; 612 613 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 614 615 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 616 status, 617 verbose_irq ? PIS(VC0) : "", 618 verbose_irq ? PIS(VC1) : "", 619 verbose_irq ? PIS(VC2) : "", 620 verbose_irq ? PIS(VC3) : "", 621 PIS(WAKEUP), 622 PIS(RESYNC), 623 PIS(PLL_LOCK), 624 PIS(PLL_UNLOCK), 625 PIS(PLL_RECALL), 626 PIS(COMPLEXIO_ERR), 627 PIS(HS_TX_TIMEOUT), 628 PIS(LP_RX_TIMEOUT), 629 PIS(TE_TRIGGER), 630 PIS(ACK_TRIGGER), 631 PIS(SYNC_LOST), 632 PIS(LDO_POWER_GOOD), 633 PIS(TA_TIMEOUT)); 634 #undef PIS 635 } 636 637 static void print_irq_status_vc(int channel, u32 status) 638 { 639 if (status == 0) 640 return; 641 642 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 643 return; 644 645 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 646 647 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 648 channel, 649 status, 650 PIS(CS), 651 PIS(ECC_CORR), 652 PIS(ECC_NO_CORR), 653 verbose_irq ? PIS(PACKET_SENT) : "", 654 PIS(BTA), 655 PIS(FIFO_TX_OVF), 656 PIS(FIFO_RX_OVF), 657 PIS(FIFO_TX_UDF), 658 PIS(PP_BUSY_CHANGE)); 659 #undef PIS 660 } 661 662 static void print_irq_status_cio(u32 status) 663 { 664 if (status == 0) 665 return; 666 667 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 668 669 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 670 status, 671 PIS(ERRSYNCESC1), 672 PIS(ERRSYNCESC2), 673 PIS(ERRSYNCESC3), 674 PIS(ERRESC1), 675 PIS(ERRESC2), 676 PIS(ERRESC3), 677 PIS(ERRCONTROL1), 678 PIS(ERRCONTROL2), 679 PIS(ERRCONTROL3), 680 PIS(STATEULPS1), 681 PIS(STATEULPS2), 682 PIS(STATEULPS3), 683 PIS(ERRCONTENTIONLP0_1), 684 PIS(ERRCONTENTIONLP1_1), 685 PIS(ERRCONTENTIONLP0_2), 686 PIS(ERRCONTENTIONLP1_2), 687 PIS(ERRCONTENTIONLP0_3), 688 PIS(ERRCONTENTIONLP1_3), 689 PIS(ULPSACTIVENOT_ALL0), 690 PIS(ULPSACTIVENOT_ALL1)); 691 #undef PIS 692 } 693 694 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 695 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus, 696 u32 *vcstatus, u32 ciostatus) 697 { 698 int i; 699 700 spin_lock(&dsi->irq_stats_lock); 701 702 dsi->irq_stats.irq_count++; 703 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 704 705 for (i = 0; i < 4; ++i) 706 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 707 708 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 709 710 spin_unlock(&dsi->irq_stats_lock); 711 } 712 #else 713 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus) 714 #endif 715 716 static int debug_irq; 717 718 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus, 719 u32 *vcstatus, u32 ciostatus) 720 { 721 int i; 722 723 if (irqstatus & DSI_IRQ_ERROR_MASK) { 724 DSSERR("DSI error, irqstatus %x\n", irqstatus); 725 print_irq_status(irqstatus); 726 spin_lock(&dsi->errors_lock); 727 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 728 spin_unlock(&dsi->errors_lock); 729 } else if (debug_irq) { 730 print_irq_status(irqstatus); 731 } 732 733 for (i = 0; i < 4; ++i) { 734 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 735 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 736 i, vcstatus[i]); 737 print_irq_status_vc(i, vcstatus[i]); 738 } else if (debug_irq) { 739 print_irq_status_vc(i, vcstatus[i]); 740 } 741 } 742 743 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 744 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 745 print_irq_status_cio(ciostatus); 746 } else if (debug_irq) { 747 print_irq_status_cio(ciostatus); 748 } 749 } 750 751 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 752 unsigned int isr_array_size, u32 irqstatus) 753 { 754 struct dsi_isr_data *isr_data; 755 int i; 756 757 for (i = 0; i < isr_array_size; i++) { 758 isr_data = &isr_array[i]; 759 if (isr_data->isr && isr_data->mask & irqstatus) 760 isr_data->isr(isr_data->arg, irqstatus); 761 } 762 } 763 764 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 765 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 766 { 767 int i; 768 769 dsi_call_isrs(isr_tables->isr_table, 770 ARRAY_SIZE(isr_tables->isr_table), 771 irqstatus); 772 773 for (i = 0; i < 4; ++i) { 774 if (vcstatus[i] == 0) 775 continue; 776 dsi_call_isrs(isr_tables->isr_table_vc[i], 777 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 778 vcstatus[i]); 779 } 780 781 if (ciostatus != 0) 782 dsi_call_isrs(isr_tables->isr_table_cio, 783 ARRAY_SIZE(isr_tables->isr_table_cio), 784 ciostatus); 785 } 786 787 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 788 { 789 struct dsi_data *dsi = arg; 790 u32 irqstatus, vcstatus[4], ciostatus; 791 int i; 792 793 if (!dsi->is_enabled) 794 return IRQ_NONE; 795 796 spin_lock(&dsi->irq_lock); 797 798 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS); 799 800 /* IRQ is not for us */ 801 if (!irqstatus) { 802 spin_unlock(&dsi->irq_lock); 803 return IRQ_NONE; 804 } 805 806 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 807 /* flush posted write */ 808 dsi_read_reg(dsi, DSI_IRQSTATUS); 809 810 for (i = 0; i < 4; ++i) { 811 if ((irqstatus & (1 << i)) == 0) { 812 vcstatus[i] = 0; 813 continue; 814 } 815 816 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 817 818 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]); 819 /* flush posted write */ 820 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 821 } 822 823 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 824 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 825 826 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 827 /* flush posted write */ 828 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 829 } else { 830 ciostatus = 0; 831 } 832 833 #ifdef DSI_CATCH_MISSING_TE 834 if (irqstatus & DSI_IRQ_TE_TRIGGER) 835 del_timer(&dsi->te_timer); 836 #endif 837 838 /* make a copy and unlock, so that isrs can unregister 839 * themselves */ 840 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 841 sizeof(dsi->isr_tables)); 842 843 spin_unlock(&dsi->irq_lock); 844 845 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 846 847 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus); 848 849 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus); 850 851 return IRQ_HANDLED; 852 } 853 854 /* dsi->irq_lock has to be locked by the caller */ 855 static void _omap_dsi_configure_irqs(struct dsi_data *dsi, 856 struct dsi_isr_data *isr_array, 857 unsigned int isr_array_size, 858 u32 default_mask, 859 const struct dsi_reg enable_reg, 860 const struct dsi_reg status_reg) 861 { 862 struct dsi_isr_data *isr_data; 863 u32 mask; 864 u32 old_mask; 865 int i; 866 867 mask = default_mask; 868 869 for (i = 0; i < isr_array_size; i++) { 870 isr_data = &isr_array[i]; 871 872 if (isr_data->isr == NULL) 873 continue; 874 875 mask |= isr_data->mask; 876 } 877 878 old_mask = dsi_read_reg(dsi, enable_reg); 879 /* clear the irqstatus for newly enabled irqs */ 880 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); 881 dsi_write_reg(dsi, enable_reg, mask); 882 883 /* flush posted writes */ 884 dsi_read_reg(dsi, enable_reg); 885 dsi_read_reg(dsi, status_reg); 886 } 887 888 /* dsi->irq_lock has to be locked by the caller */ 889 static void _omap_dsi_set_irqs(struct dsi_data *dsi) 890 { 891 u32 mask = DSI_IRQ_ERROR_MASK; 892 #ifdef DSI_CATCH_MISSING_TE 893 mask |= DSI_IRQ_TE_TRIGGER; 894 #endif 895 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, 896 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 897 DSI_IRQENABLE, DSI_IRQSTATUS); 898 } 899 900 /* dsi->irq_lock has to be locked by the caller */ 901 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc) 902 { 903 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], 904 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 905 DSI_VC_IRQ_ERROR_MASK, 906 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 907 } 908 909 /* dsi->irq_lock has to be locked by the caller */ 910 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi) 911 { 912 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, 913 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 914 DSI_CIO_IRQ_ERROR_MASK, 915 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 916 } 917 918 static void _dsi_initialize_irq(struct dsi_data *dsi) 919 { 920 unsigned long flags; 921 int vc; 922 923 spin_lock_irqsave(&dsi->irq_lock, flags); 924 925 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 926 927 _omap_dsi_set_irqs(dsi); 928 for (vc = 0; vc < 4; ++vc) 929 _omap_dsi_set_irqs_vc(dsi, vc); 930 _omap_dsi_set_irqs_cio(dsi); 931 932 spin_unlock_irqrestore(&dsi->irq_lock, flags); 933 } 934 935 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 936 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 937 { 938 struct dsi_isr_data *isr_data; 939 int free_idx; 940 int i; 941 942 BUG_ON(isr == NULL); 943 944 /* check for duplicate entry and find a free slot */ 945 free_idx = -1; 946 for (i = 0; i < isr_array_size; i++) { 947 isr_data = &isr_array[i]; 948 949 if (isr_data->isr == isr && isr_data->arg == arg && 950 isr_data->mask == mask) { 951 return -EINVAL; 952 } 953 954 if (isr_data->isr == NULL && free_idx == -1) 955 free_idx = i; 956 } 957 958 if (free_idx == -1) 959 return -EBUSY; 960 961 isr_data = &isr_array[free_idx]; 962 isr_data->isr = isr; 963 isr_data->arg = arg; 964 isr_data->mask = mask; 965 966 return 0; 967 } 968 969 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 970 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 971 { 972 struct dsi_isr_data *isr_data; 973 int i; 974 975 for (i = 0; i < isr_array_size; i++) { 976 isr_data = &isr_array[i]; 977 if (isr_data->isr != isr || isr_data->arg != arg || 978 isr_data->mask != mask) 979 continue; 980 981 isr_data->isr = NULL; 982 isr_data->arg = NULL; 983 isr_data->mask = 0; 984 985 return 0; 986 } 987 988 return -EINVAL; 989 } 990 991 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 992 void *arg, u32 mask) 993 { 994 unsigned long flags; 995 int r; 996 997 spin_lock_irqsave(&dsi->irq_lock, flags); 998 999 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1000 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1001 1002 if (r == 0) 1003 _omap_dsi_set_irqs(dsi); 1004 1005 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1006 1007 return r; 1008 } 1009 1010 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 1011 void *arg, u32 mask) 1012 { 1013 unsigned long flags; 1014 int r; 1015 1016 spin_lock_irqsave(&dsi->irq_lock, flags); 1017 1018 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1019 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1020 1021 if (r == 0) 1022 _omap_dsi_set_irqs(dsi); 1023 1024 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1025 1026 return r; 1027 } 1028 1029 static int dsi_register_isr_vc(struct dsi_data *dsi, int channel, 1030 omap_dsi_isr_t isr, void *arg, u32 mask) 1031 { 1032 unsigned long flags; 1033 int r; 1034 1035 spin_lock_irqsave(&dsi->irq_lock, flags); 1036 1037 r = _dsi_register_isr(isr, arg, mask, 1038 dsi->isr_tables.isr_table_vc[channel], 1039 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1040 1041 if (r == 0) 1042 _omap_dsi_set_irqs_vc(dsi, channel); 1043 1044 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1045 1046 return r; 1047 } 1048 1049 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel, 1050 omap_dsi_isr_t isr, void *arg, u32 mask) 1051 { 1052 unsigned long flags; 1053 int r; 1054 1055 spin_lock_irqsave(&dsi->irq_lock, flags); 1056 1057 r = _dsi_unregister_isr(isr, arg, mask, 1058 dsi->isr_tables.isr_table_vc[channel], 1059 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1060 1061 if (r == 0) 1062 _omap_dsi_set_irqs_vc(dsi, channel); 1063 1064 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1065 1066 return r; 1067 } 1068 1069 static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, 1070 void *arg, u32 mask) 1071 { 1072 unsigned long flags; 1073 int r; 1074 1075 spin_lock_irqsave(&dsi->irq_lock, flags); 1076 1077 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1078 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1079 1080 if (r == 0) 1081 _omap_dsi_set_irqs_cio(dsi); 1082 1083 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1084 1085 return r; 1086 } 1087 1088 static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, 1089 void *arg, u32 mask) 1090 { 1091 unsigned long flags; 1092 int r; 1093 1094 spin_lock_irqsave(&dsi->irq_lock, flags); 1095 1096 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1097 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1098 1099 if (r == 0) 1100 _omap_dsi_set_irqs_cio(dsi); 1101 1102 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1103 1104 return r; 1105 } 1106 1107 static u32 dsi_get_errors(struct dsi_data *dsi) 1108 { 1109 unsigned long flags; 1110 u32 e; 1111 1112 spin_lock_irqsave(&dsi->errors_lock, flags); 1113 e = dsi->errors; 1114 dsi->errors = 0; 1115 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1116 return e; 1117 } 1118 1119 static int dsi_runtime_get(struct dsi_data *dsi) 1120 { 1121 int r; 1122 1123 DSSDBG("dsi_runtime_get\n"); 1124 1125 r = pm_runtime_get_sync(dsi->dev); 1126 WARN_ON(r < 0); 1127 return r < 0 ? r : 0; 1128 } 1129 1130 static void dsi_runtime_put(struct dsi_data *dsi) 1131 { 1132 int r; 1133 1134 DSSDBG("dsi_runtime_put\n"); 1135 1136 r = pm_runtime_put_sync(dsi->dev); 1137 WARN_ON(r < 0 && r != -ENOSYS); 1138 } 1139 1140 static void _dsi_print_reset_status(struct dsi_data *dsi) 1141 { 1142 u32 l; 1143 int b0, b1, b2; 1144 1145 /* A dummy read using the SCP interface to any DSIPHY register is 1146 * required after DSIPHY reset to complete the reset of the DSI complex 1147 * I/O. */ 1148 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1149 1150 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 1151 b0 = 28; 1152 b1 = 27; 1153 b2 = 26; 1154 } else { 1155 b0 = 24; 1156 b1 = 25; 1157 b2 = 26; 1158 } 1159 1160 #define DSI_FLD_GET(fld, start, end)\ 1161 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) 1162 1163 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1164 DSI_FLD_GET(PLL_STATUS, 0, 0), 1165 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1166 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1167 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1168 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1169 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1170 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1171 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1172 1173 #undef DSI_FLD_GET 1174 } 1175 1176 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable) 1177 { 1178 DSSDBG("dsi_if_enable(%d)\n", enable); 1179 1180 enable = enable ? 1 : 0; 1181 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1182 1183 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) { 1184 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1185 return -EIO; 1186 } 1187 1188 return 0; 1189 } 1190 1191 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi) 1192 { 1193 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1194 } 1195 1196 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi) 1197 { 1198 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1199 } 1200 1201 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi) 1202 { 1203 return dsi->pll.cinfo.clkdco / 16; 1204 } 1205 1206 static unsigned long dsi_fclk_rate(struct dsi_data *dsi) 1207 { 1208 unsigned long r; 1209 enum dss_clk_source source; 1210 1211 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); 1212 if (source == DSS_CLK_SRC_FCK) { 1213 /* DSI FCLK source is DSS_CLK_FCK */ 1214 r = clk_get_rate(dsi->dss_clk); 1215 } else { 1216 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1217 r = dsi_get_pll_hsdiv_dsi_rate(dsi); 1218 } 1219 1220 return r; 1221 } 1222 1223 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1224 unsigned long lp_clk_min, unsigned long lp_clk_max, 1225 struct dsi_lp_clock_info *lp_cinfo) 1226 { 1227 unsigned int lp_clk_div; 1228 unsigned long lp_clk; 1229 1230 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1231 lp_clk = dsi_fclk / 2 / lp_clk_div; 1232 1233 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1234 return -EINVAL; 1235 1236 lp_cinfo->lp_clk_div = lp_clk_div; 1237 lp_cinfo->lp_clk = lp_clk; 1238 1239 return 0; 1240 } 1241 1242 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi) 1243 { 1244 unsigned long dsi_fclk; 1245 unsigned int lp_clk_div; 1246 unsigned long lp_clk; 1247 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; 1248 1249 1250 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1251 1252 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1253 return -EINVAL; 1254 1255 dsi_fclk = dsi_fclk_rate(dsi); 1256 1257 lp_clk = dsi_fclk / 2 / lp_clk_div; 1258 1259 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1260 dsi->current_lp_cinfo.lp_clk = lp_clk; 1261 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1262 1263 /* LP_CLK_DIVISOR */ 1264 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1265 1266 /* LP_RX_SYNCHRO_ENABLE */ 1267 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1268 1269 return 0; 1270 } 1271 1272 static void dsi_enable_scp_clk(struct dsi_data *dsi) 1273 { 1274 if (dsi->scp_clk_refcount++ == 0) 1275 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1276 } 1277 1278 static void dsi_disable_scp_clk(struct dsi_data *dsi) 1279 { 1280 WARN_ON(dsi->scp_clk_refcount == 0); 1281 if (--dsi->scp_clk_refcount == 0) 1282 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1283 } 1284 1285 enum dsi_pll_power_state { 1286 DSI_PLL_POWER_OFF = 0x0, 1287 DSI_PLL_POWER_ON_HSCLK = 0x1, 1288 DSI_PLL_POWER_ON_ALL = 0x2, 1289 DSI_PLL_POWER_ON_DIV = 0x3, 1290 }; 1291 1292 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state) 1293 { 1294 int t = 0; 1295 1296 /* DSI-PLL power command 0x3 is not working */ 1297 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && 1298 state == DSI_PLL_POWER_ON_DIV) 1299 state = DSI_PLL_POWER_ON_ALL; 1300 1301 /* PLL_PWR_CMD */ 1302 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); 1303 1304 /* PLL_PWR_STATUS */ 1305 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { 1306 if (++t > 1000) { 1307 DSSERR("Failed to set DSI PLL power mode to %d\n", 1308 state); 1309 return -ENODEV; 1310 } 1311 udelay(1); 1312 } 1313 1314 return 0; 1315 } 1316 1317 1318 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, 1319 struct dss_pll_clock_info *cinfo) 1320 { 1321 unsigned long max_dsi_fck; 1322 1323 max_dsi_fck = dsi->data->max_fck_freq; 1324 1325 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1326 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1327 } 1328 1329 static int dsi_pll_enable(struct dss_pll *pll) 1330 { 1331 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1332 int r = 0; 1333 1334 DSSDBG("PLL init\n"); 1335 1336 r = dsi_runtime_get(dsi); 1337 if (r) 1338 return r; 1339 1340 /* 1341 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1342 */ 1343 dsi_enable_scp_clk(dsi); 1344 1345 r = regulator_enable(dsi->vdds_dsi_reg); 1346 if (r) 1347 goto err0; 1348 1349 /* XXX PLL does not come out of reset without this... */ 1350 dispc_pck_free_enable(dsi->dss->dispc, 1); 1351 1352 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) { 1353 DSSERR("PLL not coming out of reset.\n"); 1354 r = -ENODEV; 1355 dispc_pck_free_enable(dsi->dss->dispc, 0); 1356 goto err1; 1357 } 1358 1359 /* XXX ... but if left on, we get problems when planes do not 1360 * fill the whole display. No idea about this */ 1361 dispc_pck_free_enable(dsi->dss->dispc, 0); 1362 1363 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL); 1364 1365 if (r) 1366 goto err1; 1367 1368 DSSDBG("PLL init done\n"); 1369 1370 return 0; 1371 err1: 1372 regulator_disable(dsi->vdds_dsi_reg); 1373 err0: 1374 dsi_disable_scp_clk(dsi); 1375 dsi_runtime_put(dsi); 1376 return r; 1377 } 1378 1379 static void dsi_pll_disable(struct dss_pll *pll) 1380 { 1381 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1382 1383 dsi_pll_power(dsi, DSI_PLL_POWER_OFF); 1384 1385 regulator_disable(dsi->vdds_dsi_reg); 1386 1387 dsi_disable_scp_clk(dsi); 1388 dsi_runtime_put(dsi); 1389 1390 DSSDBG("PLL disable done\n"); 1391 } 1392 1393 static int dsi_dump_dsi_clocks(struct seq_file *s, void *p) 1394 { 1395 struct dsi_data *dsi = s->private; 1396 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1397 enum dss_clk_source dispc_clk_src, dsi_clk_src; 1398 int dsi_module = dsi->module_id; 1399 struct dss_pll *pll = &dsi->pll; 1400 1401 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); 1402 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); 1403 1404 if (dsi_runtime_get(dsi)) 1405 return 0; 1406 1407 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1408 1409 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1410 1411 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1412 1413 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1414 cinfo->clkdco, cinfo->m); 1415 1416 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1417 dss_get_clk_source_name(dsi_module == 0 ? 1418 DSS_CLK_SRC_PLL1_1 : 1419 DSS_CLK_SRC_PLL2_1), 1420 cinfo->clkout[HSDIV_DISPC], 1421 cinfo->mX[HSDIV_DISPC], 1422 dispc_clk_src == DSS_CLK_SRC_FCK ? 1423 "off" : "on"); 1424 1425 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1426 dss_get_clk_source_name(dsi_module == 0 ? 1427 DSS_CLK_SRC_PLL1_2 : 1428 DSS_CLK_SRC_PLL2_2), 1429 cinfo->clkout[HSDIV_DSI], 1430 cinfo->mX[HSDIV_DSI], 1431 dsi_clk_src == DSS_CLK_SRC_FCK ? 1432 "off" : "on"); 1433 1434 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1435 1436 seq_printf(s, "dsi fclk source = %s\n", 1437 dss_get_clk_source_name(dsi_clk_src)); 1438 1439 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi)); 1440 1441 seq_printf(s, "DDR_CLK\t\t%lu\n", 1442 cinfo->clkdco / 4); 1443 1444 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi)); 1445 1446 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1447 1448 dsi_runtime_put(dsi); 1449 1450 return 0; 1451 } 1452 1453 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1454 static int dsi_dump_dsi_irqs(struct seq_file *s, void *p) 1455 { 1456 struct dsi_data *dsi = s->private; 1457 unsigned long flags; 1458 struct dsi_irq_stats stats; 1459 1460 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1461 1462 stats = dsi->irq_stats; 1463 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1464 dsi->irq_stats.last_reset = jiffies; 1465 1466 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1467 1468 seq_printf(s, "period %u ms\n", 1469 jiffies_to_msecs(jiffies - stats.last_reset)); 1470 1471 seq_printf(s, "irqs %d\n", stats.irq_count); 1472 #define PIS(x) \ 1473 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1474 1475 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1476 PIS(VC0); 1477 PIS(VC1); 1478 PIS(VC2); 1479 PIS(VC3); 1480 PIS(WAKEUP); 1481 PIS(RESYNC); 1482 PIS(PLL_LOCK); 1483 PIS(PLL_UNLOCK); 1484 PIS(PLL_RECALL); 1485 PIS(COMPLEXIO_ERR); 1486 PIS(HS_TX_TIMEOUT); 1487 PIS(LP_RX_TIMEOUT); 1488 PIS(TE_TRIGGER); 1489 PIS(ACK_TRIGGER); 1490 PIS(SYNC_LOST); 1491 PIS(LDO_POWER_GOOD); 1492 PIS(TA_TIMEOUT); 1493 #undef PIS 1494 1495 #define PIS(x) \ 1496 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1497 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1498 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1499 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1500 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1501 1502 seq_printf(s, "-- VC interrupts --\n"); 1503 PIS(CS); 1504 PIS(ECC_CORR); 1505 PIS(PACKET_SENT); 1506 PIS(FIFO_TX_OVF); 1507 PIS(FIFO_RX_OVF); 1508 PIS(BTA); 1509 PIS(ECC_NO_CORR); 1510 PIS(FIFO_TX_UDF); 1511 PIS(PP_BUSY_CHANGE); 1512 #undef PIS 1513 1514 #define PIS(x) \ 1515 seq_printf(s, "%-20s %10d\n", #x, \ 1516 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1517 1518 seq_printf(s, "-- CIO interrupts --\n"); 1519 PIS(ERRSYNCESC1); 1520 PIS(ERRSYNCESC2); 1521 PIS(ERRSYNCESC3); 1522 PIS(ERRESC1); 1523 PIS(ERRESC2); 1524 PIS(ERRESC3); 1525 PIS(ERRCONTROL1); 1526 PIS(ERRCONTROL2); 1527 PIS(ERRCONTROL3); 1528 PIS(STATEULPS1); 1529 PIS(STATEULPS2); 1530 PIS(STATEULPS3); 1531 PIS(ERRCONTENTIONLP0_1); 1532 PIS(ERRCONTENTIONLP1_1); 1533 PIS(ERRCONTENTIONLP0_2); 1534 PIS(ERRCONTENTIONLP1_2); 1535 PIS(ERRCONTENTIONLP0_3); 1536 PIS(ERRCONTENTIONLP1_3); 1537 PIS(ULPSACTIVENOT_ALL0); 1538 PIS(ULPSACTIVENOT_ALL1); 1539 #undef PIS 1540 1541 return 0; 1542 } 1543 #endif 1544 1545 static int dsi_dump_dsi_regs(struct seq_file *s, void *p) 1546 { 1547 struct dsi_data *dsi = s->private; 1548 1549 if (dsi_runtime_get(dsi)) 1550 return 0; 1551 dsi_enable_scp_clk(dsi); 1552 1553 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) 1554 DUMPREG(DSI_REVISION); 1555 DUMPREG(DSI_SYSCONFIG); 1556 DUMPREG(DSI_SYSSTATUS); 1557 DUMPREG(DSI_IRQSTATUS); 1558 DUMPREG(DSI_IRQENABLE); 1559 DUMPREG(DSI_CTRL); 1560 DUMPREG(DSI_COMPLEXIO_CFG1); 1561 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1562 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1563 DUMPREG(DSI_CLK_CTRL); 1564 DUMPREG(DSI_TIMING1); 1565 DUMPREG(DSI_TIMING2); 1566 DUMPREG(DSI_VM_TIMING1); 1567 DUMPREG(DSI_VM_TIMING2); 1568 DUMPREG(DSI_VM_TIMING3); 1569 DUMPREG(DSI_CLK_TIMING); 1570 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1571 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1572 DUMPREG(DSI_COMPLEXIO_CFG2); 1573 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1574 DUMPREG(DSI_VM_TIMING4); 1575 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1576 DUMPREG(DSI_VM_TIMING5); 1577 DUMPREG(DSI_VM_TIMING6); 1578 DUMPREG(DSI_VM_TIMING7); 1579 DUMPREG(DSI_STOPCLK_TIMING); 1580 1581 DUMPREG(DSI_VC_CTRL(0)); 1582 DUMPREG(DSI_VC_TE(0)); 1583 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1584 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1585 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1586 DUMPREG(DSI_VC_IRQSTATUS(0)); 1587 DUMPREG(DSI_VC_IRQENABLE(0)); 1588 1589 DUMPREG(DSI_VC_CTRL(1)); 1590 DUMPREG(DSI_VC_TE(1)); 1591 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1592 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1593 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1594 DUMPREG(DSI_VC_IRQSTATUS(1)); 1595 DUMPREG(DSI_VC_IRQENABLE(1)); 1596 1597 DUMPREG(DSI_VC_CTRL(2)); 1598 DUMPREG(DSI_VC_TE(2)); 1599 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1600 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1601 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1602 DUMPREG(DSI_VC_IRQSTATUS(2)); 1603 DUMPREG(DSI_VC_IRQENABLE(2)); 1604 1605 DUMPREG(DSI_VC_CTRL(3)); 1606 DUMPREG(DSI_VC_TE(3)); 1607 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1608 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1609 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1610 DUMPREG(DSI_VC_IRQSTATUS(3)); 1611 DUMPREG(DSI_VC_IRQENABLE(3)); 1612 1613 DUMPREG(DSI_DSIPHY_CFG0); 1614 DUMPREG(DSI_DSIPHY_CFG1); 1615 DUMPREG(DSI_DSIPHY_CFG2); 1616 DUMPREG(DSI_DSIPHY_CFG5); 1617 1618 DUMPREG(DSI_PLL_CONTROL); 1619 DUMPREG(DSI_PLL_STATUS); 1620 DUMPREG(DSI_PLL_GO); 1621 DUMPREG(DSI_PLL_CONFIGURATION1); 1622 DUMPREG(DSI_PLL_CONFIGURATION2); 1623 #undef DUMPREG 1624 1625 dsi_disable_scp_clk(dsi); 1626 dsi_runtime_put(dsi); 1627 1628 return 0; 1629 } 1630 1631 enum dsi_cio_power_state { 1632 DSI_COMPLEXIO_POWER_OFF = 0x0, 1633 DSI_COMPLEXIO_POWER_ON = 0x1, 1634 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1635 }; 1636 1637 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state) 1638 { 1639 int t = 0; 1640 1641 /* PWR_CMD */ 1642 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); 1643 1644 /* PWR_STATUS */ 1645 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), 1646 26, 25) != state) { 1647 if (++t > 1000) { 1648 DSSERR("failed to set complexio power state to " 1649 "%d\n", state); 1650 return -ENODEV; 1651 } 1652 udelay(1); 1653 } 1654 1655 return 0; 1656 } 1657 1658 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi) 1659 { 1660 int val; 1661 1662 /* line buffer on OMAP3 is 1024 x 24bits */ 1663 /* XXX: for some reason using full buffer size causes 1664 * considerable TX slowdown with update sizes that fill the 1665 * whole buffer */ 1666 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1667 return 1023 * 3; 1668 1669 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1670 1671 switch (val) { 1672 case 1: 1673 return 512 * 3; /* 512x24 bits */ 1674 case 2: 1675 return 682 * 3; /* 682x24 bits */ 1676 case 3: 1677 return 853 * 3; /* 853x24 bits */ 1678 case 4: 1679 return 1024 * 3; /* 1024x24 bits */ 1680 case 5: 1681 return 1194 * 3; /* 1194x24 bits */ 1682 case 6: 1683 return 1365 * 3; /* 1365x24 bits */ 1684 case 7: 1685 return 1920 * 3; /* 1920x24 bits */ 1686 default: 1687 BUG(); 1688 return 0; 1689 } 1690 } 1691 1692 static int dsi_set_lane_config(struct dsi_data *dsi) 1693 { 1694 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1695 static const enum dsi_lane_function functions[] = { 1696 DSI_LANE_CLK, 1697 DSI_LANE_DATA1, 1698 DSI_LANE_DATA2, 1699 DSI_LANE_DATA3, 1700 DSI_LANE_DATA4, 1701 }; 1702 u32 r; 1703 int i; 1704 1705 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1); 1706 1707 for (i = 0; i < dsi->num_lanes_used; ++i) { 1708 unsigned int offset = offsets[i]; 1709 unsigned int polarity, lane_number; 1710 unsigned int t; 1711 1712 for (t = 0; t < dsi->num_lanes_supported; ++t) 1713 if (dsi->lanes[t].function == functions[i]) 1714 break; 1715 1716 if (t == dsi->num_lanes_supported) 1717 return -EINVAL; 1718 1719 lane_number = t; 1720 polarity = dsi->lanes[t].polarity; 1721 1722 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1723 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1724 } 1725 1726 /* clear the unused lanes */ 1727 for (; i < dsi->num_lanes_supported; ++i) { 1728 unsigned int offset = offsets[i]; 1729 1730 r = FLD_MOD(r, 0, offset + 2, offset); 1731 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1732 } 1733 1734 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r); 1735 1736 return 0; 1737 } 1738 1739 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns) 1740 { 1741 /* convert time in ns to ddr ticks, rounding up */ 1742 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1743 1744 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1745 } 1746 1747 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) 1748 { 1749 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1750 1751 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1752 } 1753 1754 static void dsi_cio_timings(struct dsi_data *dsi) 1755 { 1756 u32 r; 1757 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1758 u32 tlpx_half, tclk_trail, tclk_zero; 1759 u32 tclk_prepare; 1760 1761 /* calculate timings */ 1762 1763 /* 1 * DDR_CLK = 2 * UI */ 1764 1765 /* min 40ns + 4*UI max 85ns + 6*UI */ 1766 ths_prepare = ns2ddr(dsi, 70) + 2; 1767 1768 /* min 145ns + 10*UI */ 1769 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2; 1770 1771 /* min max(8*UI, 60ns+4*UI) */ 1772 ths_trail = ns2ddr(dsi, 60) + 5; 1773 1774 /* min 100ns */ 1775 ths_exit = ns2ddr(dsi, 145); 1776 1777 /* tlpx min 50n */ 1778 tlpx_half = ns2ddr(dsi, 25); 1779 1780 /* min 60ns */ 1781 tclk_trail = ns2ddr(dsi, 60) + 2; 1782 1783 /* min 38ns, max 95ns */ 1784 tclk_prepare = ns2ddr(dsi, 65); 1785 1786 /* min tclk-prepare + tclk-zero = 300ns */ 1787 tclk_zero = ns2ddr(dsi, 260); 1788 1789 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1790 ths_prepare, ddr2ns(dsi, ths_prepare), 1791 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero)); 1792 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1793 ths_trail, ddr2ns(dsi, ths_trail), 1794 ths_exit, ddr2ns(dsi, ths_exit)); 1795 1796 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1797 "tclk_zero %u (%uns)\n", 1798 tlpx_half, ddr2ns(dsi, tlpx_half), 1799 tclk_trail, ddr2ns(dsi, tclk_trail), 1800 tclk_zero, ddr2ns(dsi, tclk_zero)); 1801 DSSDBG("tclk_prepare %u (%uns)\n", 1802 tclk_prepare, ddr2ns(dsi, tclk_prepare)); 1803 1804 /* program timings */ 1805 1806 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 1807 r = FLD_MOD(r, ths_prepare, 31, 24); 1808 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1809 r = FLD_MOD(r, ths_trail, 15, 8); 1810 r = FLD_MOD(r, ths_exit, 7, 0); 1811 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r); 1812 1813 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 1814 r = FLD_MOD(r, tlpx_half, 20, 16); 1815 r = FLD_MOD(r, tclk_trail, 15, 8); 1816 r = FLD_MOD(r, tclk_zero, 7, 0); 1817 1818 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { 1819 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1820 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1821 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1822 } 1823 1824 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r); 1825 1826 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 1827 r = FLD_MOD(r, tclk_prepare, 7, 0); 1828 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r); 1829 } 1830 1831 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1832 static void dsi_cio_enable_lane_override(struct dsi_data *dsi, 1833 unsigned int mask_p, 1834 unsigned int mask_n) 1835 { 1836 int i; 1837 u32 l; 1838 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1839 1840 l = 0; 1841 1842 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1843 unsigned int p = dsi->lanes[i].polarity; 1844 1845 if (mask_p & (1 << i)) 1846 l |= 1 << (i * 2 + (p ? 0 : 1)); 1847 1848 if (mask_n & (1 << i)) 1849 l |= 1 << (i * 2 + (p ? 1 : 0)); 1850 } 1851 1852 /* 1853 * Bits in REGLPTXSCPDAT4TO0DXDY: 1854 * 17: DY0 18: DX0 1855 * 19: DY1 20: DX1 1856 * 21: DY2 22: DX2 1857 * 23: DY3 24: DX3 1858 * 25: DY4 26: DX4 1859 */ 1860 1861 /* Set the lane override configuration */ 1862 1863 /* REGLPTXSCPDAT4TO0DXDY */ 1864 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1865 1866 /* Enable lane override */ 1867 1868 /* ENLPTXSCPDAT */ 1869 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27); 1870 } 1871 1872 static void dsi_cio_disable_lane_override(struct dsi_data *dsi) 1873 { 1874 /* Disable lane override */ 1875 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1876 /* Reset the lane override configuration */ 1877 /* REGLPTXSCPDAT4TO0DXDY */ 1878 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17); 1879 } 1880 1881 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi) 1882 { 1883 int t, i; 1884 bool in_use[DSI_MAX_NR_LANES]; 1885 static const u8 offsets_old[] = { 28, 27, 26 }; 1886 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 1887 const u8 *offsets; 1888 1889 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) 1890 offsets = offsets_old; 1891 else 1892 offsets = offsets_new; 1893 1894 for (i = 0; i < dsi->num_lanes_supported; ++i) 1895 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 1896 1897 t = 100000; 1898 while (true) { 1899 u32 l; 1900 int ok; 1901 1902 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1903 1904 ok = 0; 1905 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1906 if (!in_use[i] || (l & (1 << offsets[i]))) 1907 ok++; 1908 } 1909 1910 if (ok == dsi->num_lanes_supported) 1911 break; 1912 1913 if (--t == 0) { 1914 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1915 if (!in_use[i] || (l & (1 << offsets[i]))) 1916 continue; 1917 1918 DSSERR("CIO TXCLKESC%d domain not coming " \ 1919 "out of reset\n", i); 1920 } 1921 return -EIO; 1922 } 1923 } 1924 1925 return 0; 1926 } 1927 1928 /* return bitmask of enabled lanes, lane0 being the lsb */ 1929 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi) 1930 { 1931 unsigned int mask = 0; 1932 int i; 1933 1934 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1935 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 1936 mask |= 1 << i; 1937 } 1938 1939 return mask; 1940 } 1941 1942 /* OMAP4 CONTROL_DSIPHY */ 1943 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 1944 1945 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 1946 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 1947 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 1948 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 1949 #define OMAP4_DSI1_PIPD_SHIFT 19 1950 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 1951 #define OMAP4_DSI2_PIPD_SHIFT 14 1952 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 1953 1954 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1955 { 1956 u32 enable_mask, enable_shift; 1957 u32 pipd_mask, pipd_shift; 1958 1959 if (dsi->module_id == 0) { 1960 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 1961 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 1962 pipd_mask = OMAP4_DSI1_PIPD_MASK; 1963 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 1964 } else if (dsi->module_id == 1) { 1965 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 1966 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 1967 pipd_mask = OMAP4_DSI2_PIPD_MASK; 1968 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 1969 } else { 1970 return -ENODEV; 1971 } 1972 1973 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, 1974 enable_mask | pipd_mask, 1975 (lanes << enable_shift) | (lanes << pipd_shift)); 1976 } 1977 1978 /* OMAP5 CONTROL_DSIPHY */ 1979 1980 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 1981 1982 #define OMAP5_DSI1_LANEENABLE_SHIFT 24 1983 #define OMAP5_DSI2_LANEENABLE_SHIFT 19 1984 #define OMAP5_DSI_LANEENABLE_MASK 0x1f 1985 1986 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1987 { 1988 u32 enable_shift; 1989 1990 if (dsi->module_id == 0) 1991 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; 1992 else if (dsi->module_id == 1) 1993 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; 1994 else 1995 return -ENODEV; 1996 1997 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, 1998 OMAP5_DSI_LANEENABLE_MASK << enable_shift, 1999 lanes << enable_shift); 2000 } 2001 2002 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) 2003 { 2004 if (dsi->data->model == DSI_MODEL_OMAP4) 2005 return dsi_omap4_mux_pads(dsi, lane_mask); 2006 if (dsi->data->model == DSI_MODEL_OMAP5) 2007 return dsi_omap5_mux_pads(dsi, lane_mask); 2008 return 0; 2009 } 2010 2011 static void dsi_disable_pads(struct dsi_data *dsi) 2012 { 2013 if (dsi->data->model == DSI_MODEL_OMAP4) 2014 dsi_omap4_mux_pads(dsi, 0); 2015 else if (dsi->data->model == DSI_MODEL_OMAP5) 2016 dsi_omap5_mux_pads(dsi, 0); 2017 } 2018 2019 static int dsi_cio_init(struct dsi_data *dsi) 2020 { 2021 int r; 2022 u32 l; 2023 2024 DSSDBG("DSI CIO init starts"); 2025 2026 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi)); 2027 if (r) 2028 return r; 2029 2030 dsi_enable_scp_clk(dsi); 2031 2032 /* A dummy read using the SCP interface to any DSIPHY register is 2033 * required after DSIPHY reset to complete the reset of the DSI complex 2034 * I/O. */ 2035 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 2036 2037 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) { 2038 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2039 r = -EIO; 2040 goto err_scp_clk_dom; 2041 } 2042 2043 r = dsi_set_lane_config(dsi); 2044 if (r) 2045 goto err_scp_clk_dom; 2046 2047 /* set TX STOP MODE timer to maximum for this operation */ 2048 l = dsi_read_reg(dsi, DSI_TIMING1); 2049 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2050 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2051 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2052 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2053 dsi_write_reg(dsi, DSI_TIMING1, l); 2054 2055 if (dsi->ulps_enabled) { 2056 unsigned int mask_p; 2057 int i; 2058 2059 DSSDBG("manual ulps exit\n"); 2060 2061 /* ULPS is exited by Mark-1 state for 1ms, followed by 2062 * stop state. DSS HW cannot do this via the normal 2063 * ULPS exit sequence, as after reset the DSS HW thinks 2064 * that we are not in ULPS mode, and refuses to send the 2065 * sequence. So we need to send the ULPS exit sequence 2066 * manually by setting positive lines high and negative lines 2067 * low for 1ms. 2068 */ 2069 2070 mask_p = 0; 2071 2072 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2073 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2074 continue; 2075 mask_p |= 1 << i; 2076 } 2077 2078 dsi_cio_enable_lane_override(dsi, mask_p, 0); 2079 } 2080 2081 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON); 2082 if (r) 2083 goto err_cio_pwr; 2084 2085 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) { 2086 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2087 r = -ENODEV; 2088 goto err_cio_pwr_dom; 2089 } 2090 2091 dsi_if_enable(dsi, true); 2092 dsi_if_enable(dsi, false); 2093 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2094 2095 r = dsi_cio_wait_tx_clk_esc_reset(dsi); 2096 if (r) 2097 goto err_tx_clk_esc_rst; 2098 2099 if (dsi->ulps_enabled) { 2100 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2101 ktime_t wait = ns_to_ktime(1000 * 1000); 2102 set_current_state(TASK_UNINTERRUPTIBLE); 2103 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2104 2105 /* Disable the override. The lanes should be set to Mark-11 2106 * state by the HW */ 2107 dsi_cio_disable_lane_override(dsi); 2108 } 2109 2110 /* FORCE_TX_STOP_MODE_IO */ 2111 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); 2112 2113 dsi_cio_timings(dsi); 2114 2115 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2116 /* DDR_CLK_ALWAYS_ON */ 2117 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 2118 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2119 } 2120 2121 dsi->ulps_enabled = false; 2122 2123 DSSDBG("CIO init done\n"); 2124 2125 return 0; 2126 2127 err_tx_clk_esc_rst: 2128 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2129 err_cio_pwr_dom: 2130 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 2131 err_cio_pwr: 2132 if (dsi->ulps_enabled) 2133 dsi_cio_disable_lane_override(dsi); 2134 err_scp_clk_dom: 2135 dsi_disable_scp_clk(dsi); 2136 dsi_disable_pads(dsi); 2137 return r; 2138 } 2139 2140 static void dsi_cio_uninit(struct dsi_data *dsi) 2141 { 2142 /* DDR_CLK_ALWAYS_ON */ 2143 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 2144 2145 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 2146 dsi_disable_scp_clk(dsi); 2147 dsi_disable_pads(dsi); 2148 } 2149 2150 static void dsi_config_tx_fifo(struct dsi_data *dsi, 2151 enum fifo_size size1, enum fifo_size size2, 2152 enum fifo_size size3, enum fifo_size size4) 2153 { 2154 u32 r = 0; 2155 int add = 0; 2156 int i; 2157 2158 dsi->vc[0].tx_fifo_size = size1; 2159 dsi->vc[1].tx_fifo_size = size2; 2160 dsi->vc[2].tx_fifo_size = size3; 2161 dsi->vc[3].tx_fifo_size = size4; 2162 2163 for (i = 0; i < 4; i++) { 2164 u8 v; 2165 int size = dsi->vc[i].tx_fifo_size; 2166 2167 if (add + size > 4) { 2168 DSSERR("Illegal FIFO configuration\n"); 2169 BUG(); 2170 return; 2171 } 2172 2173 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2174 r |= v << (8 * i); 2175 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2176 add += size; 2177 } 2178 2179 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r); 2180 } 2181 2182 static void dsi_config_rx_fifo(struct dsi_data *dsi, 2183 enum fifo_size size1, enum fifo_size size2, 2184 enum fifo_size size3, enum fifo_size size4) 2185 { 2186 u32 r = 0; 2187 int add = 0; 2188 int i; 2189 2190 dsi->vc[0].rx_fifo_size = size1; 2191 dsi->vc[1].rx_fifo_size = size2; 2192 dsi->vc[2].rx_fifo_size = size3; 2193 dsi->vc[3].rx_fifo_size = size4; 2194 2195 for (i = 0; i < 4; i++) { 2196 u8 v; 2197 int size = dsi->vc[i].rx_fifo_size; 2198 2199 if (add + size > 4) { 2200 DSSERR("Illegal FIFO configuration\n"); 2201 BUG(); 2202 return; 2203 } 2204 2205 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2206 r |= v << (8 * i); 2207 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2208 add += size; 2209 } 2210 2211 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r); 2212 } 2213 2214 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) 2215 { 2216 u32 r; 2217 2218 r = dsi_read_reg(dsi, DSI_TIMING1); 2219 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2220 dsi_write_reg(dsi, DSI_TIMING1, r); 2221 2222 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) { 2223 DSSERR("TX_STOP bit not going down\n"); 2224 return -EIO; 2225 } 2226 2227 return 0; 2228 } 2229 2230 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel) 2231 { 2232 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); 2233 } 2234 2235 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2236 { 2237 struct dsi_packet_sent_handler_data *vp_data = 2238 (struct dsi_packet_sent_handler_data *) data; 2239 struct dsi_data *dsi = vp_data->dsi; 2240 const int channel = dsi->update_channel; 2241 u8 bit = dsi->te_enabled ? 30 : 31; 2242 2243 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) 2244 complete(vp_data->completion); 2245 } 2246 2247 static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) 2248 { 2249 DECLARE_COMPLETION_ONSTACK(completion); 2250 struct dsi_packet_sent_handler_data vp_data = { 2251 .dsi = dsi, 2252 .completion = &completion 2253 }; 2254 int r = 0; 2255 u8 bit; 2256 2257 bit = dsi->te_enabled ? 30 : 31; 2258 2259 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2260 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2261 if (r) 2262 goto err0; 2263 2264 /* Wait for completion only if TE_EN/TE_START is still set */ 2265 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { 2266 if (wait_for_completion_timeout(&completion, 2267 msecs_to_jiffies(10)) == 0) { 2268 DSSERR("Failed to complete previous frame transfer\n"); 2269 r = -EIO; 2270 goto err1; 2271 } 2272 } 2273 2274 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2275 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2276 2277 return 0; 2278 err1: 2279 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2280 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2281 err0: 2282 return r; 2283 } 2284 2285 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2286 { 2287 struct dsi_packet_sent_handler_data *l4_data = 2288 (struct dsi_packet_sent_handler_data *) data; 2289 struct dsi_data *dsi = l4_data->dsi; 2290 const int channel = dsi->update_channel; 2291 2292 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) 2293 complete(l4_data->completion); 2294 } 2295 2296 static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) 2297 { 2298 DECLARE_COMPLETION_ONSTACK(completion); 2299 struct dsi_packet_sent_handler_data l4_data = { 2300 .dsi = dsi, 2301 .completion = &completion 2302 }; 2303 int r = 0; 2304 2305 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2306 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2307 if (r) 2308 goto err0; 2309 2310 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2311 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { 2312 if (wait_for_completion_timeout(&completion, 2313 msecs_to_jiffies(10)) == 0) { 2314 DSSERR("Failed to complete previous l4 transfer\n"); 2315 r = -EIO; 2316 goto err1; 2317 } 2318 } 2319 2320 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2321 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2322 2323 return 0; 2324 err1: 2325 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2326 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2327 err0: 2328 return r; 2329 } 2330 2331 static int dsi_sync_vc(struct dsi_data *dsi, int channel) 2332 { 2333 WARN_ON(!dsi_bus_is_locked(dsi)); 2334 2335 WARN_ON(in_interrupt()); 2336 2337 if (!dsi_vc_is_enabled(dsi, channel)) 2338 return 0; 2339 2340 switch (dsi->vc[channel].source) { 2341 case DSI_VC_SOURCE_VP: 2342 return dsi_sync_vc_vp(dsi, channel); 2343 case DSI_VC_SOURCE_L4: 2344 return dsi_sync_vc_l4(dsi, channel); 2345 default: 2346 BUG(); 2347 return -EINVAL; 2348 } 2349 } 2350 2351 static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable) 2352 { 2353 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2354 channel, enable); 2355 2356 enable = enable ? 1 : 0; 2357 2358 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0); 2359 2360 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) { 2361 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2362 return -EIO; 2363 } 2364 2365 return 0; 2366 } 2367 2368 static void dsi_vc_initial_config(struct dsi_data *dsi, int channel) 2369 { 2370 u32 r; 2371 2372 DSSDBG("Initial config of virtual channel %d", channel); 2373 2374 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel)); 2375 2376 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2377 DSSERR("VC(%d) busy when trying to configure it!\n", 2378 channel); 2379 2380 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2381 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2382 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2383 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2384 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2385 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2386 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2387 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) 2388 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2389 2390 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2391 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2392 2393 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r); 2394 2395 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2396 } 2397 2398 static int dsi_vc_config_source(struct dsi_data *dsi, int channel, 2399 enum dsi_vc_source source) 2400 { 2401 if (dsi->vc[channel].source == source) 2402 return 0; 2403 2404 DSSDBG("Source config of virtual channel %d", channel); 2405 2406 dsi_sync_vc(dsi, channel); 2407 2408 dsi_vc_enable(dsi, channel, 0); 2409 2410 /* VC_BUSY */ 2411 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) { 2412 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2413 return -EIO; 2414 } 2415 2416 /* SOURCE, 0 = L4, 1 = video port */ 2417 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1); 2418 2419 /* DCS_CMD_ENABLE */ 2420 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { 2421 bool enable = source == DSI_VC_SOURCE_VP; 2422 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30); 2423 } 2424 2425 dsi_vc_enable(dsi, channel, 1); 2426 2427 dsi->vc[channel].source = source; 2428 2429 return 0; 2430 } 2431 2432 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2433 bool enable) 2434 { 2435 struct dsi_data *dsi = to_dsi_data(dssdev); 2436 2437 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2438 2439 WARN_ON(!dsi_bus_is_locked(dsi)); 2440 2441 dsi_vc_enable(dsi, channel, 0); 2442 dsi_if_enable(dsi, 0); 2443 2444 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9); 2445 2446 dsi_vc_enable(dsi, channel, 1); 2447 dsi_if_enable(dsi, 1); 2448 2449 dsi_force_tx_stop_mode_io(dsi); 2450 2451 /* start the DDR clock by sending a NULL packet */ 2452 if (dsi->vm_timings.ddr_clk_always_on && enable) 2453 dsi_vc_send_null(dsi, channel); 2454 } 2455 2456 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel) 2457 { 2458 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2459 u32 val; 2460 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2461 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2462 (val >> 0) & 0xff, 2463 (val >> 8) & 0xff, 2464 (val >> 16) & 0xff, 2465 (val >> 24) & 0xff); 2466 } 2467 } 2468 2469 static void dsi_show_rx_ack_with_err(u16 err) 2470 { 2471 DSSERR("\tACK with ERROR (%#x):\n", err); 2472 if (err & (1 << 0)) 2473 DSSERR("\t\tSoT Error\n"); 2474 if (err & (1 << 1)) 2475 DSSERR("\t\tSoT Sync Error\n"); 2476 if (err & (1 << 2)) 2477 DSSERR("\t\tEoT Sync Error\n"); 2478 if (err & (1 << 3)) 2479 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2480 if (err & (1 << 4)) 2481 DSSERR("\t\tLP Transmit Sync Error\n"); 2482 if (err & (1 << 5)) 2483 DSSERR("\t\tHS Receive Timeout Error\n"); 2484 if (err & (1 << 6)) 2485 DSSERR("\t\tFalse Control Error\n"); 2486 if (err & (1 << 7)) 2487 DSSERR("\t\t(reserved7)\n"); 2488 if (err & (1 << 8)) 2489 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2490 if (err & (1 << 9)) 2491 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2492 if (err & (1 << 10)) 2493 DSSERR("\t\tChecksum Error\n"); 2494 if (err & (1 << 11)) 2495 DSSERR("\t\tData type not recognized\n"); 2496 if (err & (1 << 12)) 2497 DSSERR("\t\tInvalid VC ID\n"); 2498 if (err & (1 << 13)) 2499 DSSERR("\t\tInvalid Transmission Length\n"); 2500 if (err & (1 << 14)) 2501 DSSERR("\t\t(reserved14)\n"); 2502 if (err & (1 << 15)) 2503 DSSERR("\t\tDSI Protocol Violation\n"); 2504 } 2505 2506 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) 2507 { 2508 /* RX_FIFO_NOT_EMPTY */ 2509 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2510 u32 val; 2511 u8 dt; 2512 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2513 DSSERR("\trawval %#08x\n", val); 2514 dt = FLD_GET(val, 5, 0); 2515 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2516 u16 err = FLD_GET(val, 23, 8); 2517 dsi_show_rx_ack_with_err(err); 2518 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2519 DSSERR("\tDCS short response, 1 byte: %#x\n", 2520 FLD_GET(val, 23, 8)); 2521 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2522 DSSERR("\tDCS short response, 2 byte: %#x\n", 2523 FLD_GET(val, 23, 8)); 2524 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2525 DSSERR("\tDCS long response, len %d\n", 2526 FLD_GET(val, 23, 8)); 2527 dsi_vc_flush_long_data(dsi, channel); 2528 } else { 2529 DSSERR("\tunknown datatype 0x%02x\n", dt); 2530 } 2531 } 2532 return 0; 2533 } 2534 2535 static int dsi_vc_send_bta(struct dsi_data *dsi, int channel) 2536 { 2537 if (dsi->debug_write || dsi->debug_read) 2538 DSSDBG("dsi_vc_send_bta %d\n", channel); 2539 2540 WARN_ON(!dsi_bus_is_locked(dsi)); 2541 2542 /* RX_FIFO_NOT_EMPTY */ 2543 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2544 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2545 dsi_vc_flush_receive_data(dsi, channel); 2546 } 2547 2548 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2549 2550 /* flush posted write */ 2551 dsi_read_reg(dsi, DSI_VC_CTRL(channel)); 2552 2553 return 0; 2554 } 2555 2556 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2557 { 2558 struct dsi_data *dsi = to_dsi_data(dssdev); 2559 DECLARE_COMPLETION_ONSTACK(completion); 2560 int r = 0; 2561 u32 err; 2562 2563 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler, 2564 &completion, DSI_VC_IRQ_BTA); 2565 if (r) 2566 goto err0; 2567 2568 r = dsi_register_isr(dsi, dsi_completion_handler, &completion, 2569 DSI_IRQ_ERROR_MASK); 2570 if (r) 2571 goto err1; 2572 2573 r = dsi_vc_send_bta(dsi, channel); 2574 if (r) 2575 goto err2; 2576 2577 if (wait_for_completion_timeout(&completion, 2578 msecs_to_jiffies(500)) == 0) { 2579 DSSERR("Failed to receive BTA\n"); 2580 r = -EIO; 2581 goto err2; 2582 } 2583 2584 err = dsi_get_errors(dsi); 2585 if (err) { 2586 DSSERR("Error while sending BTA: %x\n", err); 2587 r = -EIO; 2588 goto err2; 2589 } 2590 err2: 2591 dsi_unregister_isr(dsi, dsi_completion_handler, &completion, 2592 DSI_IRQ_ERROR_MASK); 2593 err1: 2594 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler, 2595 &completion, DSI_VC_IRQ_BTA); 2596 err0: 2597 return r; 2598 } 2599 2600 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel, 2601 u8 data_type, u16 len, u8 ecc) 2602 { 2603 u32 val; 2604 u8 data_id; 2605 2606 WARN_ON(!dsi_bus_is_locked(dsi)); 2607 2608 data_id = data_type | dsi->vc[channel].vc_id << 6; 2609 2610 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2611 FLD_VAL(ecc, 31, 24); 2612 2613 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val); 2614 } 2615 2616 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel, 2617 u8 b1, u8 b2, u8 b3, u8 b4) 2618 { 2619 u32 val; 2620 2621 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2622 2623 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2624 b1, b2, b3, b4, val); */ 2625 2626 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2627 } 2628 2629 static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type, 2630 u8 *data, u16 len, u8 ecc) 2631 { 2632 /*u32 val; */ 2633 int i; 2634 u8 *p; 2635 int r = 0; 2636 u8 b1, b2, b3, b4; 2637 2638 if (dsi->debug_write) 2639 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2640 2641 /* len + header */ 2642 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2643 DSSERR("unable to send long packet: packet too long.\n"); 2644 return -EINVAL; 2645 } 2646 2647 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); 2648 2649 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc); 2650 2651 p = data; 2652 for (i = 0; i < len >> 2; i++) { 2653 if (dsi->debug_write) 2654 DSSDBG("\tsending full packet %d\n", i); 2655 2656 b1 = *p++; 2657 b2 = *p++; 2658 b3 = *p++; 2659 b4 = *p++; 2660 2661 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4); 2662 } 2663 2664 i = len % 4; 2665 if (i) { 2666 b1 = 0; b2 = 0; b3 = 0; 2667 2668 if (dsi->debug_write) 2669 DSSDBG("\tsending remainder bytes %d\n", i); 2670 2671 switch (i) { 2672 case 3: 2673 b1 = *p++; 2674 b2 = *p++; 2675 b3 = *p++; 2676 break; 2677 case 2: 2678 b1 = *p++; 2679 b2 = *p++; 2680 break; 2681 case 1: 2682 b1 = *p++; 2683 break; 2684 } 2685 2686 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0); 2687 } 2688 2689 return r; 2690 } 2691 2692 static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type, 2693 u16 data, u8 ecc) 2694 { 2695 u32 r; 2696 u8 data_id; 2697 2698 WARN_ON(!dsi_bus_is_locked(dsi)); 2699 2700 if (dsi->debug_write) 2701 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2702 channel, 2703 data_type, data & 0xff, (data >> 8) & 0xff); 2704 2705 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); 2706 2707 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) { 2708 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2709 return -EINVAL; 2710 } 2711 2712 data_id = data_type | dsi->vc[channel].vc_id << 6; 2713 2714 r = (data_id << 0) | (data << 8) | (ecc << 24); 2715 2716 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2717 2718 return 0; 2719 } 2720 2721 static int dsi_vc_send_null(struct dsi_data *dsi, int channel) 2722 { 2723 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0); 2724 } 2725 2726 static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel, 2727 u8 *data, int len, 2728 enum dss_dsi_content_type type) 2729 { 2730 int r; 2731 2732 if (len == 0) { 2733 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2734 r = dsi_vc_send_short(dsi, channel, 2735 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2736 } else if (len == 1) { 2737 r = dsi_vc_send_short(dsi, channel, 2738 type == DSS_DSI_CONTENT_GENERIC ? 2739 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2740 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2741 } else if (len == 2) { 2742 r = dsi_vc_send_short(dsi, channel, 2743 type == DSS_DSI_CONTENT_GENERIC ? 2744 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2745 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2746 data[0] | (data[1] << 8), 0); 2747 } else { 2748 r = dsi_vc_send_long(dsi, channel, 2749 type == DSS_DSI_CONTENT_GENERIC ? 2750 MIPI_DSI_GENERIC_LONG_WRITE : 2751 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2752 } 2753 2754 return r; 2755 } 2756 2757 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2758 u8 *data, int len) 2759 { 2760 struct dsi_data *dsi = to_dsi_data(dssdev); 2761 2762 return dsi_vc_write_nosync_common(dsi, channel, data, len, 2763 DSS_DSI_CONTENT_DCS); 2764 } 2765 2766 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2767 u8 *data, int len) 2768 { 2769 struct dsi_data *dsi = to_dsi_data(dssdev); 2770 2771 return dsi_vc_write_nosync_common(dsi, channel, data, len, 2772 DSS_DSI_CONTENT_GENERIC); 2773 } 2774 2775 static int dsi_vc_write_common(struct omap_dss_device *dssdev, 2776 int channel, u8 *data, int len, 2777 enum dss_dsi_content_type type) 2778 { 2779 struct dsi_data *dsi = to_dsi_data(dssdev); 2780 int r; 2781 2782 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type); 2783 if (r) 2784 goto err; 2785 2786 r = dsi_vc_send_bta_sync(dssdev, channel); 2787 if (r) 2788 goto err; 2789 2790 /* RX_FIFO_NOT_EMPTY */ 2791 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2792 DSSERR("rx fifo not empty after write, dumping data:\n"); 2793 dsi_vc_flush_receive_data(dsi, channel); 2794 r = -EIO; 2795 goto err; 2796 } 2797 2798 return 0; 2799 err: 2800 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2801 channel, data[0], len); 2802 return r; 2803 } 2804 2805 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2806 int len) 2807 { 2808 return dsi_vc_write_common(dssdev, channel, data, len, 2809 DSS_DSI_CONTENT_DCS); 2810 } 2811 2812 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2813 int len) 2814 { 2815 return dsi_vc_write_common(dssdev, channel, data, len, 2816 DSS_DSI_CONTENT_GENERIC); 2817 } 2818 2819 static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel, 2820 u8 dcs_cmd) 2821 { 2822 int r; 2823 2824 if (dsi->debug_read) 2825 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2826 channel, dcs_cmd); 2827 2828 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2829 if (r) { 2830 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2831 " failed\n", channel, dcs_cmd); 2832 return r; 2833 } 2834 2835 return 0; 2836 } 2837 2838 static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel, 2839 u8 *reqdata, int reqlen) 2840 { 2841 u16 data; 2842 u8 data_type; 2843 int r; 2844 2845 if (dsi->debug_read) 2846 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2847 channel, reqlen); 2848 2849 if (reqlen == 0) { 2850 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2851 data = 0; 2852 } else if (reqlen == 1) { 2853 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2854 data = reqdata[0]; 2855 } else if (reqlen == 2) { 2856 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2857 data = reqdata[0] | (reqdata[1] << 8); 2858 } else { 2859 BUG(); 2860 return -EINVAL; 2861 } 2862 2863 r = dsi_vc_send_short(dsi, channel, data_type, data, 0); 2864 if (r) { 2865 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2866 " failed\n", channel, reqlen); 2867 return r; 2868 } 2869 2870 return 0; 2871 } 2872 2873 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, 2874 int buflen, enum dss_dsi_content_type type) 2875 { 2876 u32 val; 2877 u8 dt; 2878 int r; 2879 2880 /* RX_FIFO_NOT_EMPTY */ 2881 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) { 2882 DSSERR("RX fifo empty when trying to read.\n"); 2883 r = -EIO; 2884 goto err; 2885 } 2886 2887 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2888 if (dsi->debug_read) 2889 DSSDBG("\theader: %08x\n", val); 2890 dt = FLD_GET(val, 5, 0); 2891 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2892 u16 err = FLD_GET(val, 23, 8); 2893 dsi_show_rx_ack_with_err(err); 2894 r = -EIO; 2895 goto err; 2896 2897 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2898 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2899 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2900 u8 data = FLD_GET(val, 15, 8); 2901 if (dsi->debug_read) 2902 DSSDBG("\t%s short response, 1 byte: %02x\n", 2903 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2904 "DCS", data); 2905 2906 if (buflen < 1) { 2907 r = -EIO; 2908 goto err; 2909 } 2910 2911 buf[0] = data; 2912 2913 return 1; 2914 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2915 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2916 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2917 u16 data = FLD_GET(val, 23, 8); 2918 if (dsi->debug_read) 2919 DSSDBG("\t%s short response, 2 byte: %04x\n", 2920 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2921 "DCS", data); 2922 2923 if (buflen < 2) { 2924 r = -EIO; 2925 goto err; 2926 } 2927 2928 buf[0] = data & 0xff; 2929 buf[1] = (data >> 8) & 0xff; 2930 2931 return 2; 2932 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2933 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2934 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2935 int w; 2936 int len = FLD_GET(val, 23, 8); 2937 if (dsi->debug_read) 2938 DSSDBG("\t%s long response, len %d\n", 2939 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2940 "DCS", len); 2941 2942 if (len > buflen) { 2943 r = -EIO; 2944 goto err; 2945 } 2946 2947 /* two byte checksum ends the packet, not included in len */ 2948 for (w = 0; w < len + 2;) { 2949 int b; 2950 val = dsi_read_reg(dsi, 2951 DSI_VC_SHORT_PACKET_HEADER(channel)); 2952 if (dsi->debug_read) 2953 DSSDBG("\t\t%02x %02x %02x %02x\n", 2954 (val >> 0) & 0xff, 2955 (val >> 8) & 0xff, 2956 (val >> 16) & 0xff, 2957 (val >> 24) & 0xff); 2958 2959 for (b = 0; b < 4; ++b) { 2960 if (w < len) 2961 buf[w] = (val >> (b * 8)) & 0xff; 2962 /* we discard the 2 byte checksum */ 2963 ++w; 2964 } 2965 } 2966 2967 return len; 2968 } else { 2969 DSSERR("\tunknown datatype 0x%02x\n", dt); 2970 r = -EIO; 2971 goto err; 2972 } 2973 2974 err: 2975 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 2976 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 2977 2978 return r; 2979 } 2980 2981 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 2982 u8 *buf, int buflen) 2983 { 2984 struct dsi_data *dsi = to_dsi_data(dssdev); 2985 int r; 2986 2987 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd); 2988 if (r) 2989 goto err; 2990 2991 r = dsi_vc_send_bta_sync(dssdev, channel); 2992 if (r) 2993 goto err; 2994 2995 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, 2996 DSS_DSI_CONTENT_DCS); 2997 if (r < 0) 2998 goto err; 2999 3000 if (r != buflen) { 3001 r = -EIO; 3002 goto err; 3003 } 3004 3005 return 0; 3006 err: 3007 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3008 return r; 3009 } 3010 3011 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3012 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3013 { 3014 struct dsi_data *dsi = to_dsi_data(dssdev); 3015 int r; 3016 3017 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen); 3018 if (r) 3019 return r; 3020 3021 r = dsi_vc_send_bta_sync(dssdev, channel); 3022 if (r) 3023 return r; 3024 3025 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, 3026 DSS_DSI_CONTENT_GENERIC); 3027 if (r < 0) 3028 return r; 3029 3030 if (r != buflen) { 3031 r = -EIO; 3032 return r; 3033 } 3034 3035 return 0; 3036 } 3037 3038 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3039 u16 len) 3040 { 3041 struct dsi_data *dsi = to_dsi_data(dssdev); 3042 3043 return dsi_vc_send_short(dsi, channel, 3044 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3045 } 3046 3047 static int dsi_enter_ulps(struct dsi_data *dsi) 3048 { 3049 DECLARE_COMPLETION_ONSTACK(completion); 3050 int r, i; 3051 unsigned int mask; 3052 3053 DSSDBG("Entering ULPS"); 3054 3055 WARN_ON(!dsi_bus_is_locked(dsi)); 3056 3057 WARN_ON(dsi->ulps_enabled); 3058 3059 if (dsi->ulps_enabled) 3060 return 0; 3061 3062 /* DDR_CLK_ALWAYS_ON */ 3063 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) { 3064 dsi_if_enable(dsi, 0); 3065 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 3066 dsi_if_enable(dsi, 1); 3067 } 3068 3069 dsi_sync_vc(dsi, 0); 3070 dsi_sync_vc(dsi, 1); 3071 dsi_sync_vc(dsi, 2); 3072 dsi_sync_vc(dsi, 3); 3073 3074 dsi_force_tx_stop_mode_io(dsi); 3075 3076 dsi_vc_enable(dsi, 0, false); 3077 dsi_vc_enable(dsi, 1, false); 3078 dsi_vc_enable(dsi, 2, false); 3079 dsi_vc_enable(dsi, 3, false); 3080 3081 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3082 DSSERR("HS busy when enabling ULPS\n"); 3083 return -EIO; 3084 } 3085 3086 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3087 DSSERR("LP busy when enabling ULPS\n"); 3088 return -EIO; 3089 } 3090 3091 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion, 3092 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3093 if (r) 3094 return r; 3095 3096 mask = 0; 3097 3098 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3099 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3100 continue; 3101 mask |= 1 << i; 3102 } 3103 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3104 /* LANEx_ULPS_SIG2 */ 3105 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3106 3107 /* flush posted write and wait for SCP interface to finish the write */ 3108 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); 3109 3110 if (wait_for_completion_timeout(&completion, 3111 msecs_to_jiffies(1000)) == 0) { 3112 DSSERR("ULPS enable timeout\n"); 3113 r = -EIO; 3114 goto err; 3115 } 3116 3117 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, 3118 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3119 3120 /* Reset LANEx_ULPS_SIG2 */ 3121 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3122 3123 /* flush posted write and wait for SCP interface to finish the write */ 3124 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); 3125 3126 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS); 3127 3128 dsi_if_enable(dsi, false); 3129 3130 dsi->ulps_enabled = true; 3131 3132 return 0; 3133 3134 err: 3135 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, 3136 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3137 return r; 3138 } 3139 3140 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks, 3141 bool x4, bool x16) 3142 { 3143 unsigned long fck; 3144 unsigned long total_ticks; 3145 u32 r; 3146 3147 BUG_ON(ticks > 0x1fff); 3148 3149 /* ticks in DSI_FCK */ 3150 fck = dsi_fclk_rate(dsi); 3151 3152 r = dsi_read_reg(dsi, DSI_TIMING2); 3153 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3154 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3155 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3156 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3157 dsi_write_reg(dsi, DSI_TIMING2, r); 3158 3159 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3160 3161 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3162 total_ticks, 3163 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3164 (total_ticks * 1000) / (fck / 1000 / 1000)); 3165 } 3166 3167 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks, 3168 bool x8, bool x16) 3169 { 3170 unsigned long fck; 3171 unsigned long total_ticks; 3172 u32 r; 3173 3174 BUG_ON(ticks > 0x1fff); 3175 3176 /* ticks in DSI_FCK */ 3177 fck = dsi_fclk_rate(dsi); 3178 3179 r = dsi_read_reg(dsi, DSI_TIMING1); 3180 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3181 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3182 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3183 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3184 dsi_write_reg(dsi, DSI_TIMING1, r); 3185 3186 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3187 3188 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3189 total_ticks, 3190 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3191 (total_ticks * 1000) / (fck / 1000 / 1000)); 3192 } 3193 3194 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks, 3195 bool x4, bool x16) 3196 { 3197 unsigned long fck; 3198 unsigned long total_ticks; 3199 u32 r; 3200 3201 BUG_ON(ticks > 0x1fff); 3202 3203 /* ticks in DSI_FCK */ 3204 fck = dsi_fclk_rate(dsi); 3205 3206 r = dsi_read_reg(dsi, DSI_TIMING1); 3207 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3208 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3209 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3210 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3211 dsi_write_reg(dsi, DSI_TIMING1, r); 3212 3213 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3214 3215 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3216 total_ticks, 3217 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3218 (total_ticks * 1000) / (fck / 1000 / 1000)); 3219 } 3220 3221 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks, 3222 bool x4, bool x16) 3223 { 3224 unsigned long fck; 3225 unsigned long total_ticks; 3226 u32 r; 3227 3228 BUG_ON(ticks > 0x1fff); 3229 3230 /* ticks in TxByteClkHS */ 3231 fck = dsi_get_txbyteclkhs(dsi); 3232 3233 r = dsi_read_reg(dsi, DSI_TIMING2); 3234 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3235 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3236 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3237 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3238 dsi_write_reg(dsi, DSI_TIMING2, r); 3239 3240 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3241 3242 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3243 total_ticks, 3244 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3245 (total_ticks * 1000) / (fck / 1000 / 1000)); 3246 } 3247 3248 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi) 3249 { 3250 int num_line_buffers; 3251 3252 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3253 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3254 const struct videomode *vm = &dsi->vm; 3255 /* 3256 * Don't use line buffers if width is greater than the video 3257 * port's line buffer size 3258 */ 3259 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 3260 num_line_buffers = 0; 3261 else 3262 num_line_buffers = 2; 3263 } else { 3264 /* Use maximum number of line buffers in command mode */ 3265 num_line_buffers = 2; 3266 } 3267 3268 /* LINE_BUFFER */ 3269 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); 3270 } 3271 3272 static void dsi_config_vp_sync_events(struct dsi_data *dsi) 3273 { 3274 bool sync_end; 3275 u32 r; 3276 3277 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3278 sync_end = true; 3279 else 3280 sync_end = false; 3281 3282 r = dsi_read_reg(dsi, DSI_CTRL); 3283 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3284 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3285 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3286 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3287 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3288 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3289 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3290 dsi_write_reg(dsi, DSI_CTRL, r); 3291 } 3292 3293 static void dsi_config_blanking_modes(struct dsi_data *dsi) 3294 { 3295 int blanking_mode = dsi->vm_timings.blanking_mode; 3296 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3297 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3298 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3299 u32 r; 3300 3301 /* 3302 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3303 * 1 = Long blanking packets are sent in corresponding blanking periods 3304 */ 3305 r = dsi_read_reg(dsi, DSI_CTRL); 3306 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3307 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3308 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3309 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3310 dsi_write_reg(dsi, DSI_CTRL, r); 3311 } 3312 3313 /* 3314 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3315 * results in maximum transition time for data and clock lanes to enter and 3316 * exit HS mode. Hence, this is the scenario where the least amount of command 3317 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3318 * clock cycles that can be used to interleave command mode data in HS so that 3319 * all scenarios are satisfied. 3320 */ 3321 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3322 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3323 { 3324 int transition; 3325 3326 /* 3327 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3328 * time of data lanes only, if it isn't set, we need to consider HS 3329 * transition time of both data and clock lanes. HS transition time 3330 * of Scenario 3 is considered. 3331 */ 3332 if (ddr_alwon) { 3333 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3334 } else { 3335 int trans1, trans2; 3336 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3337 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3338 enter_hs + 1; 3339 transition = max(trans1, trans2); 3340 } 3341 3342 return blank > transition ? blank - transition : 0; 3343 } 3344 3345 /* 3346 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3347 * results in maximum transition time for data lanes to enter and exit LP mode. 3348 * Hence, this is the scenario where the least amount of command mode data can 3349 * be interleaved. We program the minimum amount of bytes that can be 3350 * interleaved in LP so that all scenarios are satisfied. 3351 */ 3352 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3353 int lp_clk_div, int tdsi_fclk) 3354 { 3355 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3356 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3357 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3358 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3359 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3360 3361 /* maximum LP transition time according to Scenario 1 */ 3362 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3363 3364 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3365 tlp_avail = thsbyte_clk * (blank - trans_lp); 3366 3367 ttxclkesc = tdsi_fclk * lp_clk_div; 3368 3369 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3370 26) / 16; 3371 3372 return max(lp_inter, 0); 3373 } 3374 3375 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi) 3376 { 3377 int blanking_mode; 3378 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3379 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3380 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3381 int tclk_trail, ths_exit, exiths_clk; 3382 bool ddr_alwon; 3383 const struct videomode *vm = &dsi->vm; 3384 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3385 int ndl = dsi->num_lanes_used - 1; 3386 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3387 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3388 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3389 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3390 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3391 u32 r; 3392 3393 r = dsi_read_reg(dsi, DSI_CTRL); 3394 blanking_mode = FLD_GET(r, 20, 20); 3395 hfp_blanking_mode = FLD_GET(r, 21, 21); 3396 hbp_blanking_mode = FLD_GET(r, 22, 22); 3397 hsa_blanking_mode = FLD_GET(r, 23, 23); 3398 3399 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 3400 hbp = FLD_GET(r, 11, 0); 3401 hfp = FLD_GET(r, 23, 12); 3402 hsa = FLD_GET(r, 31, 24); 3403 3404 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 3405 ddr_clk_post = FLD_GET(r, 7, 0); 3406 ddr_clk_pre = FLD_GET(r, 15, 8); 3407 3408 r = dsi_read_reg(dsi, DSI_VM_TIMING7); 3409 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3410 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3411 3412 r = dsi_read_reg(dsi, DSI_CLK_CTRL); 3413 lp_clk_div = FLD_GET(r, 12, 0); 3414 ddr_alwon = FLD_GET(r, 13, 13); 3415 3416 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 3417 ths_exit = FLD_GET(r, 7, 0); 3418 3419 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 3420 tclk_trail = FLD_GET(r, 15, 8); 3421 3422 exiths_clk = ths_exit + tclk_trail; 3423 3424 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3425 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3426 3427 if (!hsa_blanking_mode) { 3428 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3429 enter_hs_mode_lat, exit_hs_mode_lat, 3430 exiths_clk, ddr_clk_pre, ddr_clk_post); 3431 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3432 enter_hs_mode_lat, exit_hs_mode_lat, 3433 lp_clk_div, dsi_fclk_hsdiv); 3434 } 3435 3436 if (!hfp_blanking_mode) { 3437 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3438 enter_hs_mode_lat, exit_hs_mode_lat, 3439 exiths_clk, ddr_clk_pre, ddr_clk_post); 3440 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3441 enter_hs_mode_lat, exit_hs_mode_lat, 3442 lp_clk_div, dsi_fclk_hsdiv); 3443 } 3444 3445 if (!hbp_blanking_mode) { 3446 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3447 enter_hs_mode_lat, exit_hs_mode_lat, 3448 exiths_clk, ddr_clk_pre, ddr_clk_post); 3449 3450 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3451 enter_hs_mode_lat, exit_hs_mode_lat, 3452 lp_clk_div, dsi_fclk_hsdiv); 3453 } 3454 3455 if (!blanking_mode) { 3456 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3457 enter_hs_mode_lat, exit_hs_mode_lat, 3458 exiths_clk, ddr_clk_pre, ddr_clk_post); 3459 3460 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3461 enter_hs_mode_lat, exit_hs_mode_lat, 3462 lp_clk_div, dsi_fclk_hsdiv); 3463 } 3464 3465 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3466 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3467 bl_interleave_hs); 3468 3469 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3470 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3471 bl_interleave_lp); 3472 3473 r = dsi_read_reg(dsi, DSI_VM_TIMING4); 3474 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3475 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3476 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3477 dsi_write_reg(dsi, DSI_VM_TIMING4, r); 3478 3479 r = dsi_read_reg(dsi, DSI_VM_TIMING5); 3480 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3481 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3482 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3483 dsi_write_reg(dsi, DSI_VM_TIMING5, r); 3484 3485 r = dsi_read_reg(dsi, DSI_VM_TIMING6); 3486 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3487 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3488 dsi_write_reg(dsi, DSI_VM_TIMING6, r); 3489 } 3490 3491 static int dsi_proto_config(struct dsi_data *dsi) 3492 { 3493 u32 r; 3494 int buswidth = 0; 3495 3496 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32, 3497 DSI_FIFO_SIZE_32, 3498 DSI_FIFO_SIZE_32, 3499 DSI_FIFO_SIZE_32); 3500 3501 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32, 3502 DSI_FIFO_SIZE_32, 3503 DSI_FIFO_SIZE_32, 3504 DSI_FIFO_SIZE_32); 3505 3506 /* XXX what values for the timeouts? */ 3507 dsi_set_stop_state_counter(dsi, 0x1000, false, false); 3508 dsi_set_ta_timeout(dsi, 0x1fff, true, true); 3509 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true); 3510 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true); 3511 3512 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3513 case 16: 3514 buswidth = 0; 3515 break; 3516 case 18: 3517 buswidth = 1; 3518 break; 3519 case 24: 3520 buswidth = 2; 3521 break; 3522 default: 3523 BUG(); 3524 return -EINVAL; 3525 } 3526 3527 r = dsi_read_reg(dsi, DSI_CTRL); 3528 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3529 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3530 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3531 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3532 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3533 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3534 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3535 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3536 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { 3537 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3538 /* DCS_CMD_CODE, 1=start, 0=continue */ 3539 r = FLD_MOD(r, 0, 25, 25); 3540 } 3541 3542 dsi_write_reg(dsi, DSI_CTRL, r); 3543 3544 dsi_config_vp_num_line_buffers(dsi); 3545 3546 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3547 dsi_config_vp_sync_events(dsi); 3548 dsi_config_blanking_modes(dsi); 3549 dsi_config_cmd_mode_interleaving(dsi); 3550 } 3551 3552 dsi_vc_initial_config(dsi, 0); 3553 dsi_vc_initial_config(dsi, 1); 3554 dsi_vc_initial_config(dsi, 2); 3555 dsi_vc_initial_config(dsi, 3); 3556 3557 return 0; 3558 } 3559 3560 static void dsi_proto_timings(struct dsi_data *dsi) 3561 { 3562 unsigned int tlpx, tclk_zero, tclk_prepare, tclk_trail; 3563 unsigned int tclk_pre, tclk_post; 3564 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero; 3565 unsigned int ths_trail, ths_exit; 3566 unsigned int ddr_clk_pre, ddr_clk_post; 3567 unsigned int enter_hs_mode_lat, exit_hs_mode_lat; 3568 unsigned int ths_eot; 3569 int ndl = dsi->num_lanes_used - 1; 3570 u32 r; 3571 3572 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 3573 ths_prepare = FLD_GET(r, 31, 24); 3574 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3575 ths_zero = ths_prepare_ths_zero - ths_prepare; 3576 ths_trail = FLD_GET(r, 15, 8); 3577 ths_exit = FLD_GET(r, 7, 0); 3578 3579 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 3580 tlpx = FLD_GET(r, 20, 16) * 2; 3581 tclk_trail = FLD_GET(r, 15, 8); 3582 tclk_zero = FLD_GET(r, 7, 0); 3583 3584 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 3585 tclk_prepare = FLD_GET(r, 7, 0); 3586 3587 /* min 8*UI */ 3588 tclk_pre = 20; 3589 /* min 60ns + 52*UI */ 3590 tclk_post = ns2ddr(dsi, 60) + 26; 3591 3592 ths_eot = DIV_ROUND_UP(4, ndl); 3593 3594 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3595 4); 3596 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3597 3598 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3599 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3600 3601 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 3602 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3603 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3604 dsi_write_reg(dsi, DSI_CLK_TIMING, r); 3605 3606 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3607 ddr_clk_pre, 3608 ddr_clk_post); 3609 3610 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3611 DIV_ROUND_UP(ths_prepare, 4) + 3612 DIV_ROUND_UP(ths_zero + 3, 4); 3613 3614 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3615 3616 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3617 FLD_VAL(exit_hs_mode_lat, 15, 0); 3618 dsi_write_reg(dsi, DSI_VM_TIMING7, r); 3619 3620 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3621 enter_hs_mode_lat, exit_hs_mode_lat); 3622 3623 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3624 /* TODO: Implement a video mode check_timings function */ 3625 int hsa = dsi->vm_timings.hsa; 3626 int hfp = dsi->vm_timings.hfp; 3627 int hbp = dsi->vm_timings.hbp; 3628 int vsa = dsi->vm_timings.vsa; 3629 int vfp = dsi->vm_timings.vfp; 3630 int vbp = dsi->vm_timings.vbp; 3631 int window_sync = dsi->vm_timings.window_sync; 3632 bool hsync_end; 3633 const struct videomode *vm = &dsi->vm; 3634 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3635 int tl, t_he, width_bytes; 3636 3637 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3638 t_he = hsync_end ? 3639 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3640 3641 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3642 3643 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3644 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3645 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3646 3647 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3648 hfp, hsync_end ? hsa : 0, tl); 3649 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3650 vsa, vm->vactive); 3651 3652 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 3653 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3654 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3655 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3656 dsi_write_reg(dsi, DSI_VM_TIMING1, r); 3657 3658 r = dsi_read_reg(dsi, DSI_VM_TIMING2); 3659 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3660 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3661 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3662 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3663 dsi_write_reg(dsi, DSI_VM_TIMING2, r); 3664 3665 r = dsi_read_reg(dsi, DSI_VM_TIMING3); 3666 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 3667 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3668 dsi_write_reg(dsi, DSI_VM_TIMING3, r); 3669 } 3670 } 3671 3672 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3673 const struct omap_dsi_pin_config *pin_cfg) 3674 { 3675 struct dsi_data *dsi = to_dsi_data(dssdev); 3676 int num_pins; 3677 const int *pins; 3678 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3679 int num_lanes; 3680 int i; 3681 3682 static const enum dsi_lane_function functions[] = { 3683 DSI_LANE_CLK, 3684 DSI_LANE_DATA1, 3685 DSI_LANE_DATA2, 3686 DSI_LANE_DATA3, 3687 DSI_LANE_DATA4, 3688 }; 3689 3690 num_pins = pin_cfg->num_pins; 3691 pins = pin_cfg->pins; 3692 3693 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3694 || num_pins % 2 != 0) 3695 return -EINVAL; 3696 3697 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3698 lanes[i].function = DSI_LANE_UNUSED; 3699 3700 num_lanes = 0; 3701 3702 for (i = 0; i < num_pins; i += 2) { 3703 u8 lane, pol; 3704 int dx, dy; 3705 3706 dx = pins[i]; 3707 dy = pins[i + 1]; 3708 3709 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3710 return -EINVAL; 3711 3712 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3713 return -EINVAL; 3714 3715 if (dx & 1) { 3716 if (dy != dx - 1) 3717 return -EINVAL; 3718 pol = 1; 3719 } else { 3720 if (dy != dx + 1) 3721 return -EINVAL; 3722 pol = 0; 3723 } 3724 3725 lane = dx / 2; 3726 3727 lanes[lane].function = functions[i / 2]; 3728 lanes[lane].polarity = pol; 3729 num_lanes++; 3730 } 3731 3732 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3733 dsi->num_lanes_used = num_lanes; 3734 3735 return 0; 3736 } 3737 3738 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3739 { 3740 struct dsi_data *dsi = to_dsi_data(dssdev); 3741 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3742 u8 data_type; 3743 u16 word_count; 3744 int r; 3745 3746 r = dsi_display_init_dispc(dsi); 3747 if (r) 3748 return r; 3749 3750 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3751 switch (dsi->pix_fmt) { 3752 case OMAP_DSS_DSI_FMT_RGB888: 3753 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3754 break; 3755 case OMAP_DSS_DSI_FMT_RGB666: 3756 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3757 break; 3758 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3759 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3760 break; 3761 case OMAP_DSS_DSI_FMT_RGB565: 3762 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3763 break; 3764 default: 3765 r = -EINVAL; 3766 goto err_pix_fmt; 3767 } 3768 3769 dsi_if_enable(dsi, false); 3770 dsi_vc_enable(dsi, channel, false); 3771 3772 /* MODE, 1 = video mode */ 3773 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4); 3774 3775 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3776 3777 dsi_vc_write_long_header(dsi, channel, data_type, 3778 word_count, 0); 3779 3780 dsi_vc_enable(dsi, channel, true); 3781 dsi_if_enable(dsi, true); 3782 } 3783 3784 r = dss_mgr_enable(&dsi->output); 3785 if (r) 3786 goto err_mgr_enable; 3787 3788 return 0; 3789 3790 err_mgr_enable: 3791 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3792 dsi_if_enable(dsi, false); 3793 dsi_vc_enable(dsi, channel, false); 3794 } 3795 err_pix_fmt: 3796 dsi_display_uninit_dispc(dsi); 3797 return r; 3798 } 3799 3800 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3801 { 3802 struct dsi_data *dsi = to_dsi_data(dssdev); 3803 3804 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3805 dsi_if_enable(dsi, false); 3806 dsi_vc_enable(dsi, channel, false); 3807 3808 /* MODE, 0 = command mode */ 3809 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4); 3810 3811 dsi_vc_enable(dsi, channel, true); 3812 dsi_if_enable(dsi, true); 3813 } 3814 3815 dss_mgr_disable(&dsi->output); 3816 3817 dsi_display_uninit_dispc(dsi); 3818 } 3819 3820 static void dsi_update_screen_dispc(struct dsi_data *dsi) 3821 { 3822 unsigned int bytespp; 3823 unsigned int bytespl; 3824 unsigned int bytespf; 3825 unsigned int total_len; 3826 unsigned int packet_payload; 3827 unsigned int packet_len; 3828 u32 l; 3829 int r; 3830 const unsigned channel = dsi->update_channel; 3831 const unsigned int line_buf_size = dsi->line_buffer_size; 3832 u16 w = dsi->vm.hactive; 3833 u16 h = dsi->vm.vactive; 3834 3835 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3836 3837 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP); 3838 3839 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3840 bytespl = w * bytespp; 3841 bytespf = bytespl * h; 3842 3843 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3844 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3845 3846 if (bytespf < line_buf_size) 3847 packet_payload = bytespf; 3848 else 3849 packet_payload = (line_buf_size) / bytespl * bytespl; 3850 3851 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3852 total_len = (bytespf / packet_payload) * packet_len; 3853 3854 if (bytespf % packet_payload) 3855 total_len += (bytespf % packet_payload) + 1; 3856 3857 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3858 dsi_write_reg(dsi, DSI_VC_TE(channel), l); 3859 3860 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE, 3861 packet_len, 0); 3862 3863 if (dsi->te_enabled) 3864 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3865 else 3866 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3867 dsi_write_reg(dsi, DSI_VC_TE(channel), l); 3868 3869 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3870 * because DSS interrupts are not capable of waking up the CPU and the 3871 * framedone interrupt could be delayed for quite a long time. I think 3872 * the same goes for any DSS interrupts, but for some reason I have not 3873 * seen the problem anywhere else than here. 3874 */ 3875 dispc_disable_sidle(dsi->dss->dispc); 3876 3877 dsi_perf_mark_start(dsi); 3878 3879 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3880 msecs_to_jiffies(250)); 3881 BUG_ON(r == 0); 3882 3883 dss_mgr_start_update(&dsi->output); 3884 3885 if (dsi->te_enabled) { 3886 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3887 * for TE is longer than the timer allows */ 3888 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3889 3890 dsi_vc_send_bta(dsi, channel); 3891 3892 #ifdef DSI_CATCH_MISSING_TE 3893 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3894 #endif 3895 } 3896 } 3897 3898 #ifdef DSI_CATCH_MISSING_TE 3899 static void dsi_te_timeout(struct timer_list *unused) 3900 { 3901 DSSERR("TE not received for 250ms!\n"); 3902 } 3903 #endif 3904 3905 static void dsi_handle_framedone(struct dsi_data *dsi, int error) 3906 { 3907 /* SIDLEMODE back to smart-idle */ 3908 dispc_enable_sidle(dsi->dss->dispc); 3909 3910 if (dsi->te_enabled) { 3911 /* enable LP_RX_TO again after the TE */ 3912 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3913 } 3914 3915 dsi->framedone_callback(error, dsi->framedone_data); 3916 3917 if (!error) 3918 dsi_perf_show(dsi, "DISPC"); 3919 } 3920 3921 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 3922 { 3923 struct dsi_data *dsi = container_of(work, struct dsi_data, 3924 framedone_timeout_work.work); 3925 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 3926 * 250ms which would conflict with this timeout work. What should be 3927 * done is first cancel the transfer on the HW, and then cancel the 3928 * possibly scheduled framedone work. However, cancelling the transfer 3929 * on the HW is buggy, and would probably require resetting the whole 3930 * DSI */ 3931 3932 DSSERR("Framedone not received for 250ms!\n"); 3933 3934 dsi_handle_framedone(dsi, -ETIMEDOUT); 3935 } 3936 3937 static void dsi_framedone_irq_callback(void *data) 3938 { 3939 struct dsi_data *dsi = data; 3940 3941 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 3942 * turns itself off. However, DSI still has the pixels in its buffers, 3943 * and is sending the data. 3944 */ 3945 3946 cancel_delayed_work(&dsi->framedone_timeout_work); 3947 3948 dsi_handle_framedone(dsi, 0); 3949 } 3950 3951 static int dsi_update(struct omap_dss_device *dssdev, int channel, 3952 void (*callback)(int, void *), void *data) 3953 { 3954 struct dsi_data *dsi = to_dsi_data(dssdev); 3955 u16 dw, dh; 3956 3957 dsi_perf_mark_setup(dsi); 3958 3959 dsi->update_channel = channel; 3960 3961 dsi->framedone_callback = callback; 3962 dsi->framedone_data = data; 3963 3964 dw = dsi->vm.hactive; 3965 dh = dsi->vm.vactive; 3966 3967 #ifdef DSI_PERF_MEASURE 3968 dsi->update_bytes = dw * dh * 3969 dsi_get_pixel_size(dsi->pix_fmt) / 8; 3970 #endif 3971 dsi_update_screen_dispc(dsi); 3972 3973 return 0; 3974 } 3975 3976 /* Display funcs */ 3977 3978 static int dsi_configure_dispc_clocks(struct dsi_data *dsi) 3979 { 3980 struct dispc_clock_info dispc_cinfo; 3981 int r; 3982 unsigned long fck; 3983 3984 fck = dsi_get_pll_hsdiv_dispc_rate(dsi); 3985 3986 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 3987 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 3988 3989 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); 3990 if (r) { 3991 DSSERR("Failed to calc dispc clocks\n"); 3992 return r; 3993 } 3994 3995 dsi->mgr_config.clock_info = dispc_cinfo; 3996 3997 return 0; 3998 } 3999 4000 static int dsi_display_init_dispc(struct dsi_data *dsi) 4001 { 4002 enum omap_channel channel = dsi->output.dispc_channel; 4003 int r; 4004 4005 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ? 4006 DSS_CLK_SRC_PLL1_1 : 4007 DSS_CLK_SRC_PLL2_1); 4008 4009 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4010 r = dss_mgr_register_framedone_handler(&dsi->output, 4011 dsi_framedone_irq_callback, dsi); 4012 if (r) { 4013 DSSERR("can't register FRAMEDONE handler\n"); 4014 goto err; 4015 } 4016 4017 dsi->mgr_config.stallmode = true; 4018 dsi->mgr_config.fifohandcheck = true; 4019 } else { 4020 dsi->mgr_config.stallmode = false; 4021 dsi->mgr_config.fifohandcheck = false; 4022 } 4023 4024 r = dsi_configure_dispc_clocks(dsi); 4025 if (r) 4026 goto err1; 4027 4028 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4029 dsi->mgr_config.video_port_width = 4030 dsi_get_pixel_size(dsi->pix_fmt); 4031 dsi->mgr_config.lcden_sig_polarity = 0; 4032 4033 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); 4034 4035 return 0; 4036 err1: 4037 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4038 dss_mgr_unregister_framedone_handler(&dsi->output, 4039 dsi_framedone_irq_callback, dsi); 4040 err: 4041 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); 4042 return r; 4043 } 4044 4045 static void dsi_display_uninit_dispc(struct dsi_data *dsi) 4046 { 4047 enum omap_channel channel = dsi->output.dispc_channel; 4048 4049 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4050 dss_mgr_unregister_framedone_handler(&dsi->output, 4051 dsi_framedone_irq_callback, dsi); 4052 4053 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); 4054 } 4055 4056 static int dsi_configure_dsi_clocks(struct dsi_data *dsi) 4057 { 4058 struct dss_pll_clock_info cinfo; 4059 int r; 4060 4061 cinfo = dsi->user_dsi_cinfo; 4062 4063 r = dss_pll_set_config(&dsi->pll, &cinfo); 4064 if (r) { 4065 DSSERR("Failed to set dsi clocks\n"); 4066 return r; 4067 } 4068 4069 return 0; 4070 } 4071 4072 static int dsi_display_init_dsi(struct dsi_data *dsi) 4073 { 4074 int r; 4075 4076 r = dss_pll_enable(&dsi->pll); 4077 if (r) 4078 return r; 4079 4080 r = dsi_configure_dsi_clocks(dsi); 4081 if (r) 4082 goto err0; 4083 4084 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, 4085 dsi->module_id == 0 ? 4086 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2); 4087 4088 DSSDBG("PLL OK\n"); 4089 4090 if (!dsi->vdds_dsi_enabled) { 4091 r = regulator_enable(dsi->vdds_dsi_reg); 4092 if (r) 4093 goto err1; 4094 4095 dsi->vdds_dsi_enabled = true; 4096 } 4097 4098 r = dsi_cio_init(dsi); 4099 if (r) 4100 goto err2; 4101 4102 _dsi_print_reset_status(dsi); 4103 4104 dsi_proto_timings(dsi); 4105 dsi_set_lp_clk_divisor(dsi); 4106 4107 if (1) 4108 _dsi_print_reset_status(dsi); 4109 4110 r = dsi_proto_config(dsi); 4111 if (r) 4112 goto err3; 4113 4114 /* enable interface */ 4115 dsi_vc_enable(dsi, 0, 1); 4116 dsi_vc_enable(dsi, 1, 1); 4117 dsi_vc_enable(dsi, 2, 1); 4118 dsi_vc_enable(dsi, 3, 1); 4119 dsi_if_enable(dsi, 1); 4120 dsi_force_tx_stop_mode_io(dsi); 4121 4122 return 0; 4123 err3: 4124 dsi_cio_uninit(dsi); 4125 err2: 4126 regulator_disable(dsi->vdds_dsi_reg); 4127 dsi->vdds_dsi_enabled = false; 4128 err1: 4129 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 4130 err0: 4131 dss_pll_disable(&dsi->pll); 4132 4133 return r; 4134 } 4135 4136 static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes, 4137 bool enter_ulps) 4138 { 4139 if (enter_ulps && !dsi->ulps_enabled) 4140 dsi_enter_ulps(dsi); 4141 4142 /* disable interface */ 4143 dsi_if_enable(dsi, 0); 4144 dsi_vc_enable(dsi, 0, 0); 4145 dsi_vc_enable(dsi, 1, 0); 4146 dsi_vc_enable(dsi, 2, 0); 4147 dsi_vc_enable(dsi, 3, 0); 4148 4149 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 4150 dsi_cio_uninit(dsi); 4151 dss_pll_disable(&dsi->pll); 4152 4153 if (disconnect_lanes) { 4154 regulator_disable(dsi->vdds_dsi_reg); 4155 dsi->vdds_dsi_enabled = false; 4156 } 4157 } 4158 4159 static void dsi_display_enable(struct omap_dss_device *dssdev) 4160 { 4161 struct dsi_data *dsi = to_dsi_data(dssdev); 4162 int r; 4163 4164 DSSDBG("dsi_display_enable\n"); 4165 4166 WARN_ON(!dsi_bus_is_locked(dsi)); 4167 4168 mutex_lock(&dsi->lock); 4169 4170 r = dsi_runtime_get(dsi); 4171 if (r) 4172 goto err_get_dsi; 4173 4174 _dsi_initialize_irq(dsi); 4175 4176 r = dsi_display_init_dsi(dsi); 4177 if (r) 4178 goto err_init_dsi; 4179 4180 mutex_unlock(&dsi->lock); 4181 4182 return; 4183 4184 err_init_dsi: 4185 dsi_runtime_put(dsi); 4186 err_get_dsi: 4187 mutex_unlock(&dsi->lock); 4188 DSSDBG("dsi_display_enable FAILED\n"); 4189 } 4190 4191 static void dsi_display_disable(struct omap_dss_device *dssdev, 4192 bool disconnect_lanes, bool enter_ulps) 4193 { 4194 struct dsi_data *dsi = to_dsi_data(dssdev); 4195 4196 DSSDBG("dsi_display_disable\n"); 4197 4198 WARN_ON(!dsi_bus_is_locked(dsi)); 4199 4200 mutex_lock(&dsi->lock); 4201 4202 dsi_sync_vc(dsi, 0); 4203 dsi_sync_vc(dsi, 1); 4204 dsi_sync_vc(dsi, 2); 4205 dsi_sync_vc(dsi, 3); 4206 4207 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps); 4208 4209 dsi_runtime_put(dsi); 4210 4211 mutex_unlock(&dsi->lock); 4212 } 4213 4214 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4215 { 4216 struct dsi_data *dsi = to_dsi_data(dssdev); 4217 4218 dsi->te_enabled = enable; 4219 return 0; 4220 } 4221 4222 #ifdef PRINT_VERBOSE_VM_TIMINGS 4223 static void print_dsi_vm(const char *str, 4224 const struct omap_dss_dsi_videomode_timings *t) 4225 { 4226 unsigned long byteclk = t->hsclk / 4; 4227 int bl, wc, pps, tot; 4228 4229 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4230 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4231 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4232 tot = bl + pps; 4233 4234 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4235 4236 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4237 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4238 str, 4239 byteclk, 4240 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4241 bl, pps, tot, 4242 TO_DSI_T(t->hss), 4243 TO_DSI_T(t->hsa), 4244 TO_DSI_T(t->hse), 4245 TO_DSI_T(t->hbp), 4246 TO_DSI_T(pps), 4247 TO_DSI_T(t->hfp), 4248 4249 TO_DSI_T(bl), 4250 TO_DSI_T(pps), 4251 4252 TO_DSI_T(tot)); 4253 #undef TO_DSI_T 4254 } 4255 4256 static void print_dispc_vm(const char *str, const struct videomode *vm) 4257 { 4258 unsigned long pck = vm->pixelclock; 4259 int hact, bl, tot; 4260 4261 hact = vm->hactive; 4262 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 4263 tot = hact + bl; 4264 4265 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4266 4267 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4268 "%u/%u/%u/%u = %u + %u = %u\n", 4269 str, 4270 pck, 4271 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 4272 bl, hact, tot, 4273 TO_DISPC_T(vm->hsync_len), 4274 TO_DISPC_T(vm->hback_porch), 4275 TO_DISPC_T(hact), 4276 TO_DISPC_T(vm->hfront_porch), 4277 TO_DISPC_T(bl), 4278 TO_DISPC_T(hact), 4279 TO_DISPC_T(tot)); 4280 #undef TO_DISPC_T 4281 } 4282 4283 /* note: this is not quite accurate */ 4284 static void print_dsi_dispc_vm(const char *str, 4285 const struct omap_dss_dsi_videomode_timings *t) 4286 { 4287 struct videomode vm = { 0 }; 4288 unsigned long byteclk = t->hsclk / 4; 4289 unsigned long pck; 4290 u64 dsi_tput; 4291 int dsi_hact, dsi_htot; 4292 4293 dsi_tput = (u64)byteclk * t->ndl * 8; 4294 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4295 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4296 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4297 4298 vm.pixelclock = pck; 4299 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4300 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 4301 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 4302 vm.hactive = t->hact; 4303 4304 print_dispc_vm(str, &vm); 4305 } 4306 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4307 4308 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4309 unsigned long pck, void *data) 4310 { 4311 struct dsi_clk_calc_ctx *ctx = data; 4312 struct videomode *vm = &ctx->vm; 4313 4314 ctx->dispc_cinfo.lck_div = lckd; 4315 ctx->dispc_cinfo.pck_div = pckd; 4316 ctx->dispc_cinfo.lck = lck; 4317 ctx->dispc_cinfo.pck = pck; 4318 4319 *vm = *ctx->config->vm; 4320 vm->pixelclock = pck; 4321 vm->hactive = ctx->config->vm->hactive; 4322 vm->vactive = ctx->config->vm->vactive; 4323 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 4324 vm->vfront_porch = vm->vback_porch = 0; 4325 4326 return true; 4327 } 4328 4329 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4330 void *data) 4331 { 4332 struct dsi_clk_calc_ctx *ctx = data; 4333 4334 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4335 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4336 4337 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 4338 ctx->req_pck_min, ctx->req_pck_max, 4339 dsi_cm_calc_dispc_cb, ctx); 4340 } 4341 4342 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4343 unsigned long clkdco, void *data) 4344 { 4345 struct dsi_clk_calc_ctx *ctx = data; 4346 struct dsi_data *dsi = ctx->dsi; 4347 4348 ctx->dsi_cinfo.n = n; 4349 ctx->dsi_cinfo.m = m; 4350 ctx->dsi_cinfo.fint = fint; 4351 ctx->dsi_cinfo.clkdco = clkdco; 4352 4353 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4354 dsi->data->max_fck_freq, 4355 dsi_cm_calc_hsdiv_cb, ctx); 4356 } 4357 4358 static bool dsi_cm_calc(struct dsi_data *dsi, 4359 const struct omap_dss_dsi_config *cfg, 4360 struct dsi_clk_calc_ctx *ctx) 4361 { 4362 unsigned long clkin; 4363 int bitspp, ndl; 4364 unsigned long pll_min, pll_max; 4365 unsigned long pck, txbyteclk; 4366 4367 clkin = clk_get_rate(dsi->pll.clkin); 4368 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4369 ndl = dsi->num_lanes_used - 1; 4370 4371 /* 4372 * Here we should calculate minimum txbyteclk to be able to send the 4373 * frame in time, and also to handle TE. That's not very simple, though, 4374 * especially as we go to LP between each pixel packet due to HW 4375 * "feature". So let's just estimate very roughly and multiply by 1.5. 4376 */ 4377 pck = cfg->vm->pixelclock; 4378 pck = pck * 3 / 2; 4379 txbyteclk = pck * bitspp / 8 / ndl; 4380 4381 memset(ctx, 0, sizeof(*ctx)); 4382 ctx->dsi = dsi; 4383 ctx->pll = &dsi->pll; 4384 ctx->config = cfg; 4385 ctx->req_pck_min = pck; 4386 ctx->req_pck_nom = pck; 4387 ctx->req_pck_max = pck * 3 / 2; 4388 4389 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4390 pll_max = cfg->hs_clk_max * 4; 4391 4392 return dss_pll_calc_a(ctx->pll, clkin, 4393 pll_min, pll_max, 4394 dsi_cm_calc_pll_cb, ctx); 4395 } 4396 4397 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4398 { 4399 struct dsi_data *dsi = ctx->dsi; 4400 const struct omap_dss_dsi_config *cfg = ctx->config; 4401 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4402 int ndl = dsi->num_lanes_used - 1; 4403 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4404 unsigned long byteclk = hsclk / 4; 4405 4406 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4407 int xres; 4408 int panel_htot, panel_hbl; /* pixels */ 4409 int dispc_htot, dispc_hbl; /* pixels */ 4410 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4411 int hfp, hsa, hbp; 4412 const struct videomode *req_vm; 4413 struct videomode *dispc_vm; 4414 struct omap_dss_dsi_videomode_timings *dsi_vm; 4415 u64 dsi_tput, dispc_tput; 4416 4417 dsi_tput = (u64)byteclk * ndl * 8; 4418 4419 req_vm = cfg->vm; 4420 req_pck_min = ctx->req_pck_min; 4421 req_pck_max = ctx->req_pck_max; 4422 req_pck_nom = ctx->req_pck_nom; 4423 4424 dispc_pck = ctx->dispc_cinfo.pck; 4425 dispc_tput = (u64)dispc_pck * bitspp; 4426 4427 xres = req_vm->hactive; 4428 4429 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 4430 req_vm->hsync_len; 4431 panel_htot = xres + panel_hbl; 4432 4433 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4434 4435 /* 4436 * When there are no line buffers, DISPC and DSI must have the 4437 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4438 */ 4439 if (dsi->line_buffer_size < xres * bitspp / 8) { 4440 if (dispc_tput != dsi_tput) 4441 return false; 4442 } else { 4443 if (dispc_tput < dsi_tput) 4444 return false; 4445 } 4446 4447 /* DSI tput must be over the min requirement */ 4448 if (dsi_tput < (u64)bitspp * req_pck_min) 4449 return false; 4450 4451 /* When non-burst mode, DSI tput must be below max requirement. */ 4452 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4453 if (dsi_tput > (u64)bitspp * req_pck_max) 4454 return false; 4455 } 4456 4457 hss = DIV_ROUND_UP(4, ndl); 4458 4459 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4460 if (ndl == 3 && req_vm->hsync_len == 0) 4461 hse = 1; 4462 else 4463 hse = DIV_ROUND_UP(4, ndl); 4464 } else { 4465 hse = 0; 4466 } 4467 4468 /* DSI htot to match the panel's nominal pck */ 4469 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4470 4471 /* fail if there would be no time for blanking */ 4472 if (dsi_htot < hss + hse + dsi_hact) 4473 return false; 4474 4475 /* total DSI blanking needed to achieve panel's TL */ 4476 dsi_hbl = dsi_htot - dsi_hact; 4477 4478 /* DISPC htot to match the DSI TL */ 4479 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4480 4481 /* verify that the DSI and DISPC TLs are the same */ 4482 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4483 return false; 4484 4485 dispc_hbl = dispc_htot - xres; 4486 4487 /* setup DSI videomode */ 4488 4489 dsi_vm = &ctx->dsi_vm; 4490 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4491 4492 dsi_vm->hsclk = hsclk; 4493 4494 dsi_vm->ndl = ndl; 4495 dsi_vm->bitspp = bitspp; 4496 4497 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4498 hsa = 0; 4499 } else if (ndl == 3 && req_vm->hsync_len == 0) { 4500 hsa = 0; 4501 } else { 4502 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 4503 hsa = max(hsa - hse, 1); 4504 } 4505 4506 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 4507 hbp = max(hbp, 1); 4508 4509 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4510 if (hfp < 1) { 4511 int t; 4512 /* we need to take cycles from hbp */ 4513 4514 t = 1 - hfp; 4515 hbp = max(hbp - t, 1); 4516 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4517 4518 if (hfp < 1 && hsa > 0) { 4519 /* we need to take cycles from hsa */ 4520 t = 1 - hfp; 4521 hsa = max(hsa - t, 1); 4522 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4523 } 4524 } 4525 4526 if (hfp < 1) 4527 return false; 4528 4529 dsi_vm->hss = hss; 4530 dsi_vm->hsa = hsa; 4531 dsi_vm->hse = hse; 4532 dsi_vm->hbp = hbp; 4533 dsi_vm->hact = xres; 4534 dsi_vm->hfp = hfp; 4535 4536 dsi_vm->vsa = req_vm->vsync_len; 4537 dsi_vm->vbp = req_vm->vback_porch; 4538 dsi_vm->vact = req_vm->vactive; 4539 dsi_vm->vfp = req_vm->vfront_porch; 4540 4541 dsi_vm->trans_mode = cfg->trans_mode; 4542 4543 dsi_vm->blanking_mode = 0; 4544 dsi_vm->hsa_blanking_mode = 1; 4545 dsi_vm->hfp_blanking_mode = 1; 4546 dsi_vm->hbp_blanking_mode = 1; 4547 4548 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4549 dsi_vm->window_sync = 4; 4550 4551 /* setup DISPC videomode */ 4552 4553 dispc_vm = &ctx->vm; 4554 *dispc_vm = *req_vm; 4555 dispc_vm->pixelclock = dispc_pck; 4556 4557 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4558 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 4559 req_pck_nom); 4560 hsa = max(hsa, 1); 4561 } else { 4562 hsa = 1; 4563 } 4564 4565 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 4566 hbp = max(hbp, 1); 4567 4568 hfp = dispc_hbl - hsa - hbp; 4569 if (hfp < 1) { 4570 int t; 4571 /* we need to take cycles from hbp */ 4572 4573 t = 1 - hfp; 4574 hbp = max(hbp - t, 1); 4575 hfp = dispc_hbl - hsa - hbp; 4576 4577 if (hfp < 1) { 4578 /* we need to take cycles from hsa */ 4579 t = 1 - hfp; 4580 hsa = max(hsa - t, 1); 4581 hfp = dispc_hbl - hsa - hbp; 4582 } 4583 } 4584 4585 if (hfp < 1) 4586 return false; 4587 4588 dispc_vm->hfront_porch = hfp; 4589 dispc_vm->hsync_len = hsa; 4590 dispc_vm->hback_porch = hbp; 4591 4592 return true; 4593 } 4594 4595 4596 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4597 unsigned long pck, void *data) 4598 { 4599 struct dsi_clk_calc_ctx *ctx = data; 4600 4601 ctx->dispc_cinfo.lck_div = lckd; 4602 ctx->dispc_cinfo.pck_div = pckd; 4603 ctx->dispc_cinfo.lck = lck; 4604 ctx->dispc_cinfo.pck = pck; 4605 4606 if (dsi_vm_calc_blanking(ctx) == false) 4607 return false; 4608 4609 #ifdef PRINT_VERBOSE_VM_TIMINGS 4610 print_dispc_vm("dispc", &ctx->vm); 4611 print_dsi_vm("dsi ", &ctx->dsi_vm); 4612 print_dispc_vm("req ", ctx->config->vm); 4613 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4614 #endif 4615 4616 return true; 4617 } 4618 4619 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4620 void *data) 4621 { 4622 struct dsi_clk_calc_ctx *ctx = data; 4623 unsigned long pck_max; 4624 4625 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4626 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4627 4628 /* 4629 * In burst mode we can let the dispc pck be arbitrarily high, but it 4630 * limits our scaling abilities. So for now, don't aim too high. 4631 */ 4632 4633 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4634 pck_max = ctx->req_pck_max + 10000000; 4635 else 4636 pck_max = ctx->req_pck_max; 4637 4638 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 4639 ctx->req_pck_min, pck_max, 4640 dsi_vm_calc_dispc_cb, ctx); 4641 } 4642 4643 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4644 unsigned long clkdco, void *data) 4645 { 4646 struct dsi_clk_calc_ctx *ctx = data; 4647 struct dsi_data *dsi = ctx->dsi; 4648 4649 ctx->dsi_cinfo.n = n; 4650 ctx->dsi_cinfo.m = m; 4651 ctx->dsi_cinfo.fint = fint; 4652 ctx->dsi_cinfo.clkdco = clkdco; 4653 4654 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4655 dsi->data->max_fck_freq, 4656 dsi_vm_calc_hsdiv_cb, ctx); 4657 } 4658 4659 static bool dsi_vm_calc(struct dsi_data *dsi, 4660 const struct omap_dss_dsi_config *cfg, 4661 struct dsi_clk_calc_ctx *ctx) 4662 { 4663 const struct videomode *vm = cfg->vm; 4664 unsigned long clkin; 4665 unsigned long pll_min; 4666 unsigned long pll_max; 4667 int ndl = dsi->num_lanes_used - 1; 4668 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4669 unsigned long byteclk_min; 4670 4671 clkin = clk_get_rate(dsi->pll.clkin); 4672 4673 memset(ctx, 0, sizeof(*ctx)); 4674 ctx->dsi = dsi; 4675 ctx->pll = &dsi->pll; 4676 ctx->config = cfg; 4677 4678 /* these limits should come from the panel driver */ 4679 ctx->req_pck_min = vm->pixelclock - 1000; 4680 ctx->req_pck_nom = vm->pixelclock; 4681 ctx->req_pck_max = vm->pixelclock + 1000; 4682 4683 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4684 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4685 4686 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4687 pll_max = cfg->hs_clk_max * 4; 4688 } else { 4689 unsigned long byteclk_max; 4690 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4691 ndl * 8); 4692 4693 pll_max = byteclk_max * 4 * 4; 4694 } 4695 4696 return dss_pll_calc_a(ctx->pll, clkin, 4697 pll_min, pll_max, 4698 dsi_vm_calc_pll_cb, ctx); 4699 } 4700 4701 static int dsi_set_config(struct omap_dss_device *dssdev, 4702 const struct omap_dss_dsi_config *config) 4703 { 4704 struct dsi_data *dsi = to_dsi_data(dssdev); 4705 struct dsi_clk_calc_ctx ctx; 4706 bool ok; 4707 int r; 4708 4709 mutex_lock(&dsi->lock); 4710 4711 dsi->pix_fmt = config->pixel_format; 4712 dsi->mode = config->mode; 4713 4714 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4715 ok = dsi_vm_calc(dsi, config, &ctx); 4716 else 4717 ok = dsi_cm_calc(dsi, config, &ctx); 4718 4719 if (!ok) { 4720 DSSERR("failed to find suitable DSI clock settings\n"); 4721 r = -EINVAL; 4722 goto err; 4723 } 4724 4725 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo); 4726 4727 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4728 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4729 if (r) { 4730 DSSERR("failed to find suitable DSI LP clock settings\n"); 4731 goto err; 4732 } 4733 4734 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4735 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4736 4737 dsi->vm = ctx.vm; 4738 4739 /* 4740 * override interlace, logic level and edge related parameters in 4741 * videomode with default values 4742 */ 4743 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4744 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4745 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4746 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4747 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4748 /* 4749 * HACK: These flags should be handled through the omap_dss_device bus 4750 * flags, but this will only be possible when the DSI encoder will be 4751 * converted to the omapdrm-managed encoder model. 4752 */ 4753 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4754 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4755 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4756 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4757 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4758 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4759 4760 dss_mgr_set_timings(&dsi->output, &dsi->vm); 4761 4762 dsi->vm_timings = ctx.dsi_vm; 4763 4764 mutex_unlock(&dsi->lock); 4765 4766 return 0; 4767 err: 4768 mutex_unlock(&dsi->lock); 4769 4770 return r; 4771 } 4772 4773 /* 4774 * Return a hardcoded channel for the DSI output. This should work for 4775 * current use cases, but this can be later expanded to either resolve 4776 * the channel in some more dynamic manner, or get the channel as a user 4777 * parameter. 4778 */ 4779 static enum omap_channel dsi_get_channel(struct dsi_data *dsi) 4780 { 4781 switch (dsi->data->model) { 4782 case DSI_MODEL_OMAP3: 4783 return OMAP_DSS_CHANNEL_LCD; 4784 4785 case DSI_MODEL_OMAP4: 4786 switch (dsi->module_id) { 4787 case 0: 4788 return OMAP_DSS_CHANNEL_LCD; 4789 case 1: 4790 return OMAP_DSS_CHANNEL_LCD2; 4791 default: 4792 DSSWARN("unsupported module id\n"); 4793 return OMAP_DSS_CHANNEL_LCD; 4794 } 4795 4796 case DSI_MODEL_OMAP5: 4797 switch (dsi->module_id) { 4798 case 0: 4799 return OMAP_DSS_CHANNEL_LCD; 4800 case 1: 4801 return OMAP_DSS_CHANNEL_LCD3; 4802 default: 4803 DSSWARN("unsupported module id\n"); 4804 return OMAP_DSS_CHANNEL_LCD; 4805 } 4806 4807 default: 4808 DSSWARN("unsupported DSS version\n"); 4809 return OMAP_DSS_CHANNEL_LCD; 4810 } 4811 } 4812 4813 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4814 { 4815 struct dsi_data *dsi = to_dsi_data(dssdev); 4816 int i; 4817 4818 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4819 if (!dsi->vc[i].dssdev) { 4820 dsi->vc[i].dssdev = dssdev; 4821 *channel = i; 4822 return 0; 4823 } 4824 } 4825 4826 DSSERR("cannot get VC for display %s", dssdev->name); 4827 return -ENOSPC; 4828 } 4829 4830 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4831 { 4832 struct dsi_data *dsi = to_dsi_data(dssdev); 4833 4834 if (vc_id < 0 || vc_id > 3) { 4835 DSSERR("VC ID out of range\n"); 4836 return -EINVAL; 4837 } 4838 4839 if (channel < 0 || channel > 3) { 4840 DSSERR("Virtual Channel out of range\n"); 4841 return -EINVAL; 4842 } 4843 4844 if (dsi->vc[channel].dssdev != dssdev) { 4845 DSSERR("Virtual Channel not allocated to display %s\n", 4846 dssdev->name); 4847 return -EINVAL; 4848 } 4849 4850 dsi->vc[channel].vc_id = vc_id; 4851 4852 return 0; 4853 } 4854 4855 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4856 { 4857 struct dsi_data *dsi = to_dsi_data(dssdev); 4858 4859 if ((channel >= 0 && channel <= 3) && 4860 dsi->vc[channel].dssdev == dssdev) { 4861 dsi->vc[channel].dssdev = NULL; 4862 dsi->vc[channel].vc_id = 0; 4863 } 4864 } 4865 4866 4867 static int dsi_get_clocks(struct dsi_data *dsi) 4868 { 4869 struct clk *clk; 4870 4871 clk = devm_clk_get(dsi->dev, "fck"); 4872 if (IS_ERR(clk)) { 4873 DSSERR("can't get fck\n"); 4874 return PTR_ERR(clk); 4875 } 4876 4877 dsi->dss_clk = clk; 4878 4879 return 0; 4880 } 4881 4882 static int dsi_connect(struct omap_dss_device *src, 4883 struct omap_dss_device *dst) 4884 { 4885 return omapdss_device_connect(dst->dss, dst, dst->next); 4886 } 4887 4888 static void dsi_disconnect(struct omap_dss_device *src, 4889 struct omap_dss_device *dst) 4890 { 4891 omapdss_device_disconnect(dst, dst->next); 4892 } 4893 4894 static const struct omap_dss_device_ops dsi_ops = { 4895 .connect = dsi_connect, 4896 .disconnect = dsi_disconnect, 4897 .enable = dsi_display_enable, 4898 4899 .dsi = { 4900 .bus_lock = dsi_bus_lock, 4901 .bus_unlock = dsi_bus_unlock, 4902 4903 .disable = dsi_display_disable, 4904 4905 .enable_hs = dsi_vc_enable_hs, 4906 4907 .configure_pins = dsi_configure_pins, 4908 .set_config = dsi_set_config, 4909 4910 .enable_video_output = dsi_enable_video_output, 4911 .disable_video_output = dsi_disable_video_output, 4912 4913 .update = dsi_update, 4914 4915 .enable_te = dsi_enable_te, 4916 4917 .request_vc = dsi_request_vc, 4918 .set_vc_id = dsi_set_vc_id, 4919 .release_vc = dsi_release_vc, 4920 4921 .dcs_write = dsi_vc_dcs_write, 4922 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 4923 .dcs_read = dsi_vc_dcs_read, 4924 4925 .gen_write = dsi_vc_generic_write, 4926 .gen_write_nosync = dsi_vc_generic_write_nosync, 4927 .gen_read = dsi_vc_generic_read, 4928 4929 .bta_sync = dsi_vc_send_bta_sync, 4930 4931 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 4932 }, 4933 }; 4934 4935 /* ----------------------------------------------------------------------------- 4936 * PLL 4937 */ 4938 4939 static const struct dss_pll_ops dsi_pll_ops = { 4940 .enable = dsi_pll_enable, 4941 .disable = dsi_pll_disable, 4942 .set_config = dss_pll_write_config_type_a, 4943 }; 4944 4945 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 4946 .type = DSS_PLL_TYPE_A, 4947 4948 .n_max = (1 << 7) - 1, 4949 .m_max = (1 << 11) - 1, 4950 .mX_max = (1 << 4) - 1, 4951 .fint_min = 750000, 4952 .fint_max = 2100000, 4953 .clkdco_low = 1000000000, 4954 .clkdco_max = 1800000000, 4955 4956 .n_msb = 7, 4957 .n_lsb = 1, 4958 .m_msb = 18, 4959 .m_lsb = 8, 4960 4961 .mX_msb[0] = 22, 4962 .mX_lsb[0] = 19, 4963 .mX_msb[1] = 26, 4964 .mX_lsb[1] = 23, 4965 4966 .has_stopmode = true, 4967 .has_freqsel = true, 4968 .has_selfreqdco = false, 4969 .has_refsel = false, 4970 }; 4971 4972 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 4973 .type = DSS_PLL_TYPE_A, 4974 4975 .n_max = (1 << 8) - 1, 4976 .m_max = (1 << 12) - 1, 4977 .mX_max = (1 << 5) - 1, 4978 .fint_min = 500000, 4979 .fint_max = 2500000, 4980 .clkdco_low = 1000000000, 4981 .clkdco_max = 1800000000, 4982 4983 .n_msb = 8, 4984 .n_lsb = 1, 4985 .m_msb = 20, 4986 .m_lsb = 9, 4987 4988 .mX_msb[0] = 25, 4989 .mX_lsb[0] = 21, 4990 .mX_msb[1] = 30, 4991 .mX_lsb[1] = 26, 4992 4993 .has_stopmode = true, 4994 .has_freqsel = false, 4995 .has_selfreqdco = false, 4996 .has_refsel = false, 4997 }; 4998 4999 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5000 .type = DSS_PLL_TYPE_A, 5001 5002 .n_max = (1 << 8) - 1, 5003 .m_max = (1 << 12) - 1, 5004 .mX_max = (1 << 5) - 1, 5005 .fint_min = 150000, 5006 .fint_max = 52000000, 5007 .clkdco_low = 1000000000, 5008 .clkdco_max = 1800000000, 5009 5010 .n_msb = 8, 5011 .n_lsb = 1, 5012 .m_msb = 20, 5013 .m_lsb = 9, 5014 5015 .mX_msb[0] = 25, 5016 .mX_lsb[0] = 21, 5017 .mX_msb[1] = 30, 5018 .mX_lsb[1] = 26, 5019 5020 .has_stopmode = true, 5021 .has_freqsel = false, 5022 .has_selfreqdco = true, 5023 .has_refsel = true, 5024 }; 5025 5026 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi) 5027 { 5028 struct dss_pll *pll = &dsi->pll; 5029 struct clk *clk; 5030 int r; 5031 5032 clk = devm_clk_get(dsi->dev, "sys_clk"); 5033 if (IS_ERR(clk)) { 5034 DSSERR("can't get sys_clk\n"); 5035 return PTR_ERR(clk); 5036 } 5037 5038 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5039 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5040 pll->clkin = clk; 5041 pll->base = dsi->pll_base; 5042 pll->hw = dsi->data->pll_hw; 5043 pll->ops = &dsi_pll_ops; 5044 5045 r = dss_pll_register(dss, pll); 5046 if (r) 5047 return r; 5048 5049 return 0; 5050 } 5051 5052 /* ----------------------------------------------------------------------------- 5053 * Component Bind & Unbind 5054 */ 5055 5056 static int dsi_bind(struct device *dev, struct device *master, void *data) 5057 { 5058 struct dss_device *dss = dss_get_device(master); 5059 struct dsi_data *dsi = dev_get_drvdata(dev); 5060 char name[10]; 5061 u32 rev; 5062 int r; 5063 5064 dsi->dss = dss; 5065 5066 dsi_init_pll_data(dss, dsi); 5067 5068 r = dsi_runtime_get(dsi); 5069 if (r) 5070 return r; 5071 5072 rev = dsi_read_reg(dsi, DSI_REVISION); 5073 dev_dbg(dev, "OMAP DSI rev %d.%d\n", 5074 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5075 5076 dsi->line_buffer_size = dsi_get_line_buf_size(dsi); 5077 5078 dsi_runtime_put(dsi); 5079 5080 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); 5081 dsi->debugfs.regs = dss_debugfs_create_file(dss, name, 5082 dsi_dump_dsi_regs, dsi); 5083 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5084 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); 5085 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, 5086 dsi_dump_dsi_irqs, dsi); 5087 #endif 5088 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); 5089 dsi->debugfs.clks = dss_debugfs_create_file(dss, name, 5090 dsi_dump_dsi_clocks, dsi); 5091 5092 return 0; 5093 } 5094 5095 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5096 { 5097 struct dsi_data *dsi = dev_get_drvdata(dev); 5098 5099 dss_debugfs_remove_file(dsi->debugfs.clks); 5100 dss_debugfs_remove_file(dsi->debugfs.irqs); 5101 dss_debugfs_remove_file(dsi->debugfs.regs); 5102 5103 WARN_ON(dsi->scp_clk_refcount > 0); 5104 5105 dss_pll_unregister(&dsi->pll); 5106 } 5107 5108 static const struct component_ops dsi_component_ops = { 5109 .bind = dsi_bind, 5110 .unbind = dsi_unbind, 5111 }; 5112 5113 /* ----------------------------------------------------------------------------- 5114 * Probe & Remove, Suspend & Resume 5115 */ 5116 5117 static int dsi_init_output(struct dsi_data *dsi) 5118 { 5119 struct omap_dss_device *out = &dsi->output; 5120 int r; 5121 5122 out->dev = dsi->dev; 5123 out->id = dsi->module_id == 0 ? 5124 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5125 5126 out->type = OMAP_DISPLAY_TYPE_DSI; 5127 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5128 out->dispc_channel = dsi_get_channel(dsi); 5129 out->ops = &dsi_ops; 5130 out->owner = THIS_MODULE; 5131 out->of_ports = BIT(0); 5132 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE 5133 | DRM_BUS_FLAG_DE_HIGH 5134 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 5135 5136 r = omapdss_device_init_output(out); 5137 if (r < 0) 5138 return r; 5139 5140 omapdss_device_register(out); 5141 5142 return 0; 5143 } 5144 5145 static void dsi_uninit_output(struct dsi_data *dsi) 5146 { 5147 struct omap_dss_device *out = &dsi->output; 5148 5149 omapdss_device_unregister(out); 5150 omapdss_device_cleanup_output(out); 5151 } 5152 5153 static int dsi_probe_of(struct dsi_data *dsi) 5154 { 5155 struct device_node *node = dsi->dev->of_node; 5156 struct property *prop; 5157 u32 lane_arr[10]; 5158 int len, num_pins; 5159 int r, i; 5160 struct device_node *ep; 5161 struct omap_dsi_pin_config pin_cfg; 5162 5163 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 5164 if (!ep) 5165 return 0; 5166 5167 prop = of_find_property(ep, "lanes", &len); 5168 if (prop == NULL) { 5169 dev_err(dsi->dev, "failed to find lane data\n"); 5170 r = -EINVAL; 5171 goto err; 5172 } 5173 5174 num_pins = len / sizeof(u32); 5175 5176 if (num_pins < 4 || num_pins % 2 != 0 || 5177 num_pins > dsi->num_lanes_supported * 2) { 5178 dev_err(dsi->dev, "bad number of lanes\n"); 5179 r = -EINVAL; 5180 goto err; 5181 } 5182 5183 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5184 if (r) { 5185 dev_err(dsi->dev, "failed to read lane data\n"); 5186 goto err; 5187 } 5188 5189 pin_cfg.num_pins = num_pins; 5190 for (i = 0; i < num_pins; ++i) 5191 pin_cfg.pins[i] = (int)lane_arr[i]; 5192 5193 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5194 if (r) { 5195 dev_err(dsi->dev, "failed to configure pins"); 5196 goto err; 5197 } 5198 5199 of_node_put(ep); 5200 5201 return 0; 5202 5203 err: 5204 of_node_put(ep); 5205 return r; 5206 } 5207 5208 static const struct dsi_of_data dsi_of_data_omap34xx = { 5209 .model = DSI_MODEL_OMAP3, 5210 .pll_hw = &dss_omap3_dsi_pll_hw, 5211 .modules = (const struct dsi_module_id_data[]) { 5212 { .address = 0x4804fc00, .id = 0, }, 5213 { }, 5214 }, 5215 .max_fck_freq = 173000000, 5216 .max_pll_lpdiv = (1 << 13) - 1, 5217 .quirks = DSI_QUIRK_REVERSE_TXCLKESC, 5218 }; 5219 5220 static const struct dsi_of_data dsi_of_data_omap36xx = { 5221 .model = DSI_MODEL_OMAP3, 5222 .pll_hw = &dss_omap3_dsi_pll_hw, 5223 .modules = (const struct dsi_module_id_data[]) { 5224 { .address = 0x4804fc00, .id = 0, }, 5225 { }, 5226 }, 5227 .max_fck_freq = 173000000, 5228 .max_pll_lpdiv = (1 << 13) - 1, 5229 .quirks = DSI_QUIRK_PLL_PWR_BUG, 5230 }; 5231 5232 static const struct dsi_of_data dsi_of_data_omap4 = { 5233 .model = DSI_MODEL_OMAP4, 5234 .pll_hw = &dss_omap4_dsi_pll_hw, 5235 .modules = (const struct dsi_module_id_data[]) { 5236 { .address = 0x58004000, .id = 0, }, 5237 { .address = 0x58005000, .id = 1, }, 5238 { }, 5239 }, 5240 .max_fck_freq = 170000000, 5241 .max_pll_lpdiv = (1 << 13) - 1, 5242 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5243 | DSI_QUIRK_GNQ, 5244 }; 5245 5246 static const struct dsi_of_data dsi_of_data_omap5 = { 5247 .model = DSI_MODEL_OMAP5, 5248 .pll_hw = &dss_omap5_dsi_pll_hw, 5249 .modules = (const struct dsi_module_id_data[]) { 5250 { .address = 0x58004000, .id = 0, }, 5251 { .address = 0x58009000, .id = 1, }, 5252 { }, 5253 }, 5254 .max_fck_freq = 209250000, 5255 .max_pll_lpdiv = (1 << 13) - 1, 5256 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5257 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, 5258 }; 5259 5260 static const struct of_device_id dsi_of_match[] = { 5261 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, 5262 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, 5263 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, 5264 {}, 5265 }; 5266 5267 static const struct soc_device_attribute dsi_soc_devices[] = { 5268 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, 5269 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 5270 { /* sentinel */ } 5271 }; 5272 5273 static int dsi_probe(struct platform_device *pdev) 5274 { 5275 const struct soc_device_attribute *soc; 5276 const struct dsi_module_id_data *d; 5277 struct device *dev = &pdev->dev; 5278 struct dsi_data *dsi; 5279 struct resource *dsi_mem; 5280 struct resource *res; 5281 unsigned int i; 5282 int r; 5283 5284 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 5285 if (!dsi) 5286 return -ENOMEM; 5287 5288 dsi->dev = dev; 5289 dev_set_drvdata(dev, dsi); 5290 5291 spin_lock_init(&dsi->irq_lock); 5292 spin_lock_init(&dsi->errors_lock); 5293 dsi->errors = 0; 5294 5295 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5296 spin_lock_init(&dsi->irq_stats_lock); 5297 dsi->irq_stats.last_reset = jiffies; 5298 #endif 5299 5300 mutex_init(&dsi->lock); 5301 sema_init(&dsi->bus_lock, 1); 5302 5303 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5304 dsi_framedone_timeout_work_callback); 5305 5306 #ifdef DSI_CATCH_MISSING_TE 5307 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 5308 #endif 5309 5310 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto"); 5311 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); 5312 if (IS_ERR(dsi->proto_base)) 5313 return PTR_ERR(dsi->proto_base); 5314 5315 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 5316 dsi->phy_base = devm_ioremap_resource(dev, res); 5317 if (IS_ERR(dsi->phy_base)) 5318 return PTR_ERR(dsi->phy_base); 5319 5320 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); 5321 dsi->pll_base = devm_ioremap_resource(dev, res); 5322 if (IS_ERR(dsi->pll_base)) 5323 return PTR_ERR(dsi->pll_base); 5324 5325 dsi->irq = platform_get_irq(pdev, 0); 5326 if (dsi->irq < 0) { 5327 DSSERR("platform_get_irq failed\n"); 5328 return -ENODEV; 5329 } 5330 5331 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, 5332 IRQF_SHARED, dev_name(dev), dsi); 5333 if (r < 0) { 5334 DSSERR("request_irq failed\n"); 5335 return r; 5336 } 5337 5338 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); 5339 if (IS_ERR(dsi->vdds_dsi_reg)) { 5340 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) 5341 DSSERR("can't get DSI VDD regulator\n"); 5342 return PTR_ERR(dsi->vdds_dsi_reg); 5343 } 5344 5345 soc = soc_device_match(dsi_soc_devices); 5346 if (soc) 5347 dsi->data = soc->data; 5348 else 5349 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; 5350 5351 d = dsi->data->modules; 5352 while (d->address != 0 && d->address != dsi_mem->start) 5353 d++; 5354 5355 if (d->address == 0) { 5356 DSSERR("unsupported DSI module\n"); 5357 return -ENODEV; 5358 } 5359 5360 dsi->module_id = d->id; 5361 5362 if (dsi->data->model == DSI_MODEL_OMAP4 || 5363 dsi->data->model == DSI_MODEL_OMAP5) { 5364 struct device_node *np; 5365 5366 /* 5367 * The OMAP4/5 display DT bindings don't reference the padconf 5368 * syscon. Our only option to retrieve it is to find it by name. 5369 */ 5370 np = of_find_node_by_name(NULL, 5371 dsi->data->model == DSI_MODEL_OMAP4 ? 5372 "omap4_padconf_global" : "omap5_padconf_global"); 5373 if (!np) 5374 return -ENODEV; 5375 5376 dsi->syscon = syscon_node_to_regmap(np); 5377 of_node_put(np); 5378 } 5379 5380 /* DSI VCs initialization */ 5381 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5382 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5383 dsi->vc[i].dssdev = NULL; 5384 dsi->vc[i].vc_id = 0; 5385 } 5386 5387 r = dsi_get_clocks(dsi); 5388 if (r) 5389 return r; 5390 5391 pm_runtime_enable(dev); 5392 5393 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5394 * of data to 3 by default */ 5395 if (dsi->data->quirks & DSI_QUIRK_GNQ) { 5396 dsi_runtime_get(dsi); 5397 /* NB_DATA_LANES */ 5398 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); 5399 dsi_runtime_put(dsi); 5400 } else { 5401 dsi->num_lanes_supported = 3; 5402 } 5403 5404 r = of_platform_populate(dev->of_node, NULL, NULL, dev); 5405 if (r) { 5406 DSSERR("Failed to populate DSI child devices: %d\n", r); 5407 goto err_pm_disable; 5408 } 5409 5410 r = dsi_init_output(dsi); 5411 if (r) 5412 goto err_of_depopulate; 5413 5414 r = dsi_probe_of(dsi); 5415 if (r) { 5416 DSSERR("Invalid DSI DT data\n"); 5417 goto err_uninit_output; 5418 } 5419 5420 r = component_add(&pdev->dev, &dsi_component_ops); 5421 if (r) 5422 goto err_uninit_output; 5423 5424 return 0; 5425 5426 err_uninit_output: 5427 dsi_uninit_output(dsi); 5428 err_of_depopulate: 5429 of_platform_depopulate(dev); 5430 err_pm_disable: 5431 pm_runtime_disable(dev); 5432 return r; 5433 } 5434 5435 static int dsi_remove(struct platform_device *pdev) 5436 { 5437 struct dsi_data *dsi = platform_get_drvdata(pdev); 5438 5439 component_del(&pdev->dev, &dsi_component_ops); 5440 5441 dsi_uninit_output(dsi); 5442 5443 of_platform_depopulate(&pdev->dev); 5444 5445 pm_runtime_disable(&pdev->dev); 5446 5447 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5448 regulator_disable(dsi->vdds_dsi_reg); 5449 dsi->vdds_dsi_enabled = false; 5450 } 5451 5452 return 0; 5453 } 5454 5455 static int dsi_runtime_suspend(struct device *dev) 5456 { 5457 struct dsi_data *dsi = dev_get_drvdata(dev); 5458 5459 dsi->is_enabled = false; 5460 /* ensure the irq handler sees the is_enabled value */ 5461 smp_wmb(); 5462 /* wait for current handler to finish before turning the DSI off */ 5463 synchronize_irq(dsi->irq); 5464 5465 return 0; 5466 } 5467 5468 static int dsi_runtime_resume(struct device *dev) 5469 { 5470 struct dsi_data *dsi = dev_get_drvdata(dev); 5471 5472 dsi->is_enabled = true; 5473 /* ensure the irq handler sees the is_enabled value */ 5474 smp_wmb(); 5475 5476 return 0; 5477 } 5478 5479 static const struct dev_pm_ops dsi_pm_ops = { 5480 .runtime_suspend = dsi_runtime_suspend, 5481 .runtime_resume = dsi_runtime_resume, 5482 }; 5483 5484 struct platform_driver omap_dsihw_driver = { 5485 .probe = dsi_probe, 5486 .remove = dsi_remove, 5487 .driver = { 5488 .name = "omapdss_dsi", 5489 .pm = &dsi_pm_ops, 5490 .of_match_table = dsi_of_match, 5491 .suppress_bind_attrs = true, 5492 }, 5493 }; 5494