1 /* 2 * linux/drivers/video/omap2/dss/dsi.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "DSI" 21 22 #include <linux/kernel.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 #include <linux/io.h> 26 #include <linux/clk.h> 27 #include <linux/device.h> 28 #include <linux/err.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/mutex.h> 32 #include <linux/module.h> 33 #include <linux/semaphore.h> 34 #include <linux/seq_file.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 #include <linux/wait.h> 38 #include <linux/workqueue.h> 39 #include <linux/sched.h> 40 #include <linux/slab.h> 41 #include <linux/debugfs.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/of.h> 44 #include <linux/of_graph.h> 45 #include <linux/of_platform.h> 46 #include <linux/component.h> 47 #include <linux/sys_soc.h> 48 49 #include <video/mipi_display.h> 50 51 #include "omapdss.h" 52 #include "dss.h" 53 54 #define DSI_CATCH_MISSING_TE 55 56 struct dsi_reg { u16 module; u16 idx; }; 57 58 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 59 60 /* DSI Protocol Engine */ 61 62 #define DSI_PROTO 0 63 #define DSI_PROTO_SZ 0x200 64 65 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 66 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 67 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 68 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 69 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 70 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 71 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 72 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 73 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 74 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 75 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 76 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 77 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 78 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 79 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 80 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 81 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 82 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 83 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 84 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 85 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 86 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 87 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 88 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 89 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 90 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 91 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 92 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 93 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 94 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 95 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 96 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 97 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 98 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 99 100 /* DSIPHY_SCP */ 101 102 #define DSI_PHY 1 103 #define DSI_PHY_OFFSET 0x200 104 #define DSI_PHY_SZ 0x40 105 106 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 107 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 108 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 109 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 110 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 111 112 /* DSI_PLL_CTRL_SCP */ 113 114 #define DSI_PLL 2 115 #define DSI_PLL_OFFSET 0x300 116 #define DSI_PLL_SZ 0x20 117 118 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 119 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 120 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 121 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 122 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 123 124 #define REG_GET(dsidev, idx, start, end) \ 125 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 126 127 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ 128 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 129 130 /* Global interrupts */ 131 #define DSI_IRQ_VC0 (1 << 0) 132 #define DSI_IRQ_VC1 (1 << 1) 133 #define DSI_IRQ_VC2 (1 << 2) 134 #define DSI_IRQ_VC3 (1 << 3) 135 #define DSI_IRQ_WAKEUP (1 << 4) 136 #define DSI_IRQ_RESYNC (1 << 5) 137 #define DSI_IRQ_PLL_LOCK (1 << 7) 138 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 139 #define DSI_IRQ_PLL_RECALL (1 << 9) 140 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 141 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 142 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 143 #define DSI_IRQ_TE_TRIGGER (1 << 16) 144 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 145 #define DSI_IRQ_SYNC_LOST (1 << 18) 146 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 147 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 148 #define DSI_IRQ_ERROR_MASK \ 149 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 150 DSI_IRQ_TA_TIMEOUT) 151 #define DSI_IRQ_CHANNEL_MASK 0xf 152 153 /* Virtual channel interrupts */ 154 #define DSI_VC_IRQ_CS (1 << 0) 155 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 156 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 157 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 158 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 159 #define DSI_VC_IRQ_BTA (1 << 5) 160 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 161 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 162 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 163 #define DSI_VC_IRQ_ERROR_MASK \ 164 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 165 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 166 DSI_VC_IRQ_FIFO_TX_UDF) 167 168 /* ComplexIO interrupts */ 169 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 170 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 171 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 172 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 173 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 174 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 175 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 176 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 177 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 178 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 179 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 180 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 181 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 182 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 183 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 184 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 185 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 186 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 187 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 188 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 195 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 196 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 197 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 198 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 199 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 200 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 201 #define DSI_CIO_IRQ_ERROR_MASK \ 202 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 203 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 204 DSI_CIO_IRQ_ERRSYNCESC5 | \ 205 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 206 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 207 DSI_CIO_IRQ_ERRESC5 | \ 208 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 209 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 210 DSI_CIO_IRQ_ERRCONTROL5 | \ 211 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 212 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 213 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 214 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 215 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 216 217 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 218 219 static int dsi_display_init_dispc(struct platform_device *dsidev, 220 enum omap_channel channel); 221 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 222 enum omap_channel channel); 223 224 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 225 226 /* DSI PLL HSDIV indices */ 227 #define HSDIV_DISPC 0 228 #define HSDIV_DSI 1 229 230 #define DSI_MAX_NR_ISRS 2 231 #define DSI_MAX_NR_LANES 5 232 233 enum dsi_model { 234 DSI_MODEL_OMAP3, 235 DSI_MODEL_OMAP4, 236 DSI_MODEL_OMAP5, 237 }; 238 239 enum dsi_lane_function { 240 DSI_LANE_UNUSED = 0, 241 DSI_LANE_CLK, 242 DSI_LANE_DATA1, 243 DSI_LANE_DATA2, 244 DSI_LANE_DATA3, 245 DSI_LANE_DATA4, 246 }; 247 248 struct dsi_lane_config { 249 enum dsi_lane_function function; 250 u8 polarity; 251 }; 252 253 struct dsi_isr_data { 254 omap_dsi_isr_t isr; 255 void *arg; 256 u32 mask; 257 }; 258 259 enum fifo_size { 260 DSI_FIFO_SIZE_0 = 0, 261 DSI_FIFO_SIZE_32 = 1, 262 DSI_FIFO_SIZE_64 = 2, 263 DSI_FIFO_SIZE_96 = 3, 264 DSI_FIFO_SIZE_128 = 4, 265 }; 266 267 enum dsi_vc_source { 268 DSI_VC_SOURCE_L4 = 0, 269 DSI_VC_SOURCE_VP, 270 }; 271 272 struct dsi_irq_stats { 273 unsigned long last_reset; 274 unsigned irq_count; 275 unsigned dsi_irqs[32]; 276 unsigned vc_irqs[4][32]; 277 unsigned cio_irqs[32]; 278 }; 279 280 struct dsi_isr_tables { 281 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 282 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 283 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 284 }; 285 286 struct dsi_clk_calc_ctx { 287 struct platform_device *dsidev; 288 struct dss_pll *pll; 289 290 /* inputs */ 291 292 const struct omap_dss_dsi_config *config; 293 294 unsigned long req_pck_min, req_pck_nom, req_pck_max; 295 296 /* outputs */ 297 298 struct dss_pll_clock_info dsi_cinfo; 299 struct dispc_clock_info dispc_cinfo; 300 301 struct videomode vm; 302 struct omap_dss_dsi_videomode_timings dsi_vm; 303 }; 304 305 struct dsi_lp_clock_info { 306 unsigned long lp_clk; 307 u16 lp_clk_div; 308 }; 309 310 struct dsi_module_id_data { 311 u32 address; 312 int id; 313 }; 314 315 enum dsi_quirks { 316 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */ 317 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1), 318 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2), 319 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3), 320 DSI_QUIRK_GNQ = (1 << 4), 321 DSI_QUIRK_PHY_DCC = (1 << 5), 322 }; 323 324 struct dsi_of_data { 325 enum dsi_model model; 326 const struct dss_pll_hw *pll_hw; 327 const struct dsi_module_id_data *modules; 328 unsigned int max_fck_freq; 329 unsigned int max_pll_lpdiv; 330 enum dsi_quirks quirks; 331 }; 332 333 struct dsi_data { 334 struct platform_device *pdev; 335 void __iomem *proto_base; 336 void __iomem *phy_base; 337 void __iomem *pll_base; 338 339 const struct dsi_of_data *data; 340 int module_id; 341 342 int irq; 343 344 bool is_enabled; 345 346 struct clk *dss_clk; 347 struct regmap *syscon; 348 349 struct dispc_clock_info user_dispc_cinfo; 350 struct dss_pll_clock_info user_dsi_cinfo; 351 352 struct dsi_lp_clock_info user_lp_cinfo; 353 struct dsi_lp_clock_info current_lp_cinfo; 354 355 struct dss_pll pll; 356 357 bool vdds_dsi_enabled; 358 struct regulator *vdds_dsi_reg; 359 360 struct { 361 enum dsi_vc_source source; 362 struct omap_dss_device *dssdev; 363 enum fifo_size tx_fifo_size; 364 enum fifo_size rx_fifo_size; 365 int vc_id; 366 } vc[4]; 367 368 struct mutex lock; 369 struct semaphore bus_lock; 370 371 spinlock_t irq_lock; 372 struct dsi_isr_tables isr_tables; 373 /* space for a copy used by the interrupt handler */ 374 struct dsi_isr_tables isr_tables_copy; 375 376 int update_channel; 377 #ifdef DSI_PERF_MEASURE 378 unsigned update_bytes; 379 #endif 380 381 bool te_enabled; 382 bool ulps_enabled; 383 384 void (*framedone_callback)(int, void *); 385 void *framedone_data; 386 387 struct delayed_work framedone_timeout_work; 388 389 #ifdef DSI_CATCH_MISSING_TE 390 struct timer_list te_timer; 391 #endif 392 393 unsigned long cache_req_pck; 394 unsigned long cache_clk_freq; 395 struct dss_pll_clock_info cache_cinfo; 396 397 u32 errors; 398 spinlock_t errors_lock; 399 #ifdef DSI_PERF_MEASURE 400 ktime_t perf_setup_time; 401 ktime_t perf_start_time; 402 #endif 403 int debug_read; 404 int debug_write; 405 406 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 407 spinlock_t irq_stats_lock; 408 struct dsi_irq_stats irq_stats; 409 #endif 410 411 unsigned num_lanes_supported; 412 unsigned line_buffer_size; 413 414 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 415 unsigned num_lanes_used; 416 417 unsigned scp_clk_refcount; 418 419 struct dss_lcd_mgr_config mgr_config; 420 struct videomode vm; 421 enum omap_dss_dsi_pixel_format pix_fmt; 422 enum omap_dss_dsi_mode mode; 423 struct omap_dss_dsi_videomode_timings vm_timings; 424 425 struct omap_dss_device output; 426 }; 427 428 struct dsi_packet_sent_handler_data { 429 struct platform_device *dsidev; 430 struct completion *completion; 431 }; 432 433 #ifdef DSI_PERF_MEASURE 434 static bool dsi_perf; 435 module_param(dsi_perf, bool, 0644); 436 #endif 437 438 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 439 { 440 return dev_get_drvdata(&dsidev->dev); 441 } 442 443 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 444 { 445 return to_platform_device(dssdev->dev); 446 } 447 448 static struct platform_device *dsi_get_dsidev_from_id(int module) 449 { 450 struct omap_dss_device *out; 451 enum omap_dss_output_id id; 452 453 switch (module) { 454 case 0: 455 id = OMAP_DSS_OUTPUT_DSI1; 456 break; 457 case 1: 458 id = OMAP_DSS_OUTPUT_DSI2; 459 break; 460 default: 461 return NULL; 462 } 463 464 out = omap_dss_get_output(id); 465 466 return out ? to_platform_device(out->dev) : NULL; 467 } 468 469 static inline void dsi_write_reg(struct platform_device *dsidev, 470 const struct dsi_reg idx, u32 val) 471 { 472 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 473 void __iomem *base; 474 475 switch(idx.module) { 476 case DSI_PROTO: base = dsi->proto_base; break; 477 case DSI_PHY: base = dsi->phy_base; break; 478 case DSI_PLL: base = dsi->pll_base; break; 479 default: return; 480 } 481 482 __raw_writel(val, base + idx.idx); 483 } 484 485 static inline u32 dsi_read_reg(struct platform_device *dsidev, 486 const struct dsi_reg idx) 487 { 488 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 489 void __iomem *base; 490 491 switch(idx.module) { 492 case DSI_PROTO: base = dsi->proto_base; break; 493 case DSI_PHY: base = dsi->phy_base; break; 494 case DSI_PLL: base = dsi->pll_base; break; 495 default: return 0; 496 } 497 498 return __raw_readl(base + idx.idx); 499 } 500 501 static void dsi_bus_lock(struct omap_dss_device *dssdev) 502 { 503 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 504 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 505 506 down(&dsi->bus_lock); 507 } 508 509 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 510 { 511 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 512 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 513 514 up(&dsi->bus_lock); 515 } 516 517 static bool dsi_bus_is_locked(struct platform_device *dsidev) 518 { 519 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 520 521 return dsi->bus_lock.count == 0; 522 } 523 524 static void dsi_completion_handler(void *data, u32 mask) 525 { 526 complete((struct completion *)data); 527 } 528 529 static inline int wait_for_bit_change(struct platform_device *dsidev, 530 const struct dsi_reg idx, int bitnum, int value) 531 { 532 unsigned long timeout; 533 ktime_t wait; 534 int t; 535 536 /* first busyloop to see if the bit changes right away */ 537 t = 100; 538 while (t-- > 0) { 539 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 540 return value; 541 } 542 543 /* then loop for 500ms, sleeping for 1ms in between */ 544 timeout = jiffies + msecs_to_jiffies(500); 545 while (time_before(jiffies, timeout)) { 546 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 547 return value; 548 549 wait = ns_to_ktime(1000 * 1000); 550 set_current_state(TASK_UNINTERRUPTIBLE); 551 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 552 } 553 554 return !value; 555 } 556 557 static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 558 { 559 switch (fmt) { 560 case OMAP_DSS_DSI_FMT_RGB888: 561 case OMAP_DSS_DSI_FMT_RGB666: 562 return 24; 563 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 564 return 18; 565 case OMAP_DSS_DSI_FMT_RGB565: 566 return 16; 567 default: 568 BUG(); 569 return 0; 570 } 571 } 572 573 #ifdef DSI_PERF_MEASURE 574 static void dsi_perf_mark_setup(struct platform_device *dsidev) 575 { 576 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 577 dsi->perf_setup_time = ktime_get(); 578 } 579 580 static void dsi_perf_mark_start(struct platform_device *dsidev) 581 { 582 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 583 dsi->perf_start_time = ktime_get(); 584 } 585 586 static void dsi_perf_show(struct platform_device *dsidev, const char *name) 587 { 588 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 589 ktime_t t, setup_time, trans_time; 590 u32 total_bytes; 591 u32 setup_us, trans_us, total_us; 592 593 if (!dsi_perf) 594 return; 595 596 t = ktime_get(); 597 598 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 599 setup_us = (u32)ktime_to_us(setup_time); 600 if (setup_us == 0) 601 setup_us = 1; 602 603 trans_time = ktime_sub(t, dsi->perf_start_time); 604 trans_us = (u32)ktime_to_us(trans_time); 605 if (trans_us == 0) 606 trans_us = 1; 607 608 total_us = setup_us + trans_us; 609 610 total_bytes = dsi->update_bytes; 611 612 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 613 name, 614 setup_us, 615 trans_us, 616 total_us, 617 1000 * 1000 / total_us, 618 total_bytes, 619 total_bytes * 1000 / total_us); 620 } 621 #else 622 static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 623 { 624 } 625 626 static inline void dsi_perf_mark_start(struct platform_device *dsidev) 627 { 628 } 629 630 static inline void dsi_perf_show(struct platform_device *dsidev, 631 const char *name) 632 { 633 } 634 #endif 635 636 static int verbose_irq; 637 638 static void print_irq_status(u32 status) 639 { 640 if (status == 0) 641 return; 642 643 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 644 return; 645 646 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 647 648 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 649 status, 650 verbose_irq ? PIS(VC0) : "", 651 verbose_irq ? PIS(VC1) : "", 652 verbose_irq ? PIS(VC2) : "", 653 verbose_irq ? PIS(VC3) : "", 654 PIS(WAKEUP), 655 PIS(RESYNC), 656 PIS(PLL_LOCK), 657 PIS(PLL_UNLOCK), 658 PIS(PLL_RECALL), 659 PIS(COMPLEXIO_ERR), 660 PIS(HS_TX_TIMEOUT), 661 PIS(LP_RX_TIMEOUT), 662 PIS(TE_TRIGGER), 663 PIS(ACK_TRIGGER), 664 PIS(SYNC_LOST), 665 PIS(LDO_POWER_GOOD), 666 PIS(TA_TIMEOUT)); 667 #undef PIS 668 } 669 670 static void print_irq_status_vc(int channel, u32 status) 671 { 672 if (status == 0) 673 return; 674 675 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 676 return; 677 678 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 679 680 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 681 channel, 682 status, 683 PIS(CS), 684 PIS(ECC_CORR), 685 PIS(ECC_NO_CORR), 686 verbose_irq ? PIS(PACKET_SENT) : "", 687 PIS(BTA), 688 PIS(FIFO_TX_OVF), 689 PIS(FIFO_RX_OVF), 690 PIS(FIFO_TX_UDF), 691 PIS(PP_BUSY_CHANGE)); 692 #undef PIS 693 } 694 695 static void print_irq_status_cio(u32 status) 696 { 697 if (status == 0) 698 return; 699 700 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 701 702 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 703 status, 704 PIS(ERRSYNCESC1), 705 PIS(ERRSYNCESC2), 706 PIS(ERRSYNCESC3), 707 PIS(ERRESC1), 708 PIS(ERRESC2), 709 PIS(ERRESC3), 710 PIS(ERRCONTROL1), 711 PIS(ERRCONTROL2), 712 PIS(ERRCONTROL3), 713 PIS(STATEULPS1), 714 PIS(STATEULPS2), 715 PIS(STATEULPS3), 716 PIS(ERRCONTENTIONLP0_1), 717 PIS(ERRCONTENTIONLP1_1), 718 PIS(ERRCONTENTIONLP0_2), 719 PIS(ERRCONTENTIONLP1_2), 720 PIS(ERRCONTENTIONLP0_3), 721 PIS(ERRCONTENTIONLP1_3), 722 PIS(ULPSACTIVENOT_ALL0), 723 PIS(ULPSACTIVENOT_ALL1)); 724 #undef PIS 725 } 726 727 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 728 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 729 u32 *vcstatus, u32 ciostatus) 730 { 731 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 732 int i; 733 734 spin_lock(&dsi->irq_stats_lock); 735 736 dsi->irq_stats.irq_count++; 737 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 738 739 for (i = 0; i < 4; ++i) 740 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 741 742 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 743 744 spin_unlock(&dsi->irq_stats_lock); 745 } 746 #else 747 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 748 #endif 749 750 static int debug_irq; 751 752 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 753 u32 *vcstatus, u32 ciostatus) 754 { 755 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 756 int i; 757 758 if (irqstatus & DSI_IRQ_ERROR_MASK) { 759 DSSERR("DSI error, irqstatus %x\n", irqstatus); 760 print_irq_status(irqstatus); 761 spin_lock(&dsi->errors_lock); 762 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 763 spin_unlock(&dsi->errors_lock); 764 } else if (debug_irq) { 765 print_irq_status(irqstatus); 766 } 767 768 for (i = 0; i < 4; ++i) { 769 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 770 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 771 i, vcstatus[i]); 772 print_irq_status_vc(i, vcstatus[i]); 773 } else if (debug_irq) { 774 print_irq_status_vc(i, vcstatus[i]); 775 } 776 } 777 778 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 779 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 780 print_irq_status_cio(ciostatus); 781 } else if (debug_irq) { 782 print_irq_status_cio(ciostatus); 783 } 784 } 785 786 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 787 unsigned isr_array_size, u32 irqstatus) 788 { 789 struct dsi_isr_data *isr_data; 790 int i; 791 792 for (i = 0; i < isr_array_size; i++) { 793 isr_data = &isr_array[i]; 794 if (isr_data->isr && isr_data->mask & irqstatus) 795 isr_data->isr(isr_data->arg, irqstatus); 796 } 797 } 798 799 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 800 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 801 { 802 int i; 803 804 dsi_call_isrs(isr_tables->isr_table, 805 ARRAY_SIZE(isr_tables->isr_table), 806 irqstatus); 807 808 for (i = 0; i < 4; ++i) { 809 if (vcstatus[i] == 0) 810 continue; 811 dsi_call_isrs(isr_tables->isr_table_vc[i], 812 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 813 vcstatus[i]); 814 } 815 816 if (ciostatus != 0) 817 dsi_call_isrs(isr_tables->isr_table_cio, 818 ARRAY_SIZE(isr_tables->isr_table_cio), 819 ciostatus); 820 } 821 822 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 823 { 824 struct platform_device *dsidev; 825 struct dsi_data *dsi; 826 u32 irqstatus, vcstatus[4], ciostatus; 827 int i; 828 829 dsidev = (struct platform_device *) arg; 830 dsi = dsi_get_dsidrv_data(dsidev); 831 832 if (!dsi->is_enabled) 833 return IRQ_NONE; 834 835 spin_lock(&dsi->irq_lock); 836 837 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 838 839 /* IRQ is not for us */ 840 if (!irqstatus) { 841 spin_unlock(&dsi->irq_lock); 842 return IRQ_NONE; 843 } 844 845 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 846 /* flush posted write */ 847 dsi_read_reg(dsidev, DSI_IRQSTATUS); 848 849 for (i = 0; i < 4; ++i) { 850 if ((irqstatus & (1 << i)) == 0) { 851 vcstatus[i] = 0; 852 continue; 853 } 854 855 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 856 857 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 858 /* flush posted write */ 859 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 860 } 861 862 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 863 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 864 865 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 866 /* flush posted write */ 867 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 868 } else { 869 ciostatus = 0; 870 } 871 872 #ifdef DSI_CATCH_MISSING_TE 873 if (irqstatus & DSI_IRQ_TE_TRIGGER) 874 del_timer(&dsi->te_timer); 875 #endif 876 877 /* make a copy and unlock, so that isrs can unregister 878 * themselves */ 879 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 880 sizeof(dsi->isr_tables)); 881 882 spin_unlock(&dsi->irq_lock); 883 884 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 885 886 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 887 888 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 889 890 return IRQ_HANDLED; 891 } 892 893 /* dsi->irq_lock has to be locked by the caller */ 894 static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 895 struct dsi_isr_data *isr_array, 896 unsigned isr_array_size, u32 default_mask, 897 const struct dsi_reg enable_reg, 898 const struct dsi_reg status_reg) 899 { 900 struct dsi_isr_data *isr_data; 901 u32 mask; 902 u32 old_mask; 903 int i; 904 905 mask = default_mask; 906 907 for (i = 0; i < isr_array_size; i++) { 908 isr_data = &isr_array[i]; 909 910 if (isr_data->isr == NULL) 911 continue; 912 913 mask |= isr_data->mask; 914 } 915 916 old_mask = dsi_read_reg(dsidev, enable_reg); 917 /* clear the irqstatus for newly enabled irqs */ 918 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 919 dsi_write_reg(dsidev, enable_reg, mask); 920 921 /* flush posted writes */ 922 dsi_read_reg(dsidev, enable_reg); 923 dsi_read_reg(dsidev, status_reg); 924 } 925 926 /* dsi->irq_lock has to be locked by the caller */ 927 static void _omap_dsi_set_irqs(struct platform_device *dsidev) 928 { 929 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 930 u32 mask = DSI_IRQ_ERROR_MASK; 931 #ifdef DSI_CATCH_MISSING_TE 932 mask |= DSI_IRQ_TE_TRIGGER; 933 #endif 934 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 935 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 936 DSI_IRQENABLE, DSI_IRQSTATUS); 937 } 938 939 /* dsi->irq_lock has to be locked by the caller */ 940 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 941 { 942 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 943 944 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], 945 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 946 DSI_VC_IRQ_ERROR_MASK, 947 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 948 } 949 950 /* dsi->irq_lock has to be locked by the caller */ 951 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 952 { 953 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 954 955 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, 956 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 957 DSI_CIO_IRQ_ERROR_MASK, 958 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 959 } 960 961 static void _dsi_initialize_irq(struct platform_device *dsidev) 962 { 963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 964 unsigned long flags; 965 int vc; 966 967 spin_lock_irqsave(&dsi->irq_lock, flags); 968 969 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 970 971 _omap_dsi_set_irqs(dsidev); 972 for (vc = 0; vc < 4; ++vc) 973 _omap_dsi_set_irqs_vc(dsidev, vc); 974 _omap_dsi_set_irqs_cio(dsidev); 975 976 spin_unlock_irqrestore(&dsi->irq_lock, flags); 977 } 978 979 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 980 struct dsi_isr_data *isr_array, unsigned isr_array_size) 981 { 982 struct dsi_isr_data *isr_data; 983 int free_idx; 984 int i; 985 986 BUG_ON(isr == NULL); 987 988 /* check for duplicate entry and find a free slot */ 989 free_idx = -1; 990 for (i = 0; i < isr_array_size; i++) { 991 isr_data = &isr_array[i]; 992 993 if (isr_data->isr == isr && isr_data->arg == arg && 994 isr_data->mask == mask) { 995 return -EINVAL; 996 } 997 998 if (isr_data->isr == NULL && free_idx == -1) 999 free_idx = i; 1000 } 1001 1002 if (free_idx == -1) 1003 return -EBUSY; 1004 1005 isr_data = &isr_array[free_idx]; 1006 isr_data->isr = isr; 1007 isr_data->arg = arg; 1008 isr_data->mask = mask; 1009 1010 return 0; 1011 } 1012 1013 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 1014 struct dsi_isr_data *isr_array, unsigned isr_array_size) 1015 { 1016 struct dsi_isr_data *isr_data; 1017 int i; 1018 1019 for (i = 0; i < isr_array_size; i++) { 1020 isr_data = &isr_array[i]; 1021 if (isr_data->isr != isr || isr_data->arg != arg || 1022 isr_data->mask != mask) 1023 continue; 1024 1025 isr_data->isr = NULL; 1026 isr_data->arg = NULL; 1027 isr_data->mask = 0; 1028 1029 return 0; 1030 } 1031 1032 return -EINVAL; 1033 } 1034 1035 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 1036 void *arg, u32 mask) 1037 { 1038 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1039 unsigned long flags; 1040 int r; 1041 1042 spin_lock_irqsave(&dsi->irq_lock, flags); 1043 1044 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1045 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1046 1047 if (r == 0) 1048 _omap_dsi_set_irqs(dsidev); 1049 1050 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1051 1052 return r; 1053 } 1054 1055 static int dsi_unregister_isr(struct platform_device *dsidev, 1056 omap_dsi_isr_t isr, void *arg, u32 mask) 1057 { 1058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1059 unsigned long flags; 1060 int r; 1061 1062 spin_lock_irqsave(&dsi->irq_lock, flags); 1063 1064 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1065 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1066 1067 if (r == 0) 1068 _omap_dsi_set_irqs(dsidev); 1069 1070 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1071 1072 return r; 1073 } 1074 1075 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1076 omap_dsi_isr_t isr, void *arg, u32 mask) 1077 { 1078 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1079 unsigned long flags; 1080 int r; 1081 1082 spin_lock_irqsave(&dsi->irq_lock, flags); 1083 1084 r = _dsi_register_isr(isr, arg, mask, 1085 dsi->isr_tables.isr_table_vc[channel], 1086 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1087 1088 if (r == 0) 1089 _omap_dsi_set_irqs_vc(dsidev, channel); 1090 1091 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1092 1093 return r; 1094 } 1095 1096 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1097 omap_dsi_isr_t isr, void *arg, u32 mask) 1098 { 1099 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1100 unsigned long flags; 1101 int r; 1102 1103 spin_lock_irqsave(&dsi->irq_lock, flags); 1104 1105 r = _dsi_unregister_isr(isr, arg, mask, 1106 dsi->isr_tables.isr_table_vc[channel], 1107 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1108 1109 if (r == 0) 1110 _omap_dsi_set_irqs_vc(dsidev, channel); 1111 1112 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1113 1114 return r; 1115 } 1116 1117 static int dsi_register_isr_cio(struct platform_device *dsidev, 1118 omap_dsi_isr_t isr, void *arg, u32 mask) 1119 { 1120 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1121 unsigned long flags; 1122 int r; 1123 1124 spin_lock_irqsave(&dsi->irq_lock, flags); 1125 1126 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1127 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1128 1129 if (r == 0) 1130 _omap_dsi_set_irqs_cio(dsidev); 1131 1132 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1133 1134 return r; 1135 } 1136 1137 static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1138 omap_dsi_isr_t isr, void *arg, u32 mask) 1139 { 1140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1141 unsigned long flags; 1142 int r; 1143 1144 spin_lock_irqsave(&dsi->irq_lock, flags); 1145 1146 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1147 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1148 1149 if (r == 0) 1150 _omap_dsi_set_irqs_cio(dsidev); 1151 1152 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1153 1154 return r; 1155 } 1156 1157 static u32 dsi_get_errors(struct platform_device *dsidev) 1158 { 1159 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1160 unsigned long flags; 1161 u32 e; 1162 spin_lock_irqsave(&dsi->errors_lock, flags); 1163 e = dsi->errors; 1164 dsi->errors = 0; 1165 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1166 return e; 1167 } 1168 1169 static int dsi_runtime_get(struct platform_device *dsidev) 1170 { 1171 int r; 1172 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1173 1174 DSSDBG("dsi_runtime_get\n"); 1175 1176 r = pm_runtime_get_sync(&dsi->pdev->dev); 1177 WARN_ON(r < 0); 1178 return r < 0 ? r : 0; 1179 } 1180 1181 static void dsi_runtime_put(struct platform_device *dsidev) 1182 { 1183 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1184 int r; 1185 1186 DSSDBG("dsi_runtime_put\n"); 1187 1188 r = pm_runtime_put_sync(&dsi->pdev->dev); 1189 WARN_ON(r < 0 && r != -ENOSYS); 1190 } 1191 1192 static int dsi_regulator_init(struct platform_device *dsidev) 1193 { 1194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1195 struct regulator *vdds_dsi; 1196 1197 if (dsi->vdds_dsi_reg != NULL) 1198 return 0; 1199 1200 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1201 1202 if (IS_ERR(vdds_dsi)) { 1203 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1204 DSSERR("can't get DSI VDD regulator\n"); 1205 return PTR_ERR(vdds_dsi); 1206 } 1207 1208 dsi->vdds_dsi_reg = vdds_dsi; 1209 1210 return 0; 1211 } 1212 1213 static void _dsi_print_reset_status(struct platform_device *dsidev) 1214 { 1215 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1216 u32 l; 1217 int b0, b1, b2; 1218 1219 /* A dummy read using the SCP interface to any DSIPHY register is 1220 * required after DSIPHY reset to complete the reset of the DSI complex 1221 * I/O. */ 1222 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1223 1224 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 1225 b0 = 28; 1226 b1 = 27; 1227 b2 = 26; 1228 } else { 1229 b0 = 24; 1230 b1 = 25; 1231 b2 = 26; 1232 } 1233 1234 #define DSI_FLD_GET(fld, start, end)\ 1235 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1236 1237 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1238 DSI_FLD_GET(PLL_STATUS, 0, 0), 1239 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1240 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1241 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1242 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1243 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1244 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1245 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1246 1247 #undef DSI_FLD_GET 1248 } 1249 1250 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1251 { 1252 DSSDBG("dsi_if_enable(%d)\n", enable); 1253 1254 enable = enable ? 1 : 0; 1255 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1256 1257 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1258 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1259 return -EIO; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1266 { 1267 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1268 1269 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1270 } 1271 1272 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1273 { 1274 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1275 1276 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1277 } 1278 1279 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1280 { 1281 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1282 1283 return dsi->pll.cinfo.clkdco / 16; 1284 } 1285 1286 static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1287 { 1288 unsigned long r; 1289 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1290 1291 if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) { 1292 /* DSI FCLK source is DSS_CLK_FCK */ 1293 r = clk_get_rate(dsi->dss_clk); 1294 } else { 1295 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1296 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1297 } 1298 1299 return r; 1300 } 1301 1302 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1303 unsigned long lp_clk_min, unsigned long lp_clk_max, 1304 struct dsi_lp_clock_info *lp_cinfo) 1305 { 1306 unsigned lp_clk_div; 1307 unsigned long lp_clk; 1308 1309 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1310 lp_clk = dsi_fclk / 2 / lp_clk_div; 1311 1312 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1313 return -EINVAL; 1314 1315 lp_cinfo->lp_clk_div = lp_clk_div; 1316 lp_cinfo->lp_clk = lp_clk; 1317 1318 return 0; 1319 } 1320 1321 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1322 { 1323 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1324 unsigned long dsi_fclk; 1325 unsigned lp_clk_div; 1326 unsigned long lp_clk; 1327 unsigned lpdiv_max = dsi->data->max_pll_lpdiv; 1328 1329 1330 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1331 1332 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1333 return -EINVAL; 1334 1335 dsi_fclk = dsi_fclk_rate(dsidev); 1336 1337 lp_clk = dsi_fclk / 2 / lp_clk_div; 1338 1339 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1340 dsi->current_lp_cinfo.lp_clk = lp_clk; 1341 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1342 1343 /* LP_CLK_DIVISOR */ 1344 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1345 1346 /* LP_RX_SYNCHRO_ENABLE */ 1347 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1348 1349 return 0; 1350 } 1351 1352 static void dsi_enable_scp_clk(struct platform_device *dsidev) 1353 { 1354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1355 1356 if (dsi->scp_clk_refcount++ == 0) 1357 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1358 } 1359 1360 static void dsi_disable_scp_clk(struct platform_device *dsidev) 1361 { 1362 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1363 1364 WARN_ON(dsi->scp_clk_refcount == 0); 1365 if (--dsi->scp_clk_refcount == 0) 1366 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1367 } 1368 1369 enum dsi_pll_power_state { 1370 DSI_PLL_POWER_OFF = 0x0, 1371 DSI_PLL_POWER_ON_HSCLK = 0x1, 1372 DSI_PLL_POWER_ON_ALL = 0x2, 1373 DSI_PLL_POWER_ON_DIV = 0x3, 1374 }; 1375 1376 static int dsi_pll_power(struct platform_device *dsidev, 1377 enum dsi_pll_power_state state) 1378 { 1379 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1380 int t = 0; 1381 1382 /* DSI-PLL power command 0x3 is not working */ 1383 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && 1384 state == DSI_PLL_POWER_ON_DIV) 1385 state = DSI_PLL_POWER_ON_ALL; 1386 1387 /* PLL_PWR_CMD */ 1388 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1389 1390 /* PLL_PWR_STATUS */ 1391 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1392 if (++t > 1000) { 1393 DSSERR("Failed to set DSI PLL power mode to %d\n", 1394 state); 1395 return -ENODEV; 1396 } 1397 udelay(1); 1398 } 1399 1400 return 0; 1401 } 1402 1403 1404 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, 1405 struct dss_pll_clock_info *cinfo) 1406 { 1407 unsigned long max_dsi_fck; 1408 1409 max_dsi_fck = dsi->data->max_fck_freq; 1410 1411 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1412 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1413 } 1414 1415 static int dsi_pll_enable(struct dss_pll *pll) 1416 { 1417 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1418 struct platform_device *dsidev = dsi->pdev; 1419 int r = 0; 1420 1421 DSSDBG("PLL init\n"); 1422 1423 r = dsi_regulator_init(dsidev); 1424 if (r) 1425 return r; 1426 1427 r = dsi_runtime_get(dsidev); 1428 if (r) 1429 return r; 1430 1431 /* 1432 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1433 */ 1434 dsi_enable_scp_clk(dsidev); 1435 1436 if (!dsi->vdds_dsi_enabled) { 1437 r = regulator_enable(dsi->vdds_dsi_reg); 1438 if (r) 1439 goto err0; 1440 dsi->vdds_dsi_enabled = true; 1441 } 1442 1443 /* XXX PLL does not come out of reset without this... */ 1444 dispc_pck_free_enable(1); 1445 1446 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1447 DSSERR("PLL not coming out of reset.\n"); 1448 r = -ENODEV; 1449 dispc_pck_free_enable(0); 1450 goto err1; 1451 } 1452 1453 /* XXX ... but if left on, we get problems when planes do not 1454 * fill the whole display. No idea about this */ 1455 dispc_pck_free_enable(0); 1456 1457 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1458 1459 if (r) 1460 goto err1; 1461 1462 DSSDBG("PLL init done\n"); 1463 1464 return 0; 1465 err1: 1466 if (dsi->vdds_dsi_enabled) { 1467 regulator_disable(dsi->vdds_dsi_reg); 1468 dsi->vdds_dsi_enabled = false; 1469 } 1470 err0: 1471 dsi_disable_scp_clk(dsidev); 1472 dsi_runtime_put(dsidev); 1473 return r; 1474 } 1475 1476 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1477 { 1478 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1479 1480 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); 1481 if (disconnect_lanes) { 1482 WARN_ON(!dsi->vdds_dsi_enabled); 1483 regulator_disable(dsi->vdds_dsi_reg); 1484 dsi->vdds_dsi_enabled = false; 1485 } 1486 1487 dsi_disable_scp_clk(dsidev); 1488 dsi_runtime_put(dsidev); 1489 1490 DSSDBG("PLL uninit done\n"); 1491 } 1492 1493 static void dsi_pll_disable(struct dss_pll *pll) 1494 { 1495 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1496 struct platform_device *dsidev = dsi->pdev; 1497 1498 dsi_pll_uninit(dsidev, true); 1499 } 1500 1501 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1502 struct seq_file *s) 1503 { 1504 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1505 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1506 enum dss_clk_source dispc_clk_src, dsi_clk_src; 1507 int dsi_module = dsi->module_id; 1508 struct dss_pll *pll = &dsi->pll; 1509 1510 dispc_clk_src = dss_get_dispc_clk_source(); 1511 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1512 1513 if (dsi_runtime_get(dsidev)) 1514 return; 1515 1516 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1517 1518 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1519 1520 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1521 1522 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1523 cinfo->clkdco, cinfo->m); 1524 1525 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1526 dss_get_clk_source_name(dsi_module == 0 ? 1527 DSS_CLK_SRC_PLL1_1 : 1528 DSS_CLK_SRC_PLL2_1), 1529 cinfo->clkout[HSDIV_DISPC], 1530 cinfo->mX[HSDIV_DISPC], 1531 dispc_clk_src == DSS_CLK_SRC_FCK ? 1532 "off" : "on"); 1533 1534 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1535 dss_get_clk_source_name(dsi_module == 0 ? 1536 DSS_CLK_SRC_PLL1_2 : 1537 DSS_CLK_SRC_PLL2_2), 1538 cinfo->clkout[HSDIV_DSI], 1539 cinfo->mX[HSDIV_DSI], 1540 dsi_clk_src == DSS_CLK_SRC_FCK ? 1541 "off" : "on"); 1542 1543 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1544 1545 seq_printf(s, "dsi fclk source = %s\n", 1546 dss_get_clk_source_name(dsi_clk_src)); 1547 1548 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1549 1550 seq_printf(s, "DDR_CLK\t\t%lu\n", 1551 cinfo->clkdco / 4); 1552 1553 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1554 1555 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1556 1557 dsi_runtime_put(dsidev); 1558 } 1559 1560 void dsi_dump_clocks(struct seq_file *s) 1561 { 1562 struct platform_device *dsidev; 1563 int i; 1564 1565 for (i = 0; i < MAX_NUM_DSI; i++) { 1566 dsidev = dsi_get_dsidev_from_id(i); 1567 if (dsidev) 1568 dsi_dump_dsidev_clocks(dsidev, s); 1569 } 1570 } 1571 1572 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1573 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1574 struct seq_file *s) 1575 { 1576 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1577 unsigned long flags; 1578 struct dsi_irq_stats stats; 1579 1580 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1581 1582 stats = dsi->irq_stats; 1583 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1584 dsi->irq_stats.last_reset = jiffies; 1585 1586 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1587 1588 seq_printf(s, "period %u ms\n", 1589 jiffies_to_msecs(jiffies - stats.last_reset)); 1590 1591 seq_printf(s, "irqs %d\n", stats.irq_count); 1592 #define PIS(x) \ 1593 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1594 1595 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1596 PIS(VC0); 1597 PIS(VC1); 1598 PIS(VC2); 1599 PIS(VC3); 1600 PIS(WAKEUP); 1601 PIS(RESYNC); 1602 PIS(PLL_LOCK); 1603 PIS(PLL_UNLOCK); 1604 PIS(PLL_RECALL); 1605 PIS(COMPLEXIO_ERR); 1606 PIS(HS_TX_TIMEOUT); 1607 PIS(LP_RX_TIMEOUT); 1608 PIS(TE_TRIGGER); 1609 PIS(ACK_TRIGGER); 1610 PIS(SYNC_LOST); 1611 PIS(LDO_POWER_GOOD); 1612 PIS(TA_TIMEOUT); 1613 #undef PIS 1614 1615 #define PIS(x) \ 1616 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1617 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1618 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1619 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1620 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1621 1622 seq_printf(s, "-- VC interrupts --\n"); 1623 PIS(CS); 1624 PIS(ECC_CORR); 1625 PIS(PACKET_SENT); 1626 PIS(FIFO_TX_OVF); 1627 PIS(FIFO_RX_OVF); 1628 PIS(BTA); 1629 PIS(ECC_NO_CORR); 1630 PIS(FIFO_TX_UDF); 1631 PIS(PP_BUSY_CHANGE); 1632 #undef PIS 1633 1634 #define PIS(x) \ 1635 seq_printf(s, "%-20s %10d\n", #x, \ 1636 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1637 1638 seq_printf(s, "-- CIO interrupts --\n"); 1639 PIS(ERRSYNCESC1); 1640 PIS(ERRSYNCESC2); 1641 PIS(ERRSYNCESC3); 1642 PIS(ERRESC1); 1643 PIS(ERRESC2); 1644 PIS(ERRESC3); 1645 PIS(ERRCONTROL1); 1646 PIS(ERRCONTROL2); 1647 PIS(ERRCONTROL3); 1648 PIS(STATEULPS1); 1649 PIS(STATEULPS2); 1650 PIS(STATEULPS3); 1651 PIS(ERRCONTENTIONLP0_1); 1652 PIS(ERRCONTENTIONLP1_1); 1653 PIS(ERRCONTENTIONLP0_2); 1654 PIS(ERRCONTENTIONLP1_2); 1655 PIS(ERRCONTENTIONLP0_3); 1656 PIS(ERRCONTENTIONLP1_3); 1657 PIS(ULPSACTIVENOT_ALL0); 1658 PIS(ULPSACTIVENOT_ALL1); 1659 #undef PIS 1660 } 1661 1662 static void dsi1_dump_irqs(struct seq_file *s) 1663 { 1664 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1665 1666 dsi_dump_dsidev_irqs(dsidev, s); 1667 } 1668 1669 static void dsi2_dump_irqs(struct seq_file *s) 1670 { 1671 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1672 1673 dsi_dump_dsidev_irqs(dsidev, s); 1674 } 1675 #endif 1676 1677 static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1678 struct seq_file *s) 1679 { 1680 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1681 1682 if (dsi_runtime_get(dsidev)) 1683 return; 1684 dsi_enable_scp_clk(dsidev); 1685 1686 DUMPREG(DSI_REVISION); 1687 DUMPREG(DSI_SYSCONFIG); 1688 DUMPREG(DSI_SYSSTATUS); 1689 DUMPREG(DSI_IRQSTATUS); 1690 DUMPREG(DSI_IRQENABLE); 1691 DUMPREG(DSI_CTRL); 1692 DUMPREG(DSI_COMPLEXIO_CFG1); 1693 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1694 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1695 DUMPREG(DSI_CLK_CTRL); 1696 DUMPREG(DSI_TIMING1); 1697 DUMPREG(DSI_TIMING2); 1698 DUMPREG(DSI_VM_TIMING1); 1699 DUMPREG(DSI_VM_TIMING2); 1700 DUMPREG(DSI_VM_TIMING3); 1701 DUMPREG(DSI_CLK_TIMING); 1702 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1703 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1704 DUMPREG(DSI_COMPLEXIO_CFG2); 1705 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1706 DUMPREG(DSI_VM_TIMING4); 1707 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1708 DUMPREG(DSI_VM_TIMING5); 1709 DUMPREG(DSI_VM_TIMING6); 1710 DUMPREG(DSI_VM_TIMING7); 1711 DUMPREG(DSI_STOPCLK_TIMING); 1712 1713 DUMPREG(DSI_VC_CTRL(0)); 1714 DUMPREG(DSI_VC_TE(0)); 1715 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1716 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1717 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1718 DUMPREG(DSI_VC_IRQSTATUS(0)); 1719 DUMPREG(DSI_VC_IRQENABLE(0)); 1720 1721 DUMPREG(DSI_VC_CTRL(1)); 1722 DUMPREG(DSI_VC_TE(1)); 1723 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1724 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1725 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1726 DUMPREG(DSI_VC_IRQSTATUS(1)); 1727 DUMPREG(DSI_VC_IRQENABLE(1)); 1728 1729 DUMPREG(DSI_VC_CTRL(2)); 1730 DUMPREG(DSI_VC_TE(2)); 1731 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1732 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1733 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1734 DUMPREG(DSI_VC_IRQSTATUS(2)); 1735 DUMPREG(DSI_VC_IRQENABLE(2)); 1736 1737 DUMPREG(DSI_VC_CTRL(3)); 1738 DUMPREG(DSI_VC_TE(3)); 1739 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1740 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1741 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1742 DUMPREG(DSI_VC_IRQSTATUS(3)); 1743 DUMPREG(DSI_VC_IRQENABLE(3)); 1744 1745 DUMPREG(DSI_DSIPHY_CFG0); 1746 DUMPREG(DSI_DSIPHY_CFG1); 1747 DUMPREG(DSI_DSIPHY_CFG2); 1748 DUMPREG(DSI_DSIPHY_CFG5); 1749 1750 DUMPREG(DSI_PLL_CONTROL); 1751 DUMPREG(DSI_PLL_STATUS); 1752 DUMPREG(DSI_PLL_GO); 1753 DUMPREG(DSI_PLL_CONFIGURATION1); 1754 DUMPREG(DSI_PLL_CONFIGURATION2); 1755 1756 dsi_disable_scp_clk(dsidev); 1757 dsi_runtime_put(dsidev); 1758 #undef DUMPREG 1759 } 1760 1761 static void dsi1_dump_regs(struct seq_file *s) 1762 { 1763 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1764 1765 dsi_dump_dsidev_regs(dsidev, s); 1766 } 1767 1768 static void dsi2_dump_regs(struct seq_file *s) 1769 { 1770 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1771 1772 dsi_dump_dsidev_regs(dsidev, s); 1773 } 1774 1775 enum dsi_cio_power_state { 1776 DSI_COMPLEXIO_POWER_OFF = 0x0, 1777 DSI_COMPLEXIO_POWER_ON = 0x1, 1778 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1779 }; 1780 1781 static int dsi_cio_power(struct platform_device *dsidev, 1782 enum dsi_cio_power_state state) 1783 { 1784 int t = 0; 1785 1786 /* PWR_CMD */ 1787 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1788 1789 /* PWR_STATUS */ 1790 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1791 26, 25) != state) { 1792 if (++t > 1000) { 1793 DSSERR("failed to set complexio power state to " 1794 "%d\n", state); 1795 return -ENODEV; 1796 } 1797 udelay(1); 1798 } 1799 1800 return 0; 1801 } 1802 1803 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1804 { 1805 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1806 int val; 1807 1808 /* line buffer on OMAP3 is 1024 x 24bits */ 1809 /* XXX: for some reason using full buffer size causes 1810 * considerable TX slowdown with update sizes that fill the 1811 * whole buffer */ 1812 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1813 return 1023 * 3; 1814 1815 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1816 1817 switch (val) { 1818 case 1: 1819 return 512 * 3; /* 512x24 bits */ 1820 case 2: 1821 return 682 * 3; /* 682x24 bits */ 1822 case 3: 1823 return 853 * 3; /* 853x24 bits */ 1824 case 4: 1825 return 1024 * 3; /* 1024x24 bits */ 1826 case 5: 1827 return 1194 * 3; /* 1194x24 bits */ 1828 case 6: 1829 return 1365 * 3; /* 1365x24 bits */ 1830 case 7: 1831 return 1920 * 3; /* 1920x24 bits */ 1832 default: 1833 BUG(); 1834 return 0; 1835 } 1836 } 1837 1838 static int dsi_set_lane_config(struct platform_device *dsidev) 1839 { 1840 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1841 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1842 static const enum dsi_lane_function functions[] = { 1843 DSI_LANE_CLK, 1844 DSI_LANE_DATA1, 1845 DSI_LANE_DATA2, 1846 DSI_LANE_DATA3, 1847 DSI_LANE_DATA4, 1848 }; 1849 u32 r; 1850 int i; 1851 1852 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1853 1854 for (i = 0; i < dsi->num_lanes_used; ++i) { 1855 unsigned offset = offsets[i]; 1856 unsigned polarity, lane_number; 1857 unsigned t; 1858 1859 for (t = 0; t < dsi->num_lanes_supported; ++t) 1860 if (dsi->lanes[t].function == functions[i]) 1861 break; 1862 1863 if (t == dsi->num_lanes_supported) 1864 return -EINVAL; 1865 1866 lane_number = t; 1867 polarity = dsi->lanes[t].polarity; 1868 1869 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1870 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1871 } 1872 1873 /* clear the unused lanes */ 1874 for (; i < dsi->num_lanes_supported; ++i) { 1875 unsigned offset = offsets[i]; 1876 1877 r = FLD_MOD(r, 0, offset + 2, offset); 1878 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1879 } 1880 1881 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1882 1883 return 0; 1884 } 1885 1886 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1887 { 1888 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1889 1890 /* convert time in ns to ddr ticks, rounding up */ 1891 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1892 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1893 } 1894 1895 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1896 { 1897 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1898 1899 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1900 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1901 } 1902 1903 static void dsi_cio_timings(struct platform_device *dsidev) 1904 { 1905 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1906 u32 r; 1907 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1908 u32 tlpx_half, tclk_trail, tclk_zero; 1909 u32 tclk_prepare; 1910 1911 /* calculate timings */ 1912 1913 /* 1 * DDR_CLK = 2 * UI */ 1914 1915 /* min 40ns + 4*UI max 85ns + 6*UI */ 1916 ths_prepare = ns2ddr(dsidev, 70) + 2; 1917 1918 /* min 145ns + 10*UI */ 1919 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1920 1921 /* min max(8*UI, 60ns+4*UI) */ 1922 ths_trail = ns2ddr(dsidev, 60) + 5; 1923 1924 /* min 100ns */ 1925 ths_exit = ns2ddr(dsidev, 145); 1926 1927 /* tlpx min 50n */ 1928 tlpx_half = ns2ddr(dsidev, 25); 1929 1930 /* min 60ns */ 1931 tclk_trail = ns2ddr(dsidev, 60) + 2; 1932 1933 /* min 38ns, max 95ns */ 1934 tclk_prepare = ns2ddr(dsidev, 65); 1935 1936 /* min tclk-prepare + tclk-zero = 300ns */ 1937 tclk_zero = ns2ddr(dsidev, 260); 1938 1939 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1940 ths_prepare, ddr2ns(dsidev, ths_prepare), 1941 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1942 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1943 ths_trail, ddr2ns(dsidev, ths_trail), 1944 ths_exit, ddr2ns(dsidev, ths_exit)); 1945 1946 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1947 "tclk_zero %u (%uns)\n", 1948 tlpx_half, ddr2ns(dsidev, tlpx_half), 1949 tclk_trail, ddr2ns(dsidev, tclk_trail), 1950 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1951 DSSDBG("tclk_prepare %u (%uns)\n", 1952 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1953 1954 /* program timings */ 1955 1956 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1957 r = FLD_MOD(r, ths_prepare, 31, 24); 1958 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1959 r = FLD_MOD(r, ths_trail, 15, 8); 1960 r = FLD_MOD(r, ths_exit, 7, 0); 1961 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1962 1963 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1964 r = FLD_MOD(r, tlpx_half, 20, 16); 1965 r = FLD_MOD(r, tclk_trail, 15, 8); 1966 r = FLD_MOD(r, tclk_zero, 7, 0); 1967 1968 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { 1969 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1970 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1971 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1972 } 1973 1974 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1975 1976 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1977 r = FLD_MOD(r, tclk_prepare, 7, 0); 1978 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1979 } 1980 1981 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1982 static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1983 unsigned mask_p, unsigned mask_n) 1984 { 1985 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1986 int i; 1987 u32 l; 1988 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1989 1990 l = 0; 1991 1992 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1993 unsigned p = dsi->lanes[i].polarity; 1994 1995 if (mask_p & (1 << i)) 1996 l |= 1 << (i * 2 + (p ? 0 : 1)); 1997 1998 if (mask_n & (1 << i)) 1999 l |= 1 << (i * 2 + (p ? 1 : 0)); 2000 } 2001 2002 /* 2003 * Bits in REGLPTXSCPDAT4TO0DXDY: 2004 * 17: DY0 18: DX0 2005 * 19: DY1 20: DX1 2006 * 21: DY2 22: DX2 2007 * 23: DY3 24: DX3 2008 * 25: DY4 26: DX4 2009 */ 2010 2011 /* Set the lane override configuration */ 2012 2013 /* REGLPTXSCPDAT4TO0DXDY */ 2014 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 2015 2016 /* Enable lane override */ 2017 2018 /* ENLPTXSCPDAT */ 2019 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 2020 } 2021 2022 static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 2023 { 2024 /* Disable lane override */ 2025 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 2026 /* Reset the lane override configuration */ 2027 /* REGLPTXSCPDAT4TO0DXDY */ 2028 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 2029 } 2030 2031 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 2032 { 2033 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2034 int t, i; 2035 bool in_use[DSI_MAX_NR_LANES]; 2036 static const u8 offsets_old[] = { 28, 27, 26 }; 2037 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 2038 const u8 *offsets; 2039 2040 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) 2041 offsets = offsets_old; 2042 else 2043 offsets = offsets_new; 2044 2045 for (i = 0; i < dsi->num_lanes_supported; ++i) 2046 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 2047 2048 t = 100000; 2049 while (true) { 2050 u32 l; 2051 int ok; 2052 2053 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2054 2055 ok = 0; 2056 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2057 if (!in_use[i] || (l & (1 << offsets[i]))) 2058 ok++; 2059 } 2060 2061 if (ok == dsi->num_lanes_supported) 2062 break; 2063 2064 if (--t == 0) { 2065 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2066 if (!in_use[i] || (l & (1 << offsets[i]))) 2067 continue; 2068 2069 DSSERR("CIO TXCLKESC%d domain not coming " \ 2070 "out of reset\n", i); 2071 } 2072 return -EIO; 2073 } 2074 } 2075 2076 return 0; 2077 } 2078 2079 /* return bitmask of enabled lanes, lane0 being the lsb */ 2080 static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2081 { 2082 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2083 unsigned mask = 0; 2084 int i; 2085 2086 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2087 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 2088 mask |= 1 << i; 2089 } 2090 2091 return mask; 2092 } 2093 2094 /* OMAP4 CONTROL_DSIPHY */ 2095 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 2096 2097 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 2098 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 2099 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 2100 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 2101 #define OMAP4_DSI1_PIPD_SHIFT 19 2102 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 2103 #define OMAP4_DSI2_PIPD_SHIFT 14 2104 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 2105 2106 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) 2107 { 2108 u32 enable_mask, enable_shift; 2109 u32 pipd_mask, pipd_shift; 2110 2111 if (dsi->module_id == 0) { 2112 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 2113 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 2114 pipd_mask = OMAP4_DSI1_PIPD_MASK; 2115 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 2116 } else if (dsi->module_id == 1) { 2117 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 2118 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 2119 pipd_mask = OMAP4_DSI2_PIPD_MASK; 2120 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 2121 } else { 2122 return -ENODEV; 2123 } 2124 2125 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, 2126 enable_mask | pipd_mask, 2127 (lanes << enable_shift) | (lanes << pipd_shift)); 2128 } 2129 2130 /* OMAP5 CONTROL_DSIPHY */ 2131 2132 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 2133 2134 #define OMAP5_DSI1_LANEENABLE_SHIFT 24 2135 #define OMAP5_DSI2_LANEENABLE_SHIFT 19 2136 #define OMAP5_DSI_LANEENABLE_MASK 0x1f 2137 2138 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) 2139 { 2140 u32 enable_shift; 2141 2142 if (dsi->module_id == 0) 2143 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; 2144 else if (dsi->module_id == 1) 2145 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; 2146 else 2147 return -ENODEV; 2148 2149 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, 2150 OMAP5_DSI_LANEENABLE_MASK << enable_shift, 2151 lanes << enable_shift); 2152 } 2153 2154 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) 2155 { 2156 if (dsi->data->model == DSI_MODEL_OMAP4) 2157 return dsi_omap4_mux_pads(dsi, lane_mask); 2158 if (dsi->data->model == DSI_MODEL_OMAP5) 2159 return dsi_omap5_mux_pads(dsi, lane_mask); 2160 return 0; 2161 } 2162 2163 static void dsi_disable_pads(struct dsi_data *dsi) 2164 { 2165 if (dsi->data->model == DSI_MODEL_OMAP4) 2166 dsi_omap4_mux_pads(dsi, 0); 2167 else if (dsi->data->model == DSI_MODEL_OMAP5) 2168 dsi_omap5_mux_pads(dsi, 0); 2169 } 2170 2171 static int dsi_cio_init(struct platform_device *dsidev) 2172 { 2173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2174 int r; 2175 u32 l; 2176 2177 DSSDBG("DSI CIO init starts"); 2178 2179 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsidev)); 2180 if (r) 2181 return r; 2182 2183 dsi_enable_scp_clk(dsidev); 2184 2185 /* A dummy read using the SCP interface to any DSIPHY register is 2186 * required after DSIPHY reset to complete the reset of the DSI complex 2187 * I/O. */ 2188 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2189 2190 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2191 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2192 r = -EIO; 2193 goto err_scp_clk_dom; 2194 } 2195 2196 r = dsi_set_lane_config(dsidev); 2197 if (r) 2198 goto err_scp_clk_dom; 2199 2200 /* set TX STOP MODE timer to maximum for this operation */ 2201 l = dsi_read_reg(dsidev, DSI_TIMING1); 2202 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2203 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2204 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2205 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2206 dsi_write_reg(dsidev, DSI_TIMING1, l); 2207 2208 if (dsi->ulps_enabled) { 2209 unsigned mask_p; 2210 int i; 2211 2212 DSSDBG("manual ulps exit\n"); 2213 2214 /* ULPS is exited by Mark-1 state for 1ms, followed by 2215 * stop state. DSS HW cannot do this via the normal 2216 * ULPS exit sequence, as after reset the DSS HW thinks 2217 * that we are not in ULPS mode, and refuses to send the 2218 * sequence. So we need to send the ULPS exit sequence 2219 * manually by setting positive lines high and negative lines 2220 * low for 1ms. 2221 */ 2222 2223 mask_p = 0; 2224 2225 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2226 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2227 continue; 2228 mask_p |= 1 << i; 2229 } 2230 2231 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2232 } 2233 2234 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2235 if (r) 2236 goto err_cio_pwr; 2237 2238 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2239 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2240 r = -ENODEV; 2241 goto err_cio_pwr_dom; 2242 } 2243 2244 dsi_if_enable(dsidev, true); 2245 dsi_if_enable(dsidev, false); 2246 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2247 2248 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2249 if (r) 2250 goto err_tx_clk_esc_rst; 2251 2252 if (dsi->ulps_enabled) { 2253 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2254 ktime_t wait = ns_to_ktime(1000 * 1000); 2255 set_current_state(TASK_UNINTERRUPTIBLE); 2256 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2257 2258 /* Disable the override. The lanes should be set to Mark-11 2259 * state by the HW */ 2260 dsi_cio_disable_lane_override(dsidev); 2261 } 2262 2263 /* FORCE_TX_STOP_MODE_IO */ 2264 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2265 2266 dsi_cio_timings(dsidev); 2267 2268 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2269 /* DDR_CLK_ALWAYS_ON */ 2270 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2271 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2272 } 2273 2274 dsi->ulps_enabled = false; 2275 2276 DSSDBG("CIO init done\n"); 2277 2278 return 0; 2279 2280 err_tx_clk_esc_rst: 2281 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2282 err_cio_pwr_dom: 2283 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2284 err_cio_pwr: 2285 if (dsi->ulps_enabled) 2286 dsi_cio_disable_lane_override(dsidev); 2287 err_scp_clk_dom: 2288 dsi_disable_scp_clk(dsidev); 2289 dsi_disable_pads(dsi); 2290 return r; 2291 } 2292 2293 static void dsi_cio_uninit(struct platform_device *dsidev) 2294 { 2295 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2296 2297 /* DDR_CLK_ALWAYS_ON */ 2298 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2299 2300 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2301 dsi_disable_scp_clk(dsidev); 2302 dsi_disable_pads(dsi); 2303 } 2304 2305 static void dsi_config_tx_fifo(struct platform_device *dsidev, 2306 enum fifo_size size1, enum fifo_size size2, 2307 enum fifo_size size3, enum fifo_size size4) 2308 { 2309 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2310 u32 r = 0; 2311 int add = 0; 2312 int i; 2313 2314 dsi->vc[0].tx_fifo_size = size1; 2315 dsi->vc[1].tx_fifo_size = size2; 2316 dsi->vc[2].tx_fifo_size = size3; 2317 dsi->vc[3].tx_fifo_size = size4; 2318 2319 for (i = 0; i < 4; i++) { 2320 u8 v; 2321 int size = dsi->vc[i].tx_fifo_size; 2322 2323 if (add + size > 4) { 2324 DSSERR("Illegal FIFO configuration\n"); 2325 BUG(); 2326 return; 2327 } 2328 2329 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2330 r |= v << (8 * i); 2331 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2332 add += size; 2333 } 2334 2335 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2336 } 2337 2338 static void dsi_config_rx_fifo(struct platform_device *dsidev, 2339 enum fifo_size size1, enum fifo_size size2, 2340 enum fifo_size size3, enum fifo_size size4) 2341 { 2342 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2343 u32 r = 0; 2344 int add = 0; 2345 int i; 2346 2347 dsi->vc[0].rx_fifo_size = size1; 2348 dsi->vc[1].rx_fifo_size = size2; 2349 dsi->vc[2].rx_fifo_size = size3; 2350 dsi->vc[3].rx_fifo_size = size4; 2351 2352 for (i = 0; i < 4; i++) { 2353 u8 v; 2354 int size = dsi->vc[i].rx_fifo_size; 2355 2356 if (add + size > 4) { 2357 DSSERR("Illegal FIFO configuration\n"); 2358 BUG(); 2359 return; 2360 } 2361 2362 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2363 r |= v << (8 * i); 2364 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2365 add += size; 2366 } 2367 2368 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2369 } 2370 2371 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2372 { 2373 u32 r; 2374 2375 r = dsi_read_reg(dsidev, DSI_TIMING1); 2376 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2377 dsi_write_reg(dsidev, DSI_TIMING1, r); 2378 2379 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2380 DSSERR("TX_STOP bit not going down\n"); 2381 return -EIO; 2382 } 2383 2384 return 0; 2385 } 2386 2387 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2388 { 2389 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2390 } 2391 2392 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2393 { 2394 struct dsi_packet_sent_handler_data *vp_data = 2395 (struct dsi_packet_sent_handler_data *) data; 2396 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2397 const int channel = dsi->update_channel; 2398 u8 bit = dsi->te_enabled ? 30 : 31; 2399 2400 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2401 complete(vp_data->completion); 2402 } 2403 2404 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2405 { 2406 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2407 DECLARE_COMPLETION_ONSTACK(completion); 2408 struct dsi_packet_sent_handler_data vp_data = { 2409 .dsidev = dsidev, 2410 .completion = &completion 2411 }; 2412 int r = 0; 2413 u8 bit; 2414 2415 bit = dsi->te_enabled ? 30 : 31; 2416 2417 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2418 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2419 if (r) 2420 goto err0; 2421 2422 /* Wait for completion only if TE_EN/TE_START is still set */ 2423 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2424 if (wait_for_completion_timeout(&completion, 2425 msecs_to_jiffies(10)) == 0) { 2426 DSSERR("Failed to complete previous frame transfer\n"); 2427 r = -EIO; 2428 goto err1; 2429 } 2430 } 2431 2432 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2433 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2434 2435 return 0; 2436 err1: 2437 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2438 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2439 err0: 2440 return r; 2441 } 2442 2443 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2444 { 2445 struct dsi_packet_sent_handler_data *l4_data = 2446 (struct dsi_packet_sent_handler_data *) data; 2447 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2448 const int channel = dsi->update_channel; 2449 2450 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2451 complete(l4_data->completion); 2452 } 2453 2454 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2455 { 2456 DECLARE_COMPLETION_ONSTACK(completion); 2457 struct dsi_packet_sent_handler_data l4_data = { 2458 .dsidev = dsidev, 2459 .completion = &completion 2460 }; 2461 int r = 0; 2462 2463 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2464 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2465 if (r) 2466 goto err0; 2467 2468 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2469 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2470 if (wait_for_completion_timeout(&completion, 2471 msecs_to_jiffies(10)) == 0) { 2472 DSSERR("Failed to complete previous l4 transfer\n"); 2473 r = -EIO; 2474 goto err1; 2475 } 2476 } 2477 2478 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2479 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2480 2481 return 0; 2482 err1: 2483 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2484 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2485 err0: 2486 return r; 2487 } 2488 2489 static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2490 { 2491 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2492 2493 WARN_ON(!dsi_bus_is_locked(dsidev)); 2494 2495 WARN_ON(in_interrupt()); 2496 2497 if (!dsi_vc_is_enabled(dsidev, channel)) 2498 return 0; 2499 2500 switch (dsi->vc[channel].source) { 2501 case DSI_VC_SOURCE_VP: 2502 return dsi_sync_vc_vp(dsidev, channel); 2503 case DSI_VC_SOURCE_L4: 2504 return dsi_sync_vc_l4(dsidev, channel); 2505 default: 2506 BUG(); 2507 return -EINVAL; 2508 } 2509 } 2510 2511 static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2512 bool enable) 2513 { 2514 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2515 channel, enable); 2516 2517 enable = enable ? 1 : 0; 2518 2519 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2520 2521 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2522 0, enable) != enable) { 2523 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2524 return -EIO; 2525 } 2526 2527 return 0; 2528 } 2529 2530 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2531 { 2532 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2533 u32 r; 2534 2535 DSSDBG("Initial config of virtual channel %d", channel); 2536 2537 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2538 2539 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2540 DSSERR("VC(%d) busy when trying to configure it!\n", 2541 channel); 2542 2543 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2544 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2545 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2546 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2547 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2548 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2549 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2550 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) 2551 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2552 2553 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2554 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2555 2556 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2557 2558 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2559 } 2560 2561 static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2562 enum dsi_vc_source source) 2563 { 2564 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2565 2566 if (dsi->vc[channel].source == source) 2567 return 0; 2568 2569 DSSDBG("Source config of virtual channel %d", channel); 2570 2571 dsi_sync_vc(dsidev, channel); 2572 2573 dsi_vc_enable(dsidev, channel, 0); 2574 2575 /* VC_BUSY */ 2576 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2577 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2578 return -EIO; 2579 } 2580 2581 /* SOURCE, 0 = L4, 1 = video port */ 2582 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2583 2584 /* DCS_CMD_ENABLE */ 2585 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { 2586 bool enable = source == DSI_VC_SOURCE_VP; 2587 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2588 } 2589 2590 dsi_vc_enable(dsidev, channel, 1); 2591 2592 dsi->vc[channel].source = source; 2593 2594 return 0; 2595 } 2596 2597 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2598 bool enable) 2599 { 2600 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2601 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2602 2603 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2604 2605 WARN_ON(!dsi_bus_is_locked(dsidev)); 2606 2607 dsi_vc_enable(dsidev, channel, 0); 2608 dsi_if_enable(dsidev, 0); 2609 2610 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2611 2612 dsi_vc_enable(dsidev, channel, 1); 2613 dsi_if_enable(dsidev, 1); 2614 2615 dsi_force_tx_stop_mode_io(dsidev); 2616 2617 /* start the DDR clock by sending a NULL packet */ 2618 if (dsi->vm_timings.ddr_clk_always_on && enable) 2619 dsi_vc_send_null(dssdev, channel); 2620 } 2621 2622 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2623 { 2624 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2625 u32 val; 2626 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2627 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2628 (val >> 0) & 0xff, 2629 (val >> 8) & 0xff, 2630 (val >> 16) & 0xff, 2631 (val >> 24) & 0xff); 2632 } 2633 } 2634 2635 static void dsi_show_rx_ack_with_err(u16 err) 2636 { 2637 DSSERR("\tACK with ERROR (%#x):\n", err); 2638 if (err & (1 << 0)) 2639 DSSERR("\t\tSoT Error\n"); 2640 if (err & (1 << 1)) 2641 DSSERR("\t\tSoT Sync Error\n"); 2642 if (err & (1 << 2)) 2643 DSSERR("\t\tEoT Sync Error\n"); 2644 if (err & (1 << 3)) 2645 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2646 if (err & (1 << 4)) 2647 DSSERR("\t\tLP Transmit Sync Error\n"); 2648 if (err & (1 << 5)) 2649 DSSERR("\t\tHS Receive Timeout Error\n"); 2650 if (err & (1 << 6)) 2651 DSSERR("\t\tFalse Control Error\n"); 2652 if (err & (1 << 7)) 2653 DSSERR("\t\t(reserved7)\n"); 2654 if (err & (1 << 8)) 2655 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2656 if (err & (1 << 9)) 2657 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2658 if (err & (1 << 10)) 2659 DSSERR("\t\tChecksum Error\n"); 2660 if (err & (1 << 11)) 2661 DSSERR("\t\tData type not recognized\n"); 2662 if (err & (1 << 12)) 2663 DSSERR("\t\tInvalid VC ID\n"); 2664 if (err & (1 << 13)) 2665 DSSERR("\t\tInvalid Transmission Length\n"); 2666 if (err & (1 << 14)) 2667 DSSERR("\t\t(reserved14)\n"); 2668 if (err & (1 << 15)) 2669 DSSERR("\t\tDSI Protocol Violation\n"); 2670 } 2671 2672 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2673 int channel) 2674 { 2675 /* RX_FIFO_NOT_EMPTY */ 2676 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2677 u32 val; 2678 u8 dt; 2679 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2680 DSSERR("\trawval %#08x\n", val); 2681 dt = FLD_GET(val, 5, 0); 2682 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2683 u16 err = FLD_GET(val, 23, 8); 2684 dsi_show_rx_ack_with_err(err); 2685 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2686 DSSERR("\tDCS short response, 1 byte: %#x\n", 2687 FLD_GET(val, 23, 8)); 2688 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2689 DSSERR("\tDCS short response, 2 byte: %#x\n", 2690 FLD_GET(val, 23, 8)); 2691 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2692 DSSERR("\tDCS long response, len %d\n", 2693 FLD_GET(val, 23, 8)); 2694 dsi_vc_flush_long_data(dsidev, channel); 2695 } else { 2696 DSSERR("\tunknown datatype 0x%02x\n", dt); 2697 } 2698 } 2699 return 0; 2700 } 2701 2702 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2703 { 2704 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2705 2706 if (dsi->debug_write || dsi->debug_read) 2707 DSSDBG("dsi_vc_send_bta %d\n", channel); 2708 2709 WARN_ON(!dsi_bus_is_locked(dsidev)); 2710 2711 /* RX_FIFO_NOT_EMPTY */ 2712 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2713 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2714 dsi_vc_flush_receive_data(dsidev, channel); 2715 } 2716 2717 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2718 2719 /* flush posted write */ 2720 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2721 2722 return 0; 2723 } 2724 2725 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2726 { 2727 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2728 DECLARE_COMPLETION_ONSTACK(completion); 2729 int r = 0; 2730 u32 err; 2731 2732 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2733 &completion, DSI_VC_IRQ_BTA); 2734 if (r) 2735 goto err0; 2736 2737 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2738 DSI_IRQ_ERROR_MASK); 2739 if (r) 2740 goto err1; 2741 2742 r = dsi_vc_send_bta(dsidev, channel); 2743 if (r) 2744 goto err2; 2745 2746 if (wait_for_completion_timeout(&completion, 2747 msecs_to_jiffies(500)) == 0) { 2748 DSSERR("Failed to receive BTA\n"); 2749 r = -EIO; 2750 goto err2; 2751 } 2752 2753 err = dsi_get_errors(dsidev); 2754 if (err) { 2755 DSSERR("Error while sending BTA: %x\n", err); 2756 r = -EIO; 2757 goto err2; 2758 } 2759 err2: 2760 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2761 DSI_IRQ_ERROR_MASK); 2762 err1: 2763 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2764 &completion, DSI_VC_IRQ_BTA); 2765 err0: 2766 return r; 2767 } 2768 2769 static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2770 int channel, u8 data_type, u16 len, u8 ecc) 2771 { 2772 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2773 u32 val; 2774 u8 data_id; 2775 2776 WARN_ON(!dsi_bus_is_locked(dsidev)); 2777 2778 data_id = data_type | dsi->vc[channel].vc_id << 6; 2779 2780 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2781 FLD_VAL(ecc, 31, 24); 2782 2783 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2784 } 2785 2786 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2787 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2788 { 2789 u32 val; 2790 2791 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2792 2793 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2794 b1, b2, b3, b4, val); */ 2795 2796 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2797 } 2798 2799 static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2800 u8 data_type, u8 *data, u16 len, u8 ecc) 2801 { 2802 /*u32 val; */ 2803 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2804 int i; 2805 u8 *p; 2806 int r = 0; 2807 u8 b1, b2, b3, b4; 2808 2809 if (dsi->debug_write) 2810 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2811 2812 /* len + header */ 2813 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2814 DSSERR("unable to send long packet: packet too long.\n"); 2815 return -EINVAL; 2816 } 2817 2818 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2819 2820 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2821 2822 p = data; 2823 for (i = 0; i < len >> 2; i++) { 2824 if (dsi->debug_write) 2825 DSSDBG("\tsending full packet %d\n", i); 2826 2827 b1 = *p++; 2828 b2 = *p++; 2829 b3 = *p++; 2830 b4 = *p++; 2831 2832 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2833 } 2834 2835 i = len % 4; 2836 if (i) { 2837 b1 = 0; b2 = 0; b3 = 0; 2838 2839 if (dsi->debug_write) 2840 DSSDBG("\tsending remainder bytes %d\n", i); 2841 2842 switch (i) { 2843 case 3: 2844 b1 = *p++; 2845 b2 = *p++; 2846 b3 = *p++; 2847 break; 2848 case 2: 2849 b1 = *p++; 2850 b2 = *p++; 2851 break; 2852 case 1: 2853 b1 = *p++; 2854 break; 2855 } 2856 2857 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2858 } 2859 2860 return r; 2861 } 2862 2863 static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2864 u8 data_type, u16 data, u8 ecc) 2865 { 2866 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2867 u32 r; 2868 u8 data_id; 2869 2870 WARN_ON(!dsi_bus_is_locked(dsidev)); 2871 2872 if (dsi->debug_write) 2873 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2874 channel, 2875 data_type, data & 0xff, (data >> 8) & 0xff); 2876 2877 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2878 2879 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2880 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2881 return -EINVAL; 2882 } 2883 2884 data_id = data_type | dsi->vc[channel].vc_id << 6; 2885 2886 r = (data_id << 0) | (data << 8) | (ecc << 24); 2887 2888 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2889 2890 return 0; 2891 } 2892 2893 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2894 { 2895 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2896 2897 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, 2898 0, 0); 2899 } 2900 2901 static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2902 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2903 { 2904 int r; 2905 2906 if (len == 0) { 2907 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2908 r = dsi_vc_send_short(dsidev, channel, 2909 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2910 } else if (len == 1) { 2911 r = dsi_vc_send_short(dsidev, channel, 2912 type == DSS_DSI_CONTENT_GENERIC ? 2913 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2914 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2915 } else if (len == 2) { 2916 r = dsi_vc_send_short(dsidev, channel, 2917 type == DSS_DSI_CONTENT_GENERIC ? 2918 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2919 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2920 data[0] | (data[1] << 8), 0); 2921 } else { 2922 r = dsi_vc_send_long(dsidev, channel, 2923 type == DSS_DSI_CONTENT_GENERIC ? 2924 MIPI_DSI_GENERIC_LONG_WRITE : 2925 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2926 } 2927 2928 return r; 2929 } 2930 2931 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2932 u8 *data, int len) 2933 { 2934 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2935 2936 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2937 DSS_DSI_CONTENT_DCS); 2938 } 2939 2940 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2941 u8 *data, int len) 2942 { 2943 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2944 2945 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2946 DSS_DSI_CONTENT_GENERIC); 2947 } 2948 2949 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2950 u8 *data, int len, enum dss_dsi_content_type type) 2951 { 2952 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2953 int r; 2954 2955 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2956 if (r) 2957 goto err; 2958 2959 r = dsi_vc_send_bta_sync(dssdev, channel); 2960 if (r) 2961 goto err; 2962 2963 /* RX_FIFO_NOT_EMPTY */ 2964 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2965 DSSERR("rx fifo not empty after write, dumping data:\n"); 2966 dsi_vc_flush_receive_data(dsidev, channel); 2967 r = -EIO; 2968 goto err; 2969 } 2970 2971 return 0; 2972 err: 2973 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2974 channel, data[0], len); 2975 return r; 2976 } 2977 2978 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2979 int len) 2980 { 2981 return dsi_vc_write_common(dssdev, channel, data, len, 2982 DSS_DSI_CONTENT_DCS); 2983 } 2984 2985 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2986 int len) 2987 { 2988 return dsi_vc_write_common(dssdev, channel, data, len, 2989 DSS_DSI_CONTENT_GENERIC); 2990 } 2991 2992 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2993 int channel, u8 dcs_cmd) 2994 { 2995 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2996 int r; 2997 2998 if (dsi->debug_read) 2999 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 3000 channel, dcs_cmd); 3001 3002 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 3003 if (r) { 3004 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 3005 " failed\n", channel, dcs_cmd); 3006 return r; 3007 } 3008 3009 return 0; 3010 } 3011 3012 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 3013 int channel, u8 *reqdata, int reqlen) 3014 { 3015 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3016 u16 data; 3017 u8 data_type; 3018 int r; 3019 3020 if (dsi->debug_read) 3021 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 3022 channel, reqlen); 3023 3024 if (reqlen == 0) { 3025 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 3026 data = 0; 3027 } else if (reqlen == 1) { 3028 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 3029 data = reqdata[0]; 3030 } else if (reqlen == 2) { 3031 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 3032 data = reqdata[0] | (reqdata[1] << 8); 3033 } else { 3034 BUG(); 3035 return -EINVAL; 3036 } 3037 3038 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 3039 if (r) { 3040 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 3041 " failed\n", channel, reqlen); 3042 return r; 3043 } 3044 3045 return 0; 3046 } 3047 3048 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 3049 u8 *buf, int buflen, enum dss_dsi_content_type type) 3050 { 3051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3052 u32 val; 3053 u8 dt; 3054 int r; 3055 3056 /* RX_FIFO_NOT_EMPTY */ 3057 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 3058 DSSERR("RX fifo empty when trying to read.\n"); 3059 r = -EIO; 3060 goto err; 3061 } 3062 3063 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 3064 if (dsi->debug_read) 3065 DSSDBG("\theader: %08x\n", val); 3066 dt = FLD_GET(val, 5, 0); 3067 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 3068 u16 err = FLD_GET(val, 23, 8); 3069 dsi_show_rx_ack_with_err(err); 3070 r = -EIO; 3071 goto err; 3072 3073 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 3074 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 3075 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 3076 u8 data = FLD_GET(val, 15, 8); 3077 if (dsi->debug_read) 3078 DSSDBG("\t%s short response, 1 byte: %02x\n", 3079 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3080 "DCS", data); 3081 3082 if (buflen < 1) { 3083 r = -EIO; 3084 goto err; 3085 } 3086 3087 buf[0] = data; 3088 3089 return 1; 3090 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 3091 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 3092 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 3093 u16 data = FLD_GET(val, 23, 8); 3094 if (dsi->debug_read) 3095 DSSDBG("\t%s short response, 2 byte: %04x\n", 3096 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3097 "DCS", data); 3098 3099 if (buflen < 2) { 3100 r = -EIO; 3101 goto err; 3102 } 3103 3104 buf[0] = data & 0xff; 3105 buf[1] = (data >> 8) & 0xff; 3106 3107 return 2; 3108 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 3109 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 3110 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 3111 int w; 3112 int len = FLD_GET(val, 23, 8); 3113 if (dsi->debug_read) 3114 DSSDBG("\t%s long response, len %d\n", 3115 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3116 "DCS", len); 3117 3118 if (len > buflen) { 3119 r = -EIO; 3120 goto err; 3121 } 3122 3123 /* two byte checksum ends the packet, not included in len */ 3124 for (w = 0; w < len + 2;) { 3125 int b; 3126 val = dsi_read_reg(dsidev, 3127 DSI_VC_SHORT_PACKET_HEADER(channel)); 3128 if (dsi->debug_read) 3129 DSSDBG("\t\t%02x %02x %02x %02x\n", 3130 (val >> 0) & 0xff, 3131 (val >> 8) & 0xff, 3132 (val >> 16) & 0xff, 3133 (val >> 24) & 0xff); 3134 3135 for (b = 0; b < 4; ++b) { 3136 if (w < len) 3137 buf[w] = (val >> (b * 8)) & 0xff; 3138 /* we discard the 2 byte checksum */ 3139 ++w; 3140 } 3141 } 3142 3143 return len; 3144 } else { 3145 DSSERR("\tunknown datatype 0x%02x\n", dt); 3146 r = -EIO; 3147 goto err; 3148 } 3149 3150 err: 3151 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 3152 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 3153 3154 return r; 3155 } 3156 3157 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3158 u8 *buf, int buflen) 3159 { 3160 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3161 int r; 3162 3163 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3164 if (r) 3165 goto err; 3166 3167 r = dsi_vc_send_bta_sync(dssdev, channel); 3168 if (r) 3169 goto err; 3170 3171 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3172 DSS_DSI_CONTENT_DCS); 3173 if (r < 0) 3174 goto err; 3175 3176 if (r != buflen) { 3177 r = -EIO; 3178 goto err; 3179 } 3180 3181 return 0; 3182 err: 3183 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3184 return r; 3185 } 3186 3187 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3188 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3189 { 3190 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3191 int r; 3192 3193 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3194 if (r) 3195 return r; 3196 3197 r = dsi_vc_send_bta_sync(dssdev, channel); 3198 if (r) 3199 return r; 3200 3201 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3202 DSS_DSI_CONTENT_GENERIC); 3203 if (r < 0) 3204 return r; 3205 3206 if (r != buflen) { 3207 r = -EIO; 3208 return r; 3209 } 3210 3211 return 0; 3212 } 3213 3214 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3215 u16 len) 3216 { 3217 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3218 3219 return dsi_vc_send_short(dsidev, channel, 3220 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3221 } 3222 3223 static int dsi_enter_ulps(struct platform_device *dsidev) 3224 { 3225 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3226 DECLARE_COMPLETION_ONSTACK(completion); 3227 int r, i; 3228 unsigned mask; 3229 3230 DSSDBG("Entering ULPS"); 3231 3232 WARN_ON(!dsi_bus_is_locked(dsidev)); 3233 3234 WARN_ON(dsi->ulps_enabled); 3235 3236 if (dsi->ulps_enabled) 3237 return 0; 3238 3239 /* DDR_CLK_ALWAYS_ON */ 3240 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3241 dsi_if_enable(dsidev, 0); 3242 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3243 dsi_if_enable(dsidev, 1); 3244 } 3245 3246 dsi_sync_vc(dsidev, 0); 3247 dsi_sync_vc(dsidev, 1); 3248 dsi_sync_vc(dsidev, 2); 3249 dsi_sync_vc(dsidev, 3); 3250 3251 dsi_force_tx_stop_mode_io(dsidev); 3252 3253 dsi_vc_enable(dsidev, 0, false); 3254 dsi_vc_enable(dsidev, 1, false); 3255 dsi_vc_enable(dsidev, 2, false); 3256 dsi_vc_enable(dsidev, 3, false); 3257 3258 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3259 DSSERR("HS busy when enabling ULPS\n"); 3260 return -EIO; 3261 } 3262 3263 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3264 DSSERR("LP busy when enabling ULPS\n"); 3265 return -EIO; 3266 } 3267 3268 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3269 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3270 if (r) 3271 return r; 3272 3273 mask = 0; 3274 3275 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3276 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3277 continue; 3278 mask |= 1 << i; 3279 } 3280 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3281 /* LANEx_ULPS_SIG2 */ 3282 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3283 3284 /* flush posted write and wait for SCP interface to finish the write */ 3285 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3286 3287 if (wait_for_completion_timeout(&completion, 3288 msecs_to_jiffies(1000)) == 0) { 3289 DSSERR("ULPS enable timeout\n"); 3290 r = -EIO; 3291 goto err; 3292 } 3293 3294 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3295 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3296 3297 /* Reset LANEx_ULPS_SIG2 */ 3298 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3299 3300 /* flush posted write and wait for SCP interface to finish the write */ 3301 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3302 3303 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3304 3305 dsi_if_enable(dsidev, false); 3306 3307 dsi->ulps_enabled = true; 3308 3309 return 0; 3310 3311 err: 3312 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3313 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3314 return r; 3315 } 3316 3317 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3318 unsigned ticks, bool x4, bool x16) 3319 { 3320 unsigned long fck; 3321 unsigned long total_ticks; 3322 u32 r; 3323 3324 BUG_ON(ticks > 0x1fff); 3325 3326 /* ticks in DSI_FCK */ 3327 fck = dsi_fclk_rate(dsidev); 3328 3329 r = dsi_read_reg(dsidev, DSI_TIMING2); 3330 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3331 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3332 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3333 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3334 dsi_write_reg(dsidev, DSI_TIMING2, r); 3335 3336 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3337 3338 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3339 total_ticks, 3340 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3341 (total_ticks * 1000) / (fck / 1000 / 1000)); 3342 } 3343 3344 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3345 bool x8, bool x16) 3346 { 3347 unsigned long fck; 3348 unsigned long total_ticks; 3349 u32 r; 3350 3351 BUG_ON(ticks > 0x1fff); 3352 3353 /* ticks in DSI_FCK */ 3354 fck = dsi_fclk_rate(dsidev); 3355 3356 r = dsi_read_reg(dsidev, DSI_TIMING1); 3357 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3358 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3359 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3360 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3361 dsi_write_reg(dsidev, DSI_TIMING1, r); 3362 3363 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3364 3365 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3366 total_ticks, 3367 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3368 (total_ticks * 1000) / (fck / 1000 / 1000)); 3369 } 3370 3371 static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3372 unsigned ticks, bool x4, bool x16) 3373 { 3374 unsigned long fck; 3375 unsigned long total_ticks; 3376 u32 r; 3377 3378 BUG_ON(ticks > 0x1fff); 3379 3380 /* ticks in DSI_FCK */ 3381 fck = dsi_fclk_rate(dsidev); 3382 3383 r = dsi_read_reg(dsidev, DSI_TIMING1); 3384 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3385 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3386 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3387 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3388 dsi_write_reg(dsidev, DSI_TIMING1, r); 3389 3390 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3391 3392 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3393 total_ticks, 3394 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3395 (total_ticks * 1000) / (fck / 1000 / 1000)); 3396 } 3397 3398 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3399 unsigned ticks, bool x4, bool x16) 3400 { 3401 unsigned long fck; 3402 unsigned long total_ticks; 3403 u32 r; 3404 3405 BUG_ON(ticks > 0x1fff); 3406 3407 /* ticks in TxByteClkHS */ 3408 fck = dsi_get_txbyteclkhs(dsidev); 3409 3410 r = dsi_read_reg(dsidev, DSI_TIMING2); 3411 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3412 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3413 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3414 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3415 dsi_write_reg(dsidev, DSI_TIMING2, r); 3416 3417 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3418 3419 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3420 total_ticks, 3421 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3422 (total_ticks * 1000) / (fck / 1000 / 1000)); 3423 } 3424 3425 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3426 { 3427 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3428 int num_line_buffers; 3429 3430 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3431 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3432 struct videomode *vm = &dsi->vm; 3433 /* 3434 * Don't use line buffers if width is greater than the video 3435 * port's line buffer size 3436 */ 3437 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 3438 num_line_buffers = 0; 3439 else 3440 num_line_buffers = 2; 3441 } else { 3442 /* Use maximum number of line buffers in command mode */ 3443 num_line_buffers = 2; 3444 } 3445 3446 /* LINE_BUFFER */ 3447 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3448 } 3449 3450 static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3451 { 3452 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3453 bool sync_end; 3454 u32 r; 3455 3456 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3457 sync_end = true; 3458 else 3459 sync_end = false; 3460 3461 r = dsi_read_reg(dsidev, DSI_CTRL); 3462 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3463 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3464 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3465 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3466 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3467 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3468 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3469 dsi_write_reg(dsidev, DSI_CTRL, r); 3470 } 3471 3472 static void dsi_config_blanking_modes(struct platform_device *dsidev) 3473 { 3474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3475 int blanking_mode = dsi->vm_timings.blanking_mode; 3476 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3477 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3478 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3479 u32 r; 3480 3481 /* 3482 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3483 * 1 = Long blanking packets are sent in corresponding blanking periods 3484 */ 3485 r = dsi_read_reg(dsidev, DSI_CTRL); 3486 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3487 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3488 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3489 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3490 dsi_write_reg(dsidev, DSI_CTRL, r); 3491 } 3492 3493 /* 3494 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3495 * results in maximum transition time for data and clock lanes to enter and 3496 * exit HS mode. Hence, this is the scenario where the least amount of command 3497 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3498 * clock cycles that can be used to interleave command mode data in HS so that 3499 * all scenarios are satisfied. 3500 */ 3501 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3502 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3503 { 3504 int transition; 3505 3506 /* 3507 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3508 * time of data lanes only, if it isn't set, we need to consider HS 3509 * transition time of both data and clock lanes. HS transition time 3510 * of Scenario 3 is considered. 3511 */ 3512 if (ddr_alwon) { 3513 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3514 } else { 3515 int trans1, trans2; 3516 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3517 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3518 enter_hs + 1; 3519 transition = max(trans1, trans2); 3520 } 3521 3522 return blank > transition ? blank - transition : 0; 3523 } 3524 3525 /* 3526 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3527 * results in maximum transition time for data lanes to enter and exit LP mode. 3528 * Hence, this is the scenario where the least amount of command mode data can 3529 * be interleaved. We program the minimum amount of bytes that can be 3530 * interleaved in LP so that all scenarios are satisfied. 3531 */ 3532 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3533 int lp_clk_div, int tdsi_fclk) 3534 { 3535 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3536 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3537 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3538 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3539 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3540 3541 /* maximum LP transition time according to Scenario 1 */ 3542 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3543 3544 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3545 tlp_avail = thsbyte_clk * (blank - trans_lp); 3546 3547 ttxclkesc = tdsi_fclk * lp_clk_div; 3548 3549 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3550 26) / 16; 3551 3552 return max(lp_inter, 0); 3553 } 3554 3555 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3556 { 3557 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3558 int blanking_mode; 3559 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3560 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3561 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3562 int tclk_trail, ths_exit, exiths_clk; 3563 bool ddr_alwon; 3564 struct videomode *vm = &dsi->vm; 3565 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3566 int ndl = dsi->num_lanes_used - 1; 3567 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3568 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3569 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3570 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3571 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3572 u32 r; 3573 3574 r = dsi_read_reg(dsidev, DSI_CTRL); 3575 blanking_mode = FLD_GET(r, 20, 20); 3576 hfp_blanking_mode = FLD_GET(r, 21, 21); 3577 hbp_blanking_mode = FLD_GET(r, 22, 22); 3578 hsa_blanking_mode = FLD_GET(r, 23, 23); 3579 3580 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3581 hbp = FLD_GET(r, 11, 0); 3582 hfp = FLD_GET(r, 23, 12); 3583 hsa = FLD_GET(r, 31, 24); 3584 3585 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3586 ddr_clk_post = FLD_GET(r, 7, 0); 3587 ddr_clk_pre = FLD_GET(r, 15, 8); 3588 3589 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3590 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3591 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3592 3593 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3594 lp_clk_div = FLD_GET(r, 12, 0); 3595 ddr_alwon = FLD_GET(r, 13, 13); 3596 3597 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3598 ths_exit = FLD_GET(r, 7, 0); 3599 3600 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3601 tclk_trail = FLD_GET(r, 15, 8); 3602 3603 exiths_clk = ths_exit + tclk_trail; 3604 3605 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3606 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3607 3608 if (!hsa_blanking_mode) { 3609 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3610 enter_hs_mode_lat, exit_hs_mode_lat, 3611 exiths_clk, ddr_clk_pre, ddr_clk_post); 3612 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3613 enter_hs_mode_lat, exit_hs_mode_lat, 3614 lp_clk_div, dsi_fclk_hsdiv); 3615 } 3616 3617 if (!hfp_blanking_mode) { 3618 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3619 enter_hs_mode_lat, exit_hs_mode_lat, 3620 exiths_clk, ddr_clk_pre, ddr_clk_post); 3621 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3622 enter_hs_mode_lat, exit_hs_mode_lat, 3623 lp_clk_div, dsi_fclk_hsdiv); 3624 } 3625 3626 if (!hbp_blanking_mode) { 3627 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3628 enter_hs_mode_lat, exit_hs_mode_lat, 3629 exiths_clk, ddr_clk_pre, ddr_clk_post); 3630 3631 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3632 enter_hs_mode_lat, exit_hs_mode_lat, 3633 lp_clk_div, dsi_fclk_hsdiv); 3634 } 3635 3636 if (!blanking_mode) { 3637 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3638 enter_hs_mode_lat, exit_hs_mode_lat, 3639 exiths_clk, ddr_clk_pre, ddr_clk_post); 3640 3641 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3642 enter_hs_mode_lat, exit_hs_mode_lat, 3643 lp_clk_div, dsi_fclk_hsdiv); 3644 } 3645 3646 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3647 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3648 bl_interleave_hs); 3649 3650 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3651 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3652 bl_interleave_lp); 3653 3654 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3655 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3656 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3657 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3658 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3659 3660 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3661 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3662 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3663 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3664 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3665 3666 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3667 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3668 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3669 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3670 } 3671 3672 static int dsi_proto_config(struct platform_device *dsidev) 3673 { 3674 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3675 u32 r; 3676 int buswidth = 0; 3677 3678 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3679 DSI_FIFO_SIZE_32, 3680 DSI_FIFO_SIZE_32, 3681 DSI_FIFO_SIZE_32); 3682 3683 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3684 DSI_FIFO_SIZE_32, 3685 DSI_FIFO_SIZE_32, 3686 DSI_FIFO_SIZE_32); 3687 3688 /* XXX what values for the timeouts? */ 3689 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3690 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3691 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3692 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3693 3694 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3695 case 16: 3696 buswidth = 0; 3697 break; 3698 case 18: 3699 buswidth = 1; 3700 break; 3701 case 24: 3702 buswidth = 2; 3703 break; 3704 default: 3705 BUG(); 3706 return -EINVAL; 3707 } 3708 3709 r = dsi_read_reg(dsidev, DSI_CTRL); 3710 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3711 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3712 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3713 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3714 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3715 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3716 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3717 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3718 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { 3719 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3720 /* DCS_CMD_CODE, 1=start, 0=continue */ 3721 r = FLD_MOD(r, 0, 25, 25); 3722 } 3723 3724 dsi_write_reg(dsidev, DSI_CTRL, r); 3725 3726 dsi_config_vp_num_line_buffers(dsidev); 3727 3728 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3729 dsi_config_vp_sync_events(dsidev); 3730 dsi_config_blanking_modes(dsidev); 3731 dsi_config_cmd_mode_interleaving(dsidev); 3732 } 3733 3734 dsi_vc_initial_config(dsidev, 0); 3735 dsi_vc_initial_config(dsidev, 1); 3736 dsi_vc_initial_config(dsidev, 2); 3737 dsi_vc_initial_config(dsidev, 3); 3738 3739 return 0; 3740 } 3741 3742 static void dsi_proto_timings(struct platform_device *dsidev) 3743 { 3744 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3745 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; 3746 unsigned tclk_pre, tclk_post; 3747 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3748 unsigned ths_trail, ths_exit; 3749 unsigned ddr_clk_pre, ddr_clk_post; 3750 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3751 unsigned ths_eot; 3752 int ndl = dsi->num_lanes_used - 1; 3753 u32 r; 3754 3755 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3756 ths_prepare = FLD_GET(r, 31, 24); 3757 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3758 ths_zero = ths_prepare_ths_zero - ths_prepare; 3759 ths_trail = FLD_GET(r, 15, 8); 3760 ths_exit = FLD_GET(r, 7, 0); 3761 3762 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3763 tlpx = FLD_GET(r, 20, 16) * 2; 3764 tclk_trail = FLD_GET(r, 15, 8); 3765 tclk_zero = FLD_GET(r, 7, 0); 3766 3767 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3768 tclk_prepare = FLD_GET(r, 7, 0); 3769 3770 /* min 8*UI */ 3771 tclk_pre = 20; 3772 /* min 60ns + 52*UI */ 3773 tclk_post = ns2ddr(dsidev, 60) + 26; 3774 3775 ths_eot = DIV_ROUND_UP(4, ndl); 3776 3777 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3778 4); 3779 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3780 3781 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3782 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3783 3784 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3785 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3786 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3787 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3788 3789 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3790 ddr_clk_pre, 3791 ddr_clk_post); 3792 3793 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3794 DIV_ROUND_UP(ths_prepare, 4) + 3795 DIV_ROUND_UP(ths_zero + 3, 4); 3796 3797 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3798 3799 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3800 FLD_VAL(exit_hs_mode_lat, 15, 0); 3801 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3802 3803 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3804 enter_hs_mode_lat, exit_hs_mode_lat); 3805 3806 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3807 /* TODO: Implement a video mode check_timings function */ 3808 int hsa = dsi->vm_timings.hsa; 3809 int hfp = dsi->vm_timings.hfp; 3810 int hbp = dsi->vm_timings.hbp; 3811 int vsa = dsi->vm_timings.vsa; 3812 int vfp = dsi->vm_timings.vfp; 3813 int vbp = dsi->vm_timings.vbp; 3814 int window_sync = dsi->vm_timings.window_sync; 3815 bool hsync_end; 3816 struct videomode *vm = &dsi->vm; 3817 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3818 int tl, t_he, width_bytes; 3819 3820 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3821 t_he = hsync_end ? 3822 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3823 3824 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3825 3826 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3827 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3828 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3829 3830 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3831 hfp, hsync_end ? hsa : 0, tl); 3832 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3833 vsa, vm->vactive); 3834 3835 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3836 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3837 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3838 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3839 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3840 3841 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3842 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3843 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3844 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3845 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3846 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3847 3848 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3849 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 3850 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3851 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3852 } 3853 } 3854 3855 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3856 const struct omap_dsi_pin_config *pin_cfg) 3857 { 3858 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3859 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3860 int num_pins; 3861 const int *pins; 3862 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3863 int num_lanes; 3864 int i; 3865 3866 static const enum dsi_lane_function functions[] = { 3867 DSI_LANE_CLK, 3868 DSI_LANE_DATA1, 3869 DSI_LANE_DATA2, 3870 DSI_LANE_DATA3, 3871 DSI_LANE_DATA4, 3872 }; 3873 3874 num_pins = pin_cfg->num_pins; 3875 pins = pin_cfg->pins; 3876 3877 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3878 || num_pins % 2 != 0) 3879 return -EINVAL; 3880 3881 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3882 lanes[i].function = DSI_LANE_UNUSED; 3883 3884 num_lanes = 0; 3885 3886 for (i = 0; i < num_pins; i += 2) { 3887 u8 lane, pol; 3888 int dx, dy; 3889 3890 dx = pins[i]; 3891 dy = pins[i + 1]; 3892 3893 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3894 return -EINVAL; 3895 3896 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3897 return -EINVAL; 3898 3899 if (dx & 1) { 3900 if (dy != dx - 1) 3901 return -EINVAL; 3902 pol = 1; 3903 } else { 3904 if (dy != dx + 1) 3905 return -EINVAL; 3906 pol = 0; 3907 } 3908 3909 lane = dx / 2; 3910 3911 lanes[lane].function = functions[i / 2]; 3912 lanes[lane].polarity = pol; 3913 num_lanes++; 3914 } 3915 3916 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3917 dsi->num_lanes_used = num_lanes; 3918 3919 return 0; 3920 } 3921 3922 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3923 { 3924 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3925 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3926 enum omap_channel dispc_channel = dssdev->dispc_channel; 3927 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3928 struct omap_dss_device *out = &dsi->output; 3929 u8 data_type; 3930 u16 word_count; 3931 int r; 3932 3933 if (!out->dispc_channel_connected) { 3934 DSSERR("failed to enable display: no output/manager\n"); 3935 return -ENODEV; 3936 } 3937 3938 r = dsi_display_init_dispc(dsidev, dispc_channel); 3939 if (r) 3940 goto err_init_dispc; 3941 3942 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3943 switch (dsi->pix_fmt) { 3944 case OMAP_DSS_DSI_FMT_RGB888: 3945 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3946 break; 3947 case OMAP_DSS_DSI_FMT_RGB666: 3948 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3949 break; 3950 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3951 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3952 break; 3953 case OMAP_DSS_DSI_FMT_RGB565: 3954 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3955 break; 3956 default: 3957 r = -EINVAL; 3958 goto err_pix_fmt; 3959 } 3960 3961 dsi_if_enable(dsidev, false); 3962 dsi_vc_enable(dsidev, channel, false); 3963 3964 /* MODE, 1 = video mode */ 3965 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3966 3967 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3968 3969 dsi_vc_write_long_header(dsidev, channel, data_type, 3970 word_count, 0); 3971 3972 dsi_vc_enable(dsidev, channel, true); 3973 dsi_if_enable(dsidev, true); 3974 } 3975 3976 r = dss_mgr_enable(dispc_channel); 3977 if (r) 3978 goto err_mgr_enable; 3979 3980 return 0; 3981 3982 err_mgr_enable: 3983 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3984 dsi_if_enable(dsidev, false); 3985 dsi_vc_enable(dsidev, channel, false); 3986 } 3987 err_pix_fmt: 3988 dsi_display_uninit_dispc(dsidev, dispc_channel); 3989 err_init_dispc: 3990 return r; 3991 } 3992 3993 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3994 { 3995 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3996 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3997 enum omap_channel dispc_channel = dssdev->dispc_channel; 3998 3999 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 4000 dsi_if_enable(dsidev, false); 4001 dsi_vc_enable(dsidev, channel, false); 4002 4003 /* MODE, 0 = command mode */ 4004 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 4005 4006 dsi_vc_enable(dsidev, channel, true); 4007 dsi_if_enable(dsidev, true); 4008 } 4009 4010 dss_mgr_disable(dispc_channel); 4011 4012 dsi_display_uninit_dispc(dsidev, dispc_channel); 4013 } 4014 4015 static void dsi_update_screen_dispc(struct platform_device *dsidev) 4016 { 4017 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4018 enum omap_channel dispc_channel = dsi->output.dispc_channel; 4019 unsigned bytespp; 4020 unsigned bytespl; 4021 unsigned bytespf; 4022 unsigned total_len; 4023 unsigned packet_payload; 4024 unsigned packet_len; 4025 u32 l; 4026 int r; 4027 const unsigned channel = dsi->update_channel; 4028 const unsigned line_buf_size = dsi->line_buffer_size; 4029 u16 w = dsi->vm.hactive; 4030 u16 h = dsi->vm.vactive; 4031 4032 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 4033 4034 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 4035 4036 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 4037 bytespl = w * bytespp; 4038 bytespf = bytespl * h; 4039 4040 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 4041 * number of lines in a packet. See errata about VP_CLK_RATIO */ 4042 4043 if (bytespf < line_buf_size) 4044 packet_payload = bytespf; 4045 else 4046 packet_payload = (line_buf_size) / bytespl * bytespl; 4047 4048 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 4049 total_len = (bytespf / packet_payload) * packet_len; 4050 4051 if (bytespf % packet_payload) 4052 total_len += (bytespf % packet_payload) + 1; 4053 4054 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 4055 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 4056 4057 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 4058 packet_len, 0); 4059 4060 if (dsi->te_enabled) 4061 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 4062 else 4063 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 4064 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 4065 4066 /* We put SIDLEMODE to no-idle for the duration of the transfer, 4067 * because DSS interrupts are not capable of waking up the CPU and the 4068 * framedone interrupt could be delayed for quite a long time. I think 4069 * the same goes for any DSS interrupts, but for some reason I have not 4070 * seen the problem anywhere else than here. 4071 */ 4072 dispc_disable_sidle(); 4073 4074 dsi_perf_mark_start(dsidev); 4075 4076 r = schedule_delayed_work(&dsi->framedone_timeout_work, 4077 msecs_to_jiffies(250)); 4078 BUG_ON(r == 0); 4079 4080 dss_mgr_set_timings(dispc_channel, &dsi->vm); 4081 4082 dss_mgr_start_update(dispc_channel); 4083 4084 if (dsi->te_enabled) { 4085 /* disable LP_RX_TO, so that we can receive TE. Time to wait 4086 * for TE is longer than the timer allows */ 4087 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 4088 4089 dsi_vc_send_bta(dsidev, channel); 4090 4091 #ifdef DSI_CATCH_MISSING_TE 4092 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 4093 #endif 4094 } 4095 } 4096 4097 #ifdef DSI_CATCH_MISSING_TE 4098 static void dsi_te_timeout(unsigned long arg) 4099 { 4100 DSSERR("TE not received for 250ms!\n"); 4101 } 4102 #endif 4103 4104 static void dsi_handle_framedone(struct platform_device *dsidev, int error) 4105 { 4106 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4107 4108 /* SIDLEMODE back to smart-idle */ 4109 dispc_enable_sidle(); 4110 4111 if (dsi->te_enabled) { 4112 /* enable LP_RX_TO again after the TE */ 4113 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 4114 } 4115 4116 dsi->framedone_callback(error, dsi->framedone_data); 4117 4118 if (!error) 4119 dsi_perf_show(dsidev, "DISPC"); 4120 } 4121 4122 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4123 { 4124 struct dsi_data *dsi = container_of(work, struct dsi_data, 4125 framedone_timeout_work.work); 4126 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 4127 * 250ms which would conflict with this timeout work. What should be 4128 * done is first cancel the transfer on the HW, and then cancel the 4129 * possibly scheduled framedone work. However, cancelling the transfer 4130 * on the HW is buggy, and would probably require resetting the whole 4131 * DSI */ 4132 4133 DSSERR("Framedone not received for 250ms!\n"); 4134 4135 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4136 } 4137 4138 static void dsi_framedone_irq_callback(void *data) 4139 { 4140 struct platform_device *dsidev = (struct platform_device *) data; 4141 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4142 4143 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4144 * turns itself off. However, DSI still has the pixels in its buffers, 4145 * and is sending the data. 4146 */ 4147 4148 cancel_delayed_work(&dsi->framedone_timeout_work); 4149 4150 dsi_handle_framedone(dsidev, 0); 4151 } 4152 4153 static int dsi_update(struct omap_dss_device *dssdev, int channel, 4154 void (*callback)(int, void *), void *data) 4155 { 4156 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4158 u16 dw, dh; 4159 4160 dsi_perf_mark_setup(dsidev); 4161 4162 dsi->update_channel = channel; 4163 4164 dsi->framedone_callback = callback; 4165 dsi->framedone_data = data; 4166 4167 dw = dsi->vm.hactive; 4168 dh = dsi->vm.vactive; 4169 4170 #ifdef DSI_PERF_MEASURE 4171 dsi->update_bytes = dw * dh * 4172 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4173 #endif 4174 dsi_update_screen_dispc(dsidev); 4175 4176 return 0; 4177 } 4178 4179 /* Display funcs */ 4180 4181 static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4182 { 4183 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4184 struct dispc_clock_info dispc_cinfo; 4185 int r; 4186 unsigned long fck; 4187 4188 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4189 4190 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4191 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4192 4193 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4194 if (r) { 4195 DSSERR("Failed to calc dispc clocks\n"); 4196 return r; 4197 } 4198 4199 dsi->mgr_config.clock_info = dispc_cinfo; 4200 4201 return 0; 4202 } 4203 4204 static int dsi_display_init_dispc(struct platform_device *dsidev, 4205 enum omap_channel channel) 4206 { 4207 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4208 int r; 4209 4210 dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? 4211 DSS_CLK_SRC_PLL1_1 : 4212 DSS_CLK_SRC_PLL2_1); 4213 4214 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4215 r = dss_mgr_register_framedone_handler(channel, 4216 dsi_framedone_irq_callback, dsidev); 4217 if (r) { 4218 DSSERR("can't register FRAMEDONE handler\n"); 4219 goto err; 4220 } 4221 4222 dsi->mgr_config.stallmode = true; 4223 dsi->mgr_config.fifohandcheck = true; 4224 } else { 4225 dsi->mgr_config.stallmode = false; 4226 dsi->mgr_config.fifohandcheck = false; 4227 } 4228 4229 /* 4230 * override interlace, logic level and edge related parameters in 4231 * videomode with default values 4232 */ 4233 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4234 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4235 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4236 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4237 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4238 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4239 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4240 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4241 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4242 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4243 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4244 4245 dss_mgr_set_timings(channel, &dsi->vm); 4246 4247 r = dsi_configure_dispc_clocks(dsidev); 4248 if (r) 4249 goto err1; 4250 4251 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4252 dsi->mgr_config.video_port_width = 4253 dsi_get_pixel_size(dsi->pix_fmt); 4254 dsi->mgr_config.lcden_sig_polarity = 0; 4255 4256 dss_mgr_set_lcd_config(channel, &dsi->mgr_config); 4257 4258 return 0; 4259 err1: 4260 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4261 dss_mgr_unregister_framedone_handler(channel, 4262 dsi_framedone_irq_callback, dsidev); 4263 err: 4264 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4265 return r; 4266 } 4267 4268 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4269 enum omap_channel channel) 4270 { 4271 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4272 4273 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4274 dss_mgr_unregister_framedone_handler(channel, 4275 dsi_framedone_irq_callback, dsidev); 4276 4277 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4278 } 4279 4280 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4281 { 4282 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4283 struct dss_pll_clock_info cinfo; 4284 int r; 4285 4286 cinfo = dsi->user_dsi_cinfo; 4287 4288 r = dss_pll_set_config(&dsi->pll, &cinfo); 4289 if (r) { 4290 DSSERR("Failed to set dsi clocks\n"); 4291 return r; 4292 } 4293 4294 return 0; 4295 } 4296 4297 static int dsi_display_init_dsi(struct platform_device *dsidev) 4298 { 4299 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4300 int r; 4301 4302 r = dss_pll_enable(&dsi->pll); 4303 if (r) 4304 goto err0; 4305 4306 r = dsi_configure_dsi_clocks(dsidev); 4307 if (r) 4308 goto err1; 4309 4310 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4311 DSS_CLK_SRC_PLL1_2 : 4312 DSS_CLK_SRC_PLL2_2); 4313 4314 DSSDBG("PLL OK\n"); 4315 4316 r = dsi_cio_init(dsidev); 4317 if (r) 4318 goto err2; 4319 4320 _dsi_print_reset_status(dsidev); 4321 4322 dsi_proto_timings(dsidev); 4323 dsi_set_lp_clk_divisor(dsidev); 4324 4325 if (1) 4326 _dsi_print_reset_status(dsidev); 4327 4328 r = dsi_proto_config(dsidev); 4329 if (r) 4330 goto err3; 4331 4332 /* enable interface */ 4333 dsi_vc_enable(dsidev, 0, 1); 4334 dsi_vc_enable(dsidev, 1, 1); 4335 dsi_vc_enable(dsidev, 2, 1); 4336 dsi_vc_enable(dsidev, 3, 1); 4337 dsi_if_enable(dsidev, 1); 4338 dsi_force_tx_stop_mode_io(dsidev); 4339 4340 return 0; 4341 err3: 4342 dsi_cio_uninit(dsidev); 4343 err2: 4344 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4345 err1: 4346 dss_pll_disable(&dsi->pll); 4347 err0: 4348 return r; 4349 } 4350 4351 static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4352 bool disconnect_lanes, bool enter_ulps) 4353 { 4354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4355 4356 if (enter_ulps && !dsi->ulps_enabled) 4357 dsi_enter_ulps(dsidev); 4358 4359 /* disable interface */ 4360 dsi_if_enable(dsidev, 0); 4361 dsi_vc_enable(dsidev, 0, 0); 4362 dsi_vc_enable(dsidev, 1, 0); 4363 dsi_vc_enable(dsidev, 2, 0); 4364 dsi_vc_enable(dsidev, 3, 0); 4365 4366 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4367 dsi_cio_uninit(dsidev); 4368 dsi_pll_uninit(dsidev, disconnect_lanes); 4369 } 4370 4371 static int dsi_display_enable(struct omap_dss_device *dssdev) 4372 { 4373 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4374 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4375 int r = 0; 4376 4377 DSSDBG("dsi_display_enable\n"); 4378 4379 WARN_ON(!dsi_bus_is_locked(dsidev)); 4380 4381 mutex_lock(&dsi->lock); 4382 4383 r = dsi_runtime_get(dsidev); 4384 if (r) 4385 goto err_get_dsi; 4386 4387 _dsi_initialize_irq(dsidev); 4388 4389 r = dsi_display_init_dsi(dsidev); 4390 if (r) 4391 goto err_init_dsi; 4392 4393 mutex_unlock(&dsi->lock); 4394 4395 return 0; 4396 4397 err_init_dsi: 4398 dsi_runtime_put(dsidev); 4399 err_get_dsi: 4400 mutex_unlock(&dsi->lock); 4401 DSSDBG("dsi_display_enable FAILED\n"); 4402 return r; 4403 } 4404 4405 static void dsi_display_disable(struct omap_dss_device *dssdev, 4406 bool disconnect_lanes, bool enter_ulps) 4407 { 4408 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4409 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4410 4411 DSSDBG("dsi_display_disable\n"); 4412 4413 WARN_ON(!dsi_bus_is_locked(dsidev)); 4414 4415 mutex_lock(&dsi->lock); 4416 4417 dsi_sync_vc(dsidev, 0); 4418 dsi_sync_vc(dsidev, 1); 4419 dsi_sync_vc(dsidev, 2); 4420 dsi_sync_vc(dsidev, 3); 4421 4422 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4423 4424 dsi_runtime_put(dsidev); 4425 4426 mutex_unlock(&dsi->lock); 4427 } 4428 4429 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4430 { 4431 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4432 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4433 4434 dsi->te_enabled = enable; 4435 return 0; 4436 } 4437 4438 #ifdef PRINT_VERBOSE_VM_TIMINGS 4439 static void print_dsi_vm(const char *str, 4440 const struct omap_dss_dsi_videomode_timings *t) 4441 { 4442 unsigned long byteclk = t->hsclk / 4; 4443 int bl, wc, pps, tot; 4444 4445 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4446 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4447 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4448 tot = bl + pps; 4449 4450 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4451 4452 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4453 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4454 str, 4455 byteclk, 4456 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4457 bl, pps, tot, 4458 TO_DSI_T(t->hss), 4459 TO_DSI_T(t->hsa), 4460 TO_DSI_T(t->hse), 4461 TO_DSI_T(t->hbp), 4462 TO_DSI_T(pps), 4463 TO_DSI_T(t->hfp), 4464 4465 TO_DSI_T(bl), 4466 TO_DSI_T(pps), 4467 4468 TO_DSI_T(tot)); 4469 #undef TO_DSI_T 4470 } 4471 4472 static void print_dispc_vm(const char *str, const struct videomode *vm) 4473 { 4474 unsigned long pck = vm->pixelclock; 4475 int hact, bl, tot; 4476 4477 hact = vm->hactive; 4478 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 4479 tot = hact + bl; 4480 4481 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4482 4483 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4484 "%u/%u/%u/%u = %u + %u = %u\n", 4485 str, 4486 pck, 4487 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 4488 bl, hact, tot, 4489 TO_DISPC_T(vm->hsync_len), 4490 TO_DISPC_T(vm->hback_porch), 4491 TO_DISPC_T(hact), 4492 TO_DISPC_T(vm->hfront_porch), 4493 TO_DISPC_T(bl), 4494 TO_DISPC_T(hact), 4495 TO_DISPC_T(tot)); 4496 #undef TO_DISPC_T 4497 } 4498 4499 /* note: this is not quite accurate */ 4500 static void print_dsi_dispc_vm(const char *str, 4501 const struct omap_dss_dsi_videomode_timings *t) 4502 { 4503 struct videomode vm = { 0 }; 4504 unsigned long byteclk = t->hsclk / 4; 4505 unsigned long pck; 4506 u64 dsi_tput; 4507 int dsi_hact, dsi_htot; 4508 4509 dsi_tput = (u64)byteclk * t->ndl * 8; 4510 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4511 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4512 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4513 4514 vm.pixelclock = pck; 4515 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4516 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 4517 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 4518 vm.hactive = t->hact; 4519 4520 print_dispc_vm(str, &vm); 4521 } 4522 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4523 4524 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4525 unsigned long pck, void *data) 4526 { 4527 struct dsi_clk_calc_ctx *ctx = data; 4528 struct videomode *vm = &ctx->vm; 4529 4530 ctx->dispc_cinfo.lck_div = lckd; 4531 ctx->dispc_cinfo.pck_div = pckd; 4532 ctx->dispc_cinfo.lck = lck; 4533 ctx->dispc_cinfo.pck = pck; 4534 4535 *vm = *ctx->config->vm; 4536 vm->pixelclock = pck; 4537 vm->hactive = ctx->config->vm->hactive; 4538 vm->vactive = ctx->config->vm->vactive; 4539 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 4540 vm->vfront_porch = vm->vback_porch = 0; 4541 4542 return true; 4543 } 4544 4545 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4546 void *data) 4547 { 4548 struct dsi_clk_calc_ctx *ctx = data; 4549 4550 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4551 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4552 4553 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4554 dsi_cm_calc_dispc_cb, ctx); 4555 } 4556 4557 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4558 unsigned long clkdco, void *data) 4559 { 4560 struct dsi_clk_calc_ctx *ctx = data; 4561 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4562 4563 ctx->dsi_cinfo.n = n; 4564 ctx->dsi_cinfo.m = m; 4565 ctx->dsi_cinfo.fint = fint; 4566 ctx->dsi_cinfo.clkdco = clkdco; 4567 4568 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4569 dsi->data->max_fck_freq, 4570 dsi_cm_calc_hsdiv_cb, ctx); 4571 } 4572 4573 static bool dsi_cm_calc(struct dsi_data *dsi, 4574 const struct omap_dss_dsi_config *cfg, 4575 struct dsi_clk_calc_ctx *ctx) 4576 { 4577 unsigned long clkin; 4578 int bitspp, ndl; 4579 unsigned long pll_min, pll_max; 4580 unsigned long pck, txbyteclk; 4581 4582 clkin = clk_get_rate(dsi->pll.clkin); 4583 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4584 ndl = dsi->num_lanes_used - 1; 4585 4586 /* 4587 * Here we should calculate minimum txbyteclk to be able to send the 4588 * frame in time, and also to handle TE. That's not very simple, though, 4589 * especially as we go to LP between each pixel packet due to HW 4590 * "feature". So let's just estimate very roughly and multiply by 1.5. 4591 */ 4592 pck = cfg->vm->pixelclock; 4593 pck = pck * 3 / 2; 4594 txbyteclk = pck * bitspp / 8 / ndl; 4595 4596 memset(ctx, 0, sizeof(*ctx)); 4597 ctx->dsidev = dsi->pdev; 4598 ctx->pll = &dsi->pll; 4599 ctx->config = cfg; 4600 ctx->req_pck_min = pck; 4601 ctx->req_pck_nom = pck; 4602 ctx->req_pck_max = pck * 3 / 2; 4603 4604 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4605 pll_max = cfg->hs_clk_max * 4; 4606 4607 return dss_pll_calc_a(ctx->pll, clkin, 4608 pll_min, pll_max, 4609 dsi_cm_calc_pll_cb, ctx); 4610 } 4611 4612 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4613 { 4614 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4615 const struct omap_dss_dsi_config *cfg = ctx->config; 4616 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4617 int ndl = dsi->num_lanes_used - 1; 4618 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4619 unsigned long byteclk = hsclk / 4; 4620 4621 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4622 int xres; 4623 int panel_htot, panel_hbl; /* pixels */ 4624 int dispc_htot, dispc_hbl; /* pixels */ 4625 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4626 int hfp, hsa, hbp; 4627 const struct videomode *req_vm; 4628 struct videomode *dispc_vm; 4629 struct omap_dss_dsi_videomode_timings *dsi_vm; 4630 u64 dsi_tput, dispc_tput; 4631 4632 dsi_tput = (u64)byteclk * ndl * 8; 4633 4634 req_vm = cfg->vm; 4635 req_pck_min = ctx->req_pck_min; 4636 req_pck_max = ctx->req_pck_max; 4637 req_pck_nom = ctx->req_pck_nom; 4638 4639 dispc_pck = ctx->dispc_cinfo.pck; 4640 dispc_tput = (u64)dispc_pck * bitspp; 4641 4642 xres = req_vm->hactive; 4643 4644 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 4645 req_vm->hsync_len; 4646 panel_htot = xres + panel_hbl; 4647 4648 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4649 4650 /* 4651 * When there are no line buffers, DISPC and DSI must have the 4652 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4653 */ 4654 if (dsi->line_buffer_size < xres * bitspp / 8) { 4655 if (dispc_tput != dsi_tput) 4656 return false; 4657 } else { 4658 if (dispc_tput < dsi_tput) 4659 return false; 4660 } 4661 4662 /* DSI tput must be over the min requirement */ 4663 if (dsi_tput < (u64)bitspp * req_pck_min) 4664 return false; 4665 4666 /* When non-burst mode, DSI tput must be below max requirement. */ 4667 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4668 if (dsi_tput > (u64)bitspp * req_pck_max) 4669 return false; 4670 } 4671 4672 hss = DIV_ROUND_UP(4, ndl); 4673 4674 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4675 if (ndl == 3 && req_vm->hsync_len == 0) 4676 hse = 1; 4677 else 4678 hse = DIV_ROUND_UP(4, ndl); 4679 } else { 4680 hse = 0; 4681 } 4682 4683 /* DSI htot to match the panel's nominal pck */ 4684 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4685 4686 /* fail if there would be no time for blanking */ 4687 if (dsi_htot < hss + hse + dsi_hact) 4688 return false; 4689 4690 /* total DSI blanking needed to achieve panel's TL */ 4691 dsi_hbl = dsi_htot - dsi_hact; 4692 4693 /* DISPC htot to match the DSI TL */ 4694 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4695 4696 /* verify that the DSI and DISPC TLs are the same */ 4697 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4698 return false; 4699 4700 dispc_hbl = dispc_htot - xres; 4701 4702 /* setup DSI videomode */ 4703 4704 dsi_vm = &ctx->dsi_vm; 4705 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4706 4707 dsi_vm->hsclk = hsclk; 4708 4709 dsi_vm->ndl = ndl; 4710 dsi_vm->bitspp = bitspp; 4711 4712 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4713 hsa = 0; 4714 } else if (ndl == 3 && req_vm->hsync_len == 0) { 4715 hsa = 0; 4716 } else { 4717 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 4718 hsa = max(hsa - hse, 1); 4719 } 4720 4721 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 4722 hbp = max(hbp, 1); 4723 4724 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4725 if (hfp < 1) { 4726 int t; 4727 /* we need to take cycles from hbp */ 4728 4729 t = 1 - hfp; 4730 hbp = max(hbp - t, 1); 4731 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4732 4733 if (hfp < 1 && hsa > 0) { 4734 /* we need to take cycles from hsa */ 4735 t = 1 - hfp; 4736 hsa = max(hsa - t, 1); 4737 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4738 } 4739 } 4740 4741 if (hfp < 1) 4742 return false; 4743 4744 dsi_vm->hss = hss; 4745 dsi_vm->hsa = hsa; 4746 dsi_vm->hse = hse; 4747 dsi_vm->hbp = hbp; 4748 dsi_vm->hact = xres; 4749 dsi_vm->hfp = hfp; 4750 4751 dsi_vm->vsa = req_vm->vsync_len; 4752 dsi_vm->vbp = req_vm->vback_porch; 4753 dsi_vm->vact = req_vm->vactive; 4754 dsi_vm->vfp = req_vm->vfront_porch; 4755 4756 dsi_vm->trans_mode = cfg->trans_mode; 4757 4758 dsi_vm->blanking_mode = 0; 4759 dsi_vm->hsa_blanking_mode = 1; 4760 dsi_vm->hfp_blanking_mode = 1; 4761 dsi_vm->hbp_blanking_mode = 1; 4762 4763 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4764 dsi_vm->window_sync = 4; 4765 4766 /* setup DISPC videomode */ 4767 4768 dispc_vm = &ctx->vm; 4769 *dispc_vm = *req_vm; 4770 dispc_vm->pixelclock = dispc_pck; 4771 4772 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4773 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 4774 req_pck_nom); 4775 hsa = max(hsa, 1); 4776 } else { 4777 hsa = 1; 4778 } 4779 4780 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 4781 hbp = max(hbp, 1); 4782 4783 hfp = dispc_hbl - hsa - hbp; 4784 if (hfp < 1) { 4785 int t; 4786 /* we need to take cycles from hbp */ 4787 4788 t = 1 - hfp; 4789 hbp = max(hbp - t, 1); 4790 hfp = dispc_hbl - hsa - hbp; 4791 4792 if (hfp < 1) { 4793 /* we need to take cycles from hsa */ 4794 t = 1 - hfp; 4795 hsa = max(hsa - t, 1); 4796 hfp = dispc_hbl - hsa - hbp; 4797 } 4798 } 4799 4800 if (hfp < 1) 4801 return false; 4802 4803 dispc_vm->hfront_porch = hfp; 4804 dispc_vm->hsync_len = hsa; 4805 dispc_vm->hback_porch = hbp; 4806 4807 return true; 4808 } 4809 4810 4811 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4812 unsigned long pck, void *data) 4813 { 4814 struct dsi_clk_calc_ctx *ctx = data; 4815 4816 ctx->dispc_cinfo.lck_div = lckd; 4817 ctx->dispc_cinfo.pck_div = pckd; 4818 ctx->dispc_cinfo.lck = lck; 4819 ctx->dispc_cinfo.pck = pck; 4820 4821 if (dsi_vm_calc_blanking(ctx) == false) 4822 return false; 4823 4824 #ifdef PRINT_VERBOSE_VM_TIMINGS 4825 print_dispc_vm("dispc", &ctx->vm); 4826 print_dsi_vm("dsi ", &ctx->dsi_vm); 4827 print_dispc_vm("req ", ctx->config->vm); 4828 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4829 #endif 4830 4831 return true; 4832 } 4833 4834 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4835 void *data) 4836 { 4837 struct dsi_clk_calc_ctx *ctx = data; 4838 unsigned long pck_max; 4839 4840 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4841 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4842 4843 /* 4844 * In burst mode we can let the dispc pck be arbitrarily high, but it 4845 * limits our scaling abilities. So for now, don't aim too high. 4846 */ 4847 4848 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4849 pck_max = ctx->req_pck_max + 10000000; 4850 else 4851 pck_max = ctx->req_pck_max; 4852 4853 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4854 dsi_vm_calc_dispc_cb, ctx); 4855 } 4856 4857 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4858 unsigned long clkdco, void *data) 4859 { 4860 struct dsi_clk_calc_ctx *ctx = data; 4861 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4862 4863 ctx->dsi_cinfo.n = n; 4864 ctx->dsi_cinfo.m = m; 4865 ctx->dsi_cinfo.fint = fint; 4866 ctx->dsi_cinfo.clkdco = clkdco; 4867 4868 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4869 dsi->data->max_fck_freq, 4870 dsi_vm_calc_hsdiv_cb, ctx); 4871 } 4872 4873 static bool dsi_vm_calc(struct dsi_data *dsi, 4874 const struct omap_dss_dsi_config *cfg, 4875 struct dsi_clk_calc_ctx *ctx) 4876 { 4877 const struct videomode *vm = cfg->vm; 4878 unsigned long clkin; 4879 unsigned long pll_min; 4880 unsigned long pll_max; 4881 int ndl = dsi->num_lanes_used - 1; 4882 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4883 unsigned long byteclk_min; 4884 4885 clkin = clk_get_rate(dsi->pll.clkin); 4886 4887 memset(ctx, 0, sizeof(*ctx)); 4888 ctx->dsidev = dsi->pdev; 4889 ctx->pll = &dsi->pll; 4890 ctx->config = cfg; 4891 4892 /* these limits should come from the panel driver */ 4893 ctx->req_pck_min = vm->pixelclock - 1000; 4894 ctx->req_pck_nom = vm->pixelclock; 4895 ctx->req_pck_max = vm->pixelclock + 1000; 4896 4897 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4898 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4899 4900 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4901 pll_max = cfg->hs_clk_max * 4; 4902 } else { 4903 unsigned long byteclk_max; 4904 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4905 ndl * 8); 4906 4907 pll_max = byteclk_max * 4 * 4; 4908 } 4909 4910 return dss_pll_calc_a(ctx->pll, clkin, 4911 pll_min, pll_max, 4912 dsi_vm_calc_pll_cb, ctx); 4913 } 4914 4915 static int dsi_set_config(struct omap_dss_device *dssdev, 4916 const struct omap_dss_dsi_config *config) 4917 { 4918 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4919 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4920 struct dsi_clk_calc_ctx ctx; 4921 bool ok; 4922 int r; 4923 4924 mutex_lock(&dsi->lock); 4925 4926 dsi->pix_fmt = config->pixel_format; 4927 dsi->mode = config->mode; 4928 4929 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4930 ok = dsi_vm_calc(dsi, config, &ctx); 4931 else 4932 ok = dsi_cm_calc(dsi, config, &ctx); 4933 4934 if (!ok) { 4935 DSSERR("failed to find suitable DSI clock settings\n"); 4936 r = -EINVAL; 4937 goto err; 4938 } 4939 4940 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo); 4941 4942 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4943 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4944 if (r) { 4945 DSSERR("failed to find suitable DSI LP clock settings\n"); 4946 goto err; 4947 } 4948 4949 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4950 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4951 4952 dsi->vm = ctx.vm; 4953 dsi->vm_timings = ctx.dsi_vm; 4954 4955 mutex_unlock(&dsi->lock); 4956 4957 return 0; 4958 err: 4959 mutex_unlock(&dsi->lock); 4960 4961 return r; 4962 } 4963 4964 /* 4965 * Return a hardcoded channel for the DSI output. This should work for 4966 * current use cases, but this can be later expanded to either resolve 4967 * the channel in some more dynamic manner, or get the channel as a user 4968 * parameter. 4969 */ 4970 static enum omap_channel dsi_get_channel(struct dsi_data *dsi) 4971 { 4972 switch (dsi->data->model) { 4973 case DSI_MODEL_OMAP3: 4974 return OMAP_DSS_CHANNEL_LCD; 4975 4976 case DSI_MODEL_OMAP4: 4977 switch (dsi->module_id) { 4978 case 0: 4979 return OMAP_DSS_CHANNEL_LCD; 4980 case 1: 4981 return OMAP_DSS_CHANNEL_LCD2; 4982 default: 4983 DSSWARN("unsupported module id\n"); 4984 return OMAP_DSS_CHANNEL_LCD; 4985 } 4986 4987 case DSI_MODEL_OMAP5: 4988 switch (dsi->module_id) { 4989 case 0: 4990 return OMAP_DSS_CHANNEL_LCD; 4991 case 1: 4992 return OMAP_DSS_CHANNEL_LCD3; 4993 default: 4994 DSSWARN("unsupported module id\n"); 4995 return OMAP_DSS_CHANNEL_LCD; 4996 } 4997 4998 default: 4999 DSSWARN("unsupported DSS version\n"); 5000 return OMAP_DSS_CHANNEL_LCD; 5001 } 5002 } 5003 5004 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 5005 { 5006 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 5007 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5008 int i; 5009 5010 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5011 if (!dsi->vc[i].dssdev) { 5012 dsi->vc[i].dssdev = dssdev; 5013 *channel = i; 5014 return 0; 5015 } 5016 } 5017 5018 DSSERR("cannot get VC for display %s", dssdev->name); 5019 return -ENOSPC; 5020 } 5021 5022 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 5023 { 5024 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 5025 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5026 5027 if (vc_id < 0 || vc_id > 3) { 5028 DSSERR("VC ID out of range\n"); 5029 return -EINVAL; 5030 } 5031 5032 if (channel < 0 || channel > 3) { 5033 DSSERR("Virtual Channel out of range\n"); 5034 return -EINVAL; 5035 } 5036 5037 if (dsi->vc[channel].dssdev != dssdev) { 5038 DSSERR("Virtual Channel not allocated to display %s\n", 5039 dssdev->name); 5040 return -EINVAL; 5041 } 5042 5043 dsi->vc[channel].vc_id = vc_id; 5044 5045 return 0; 5046 } 5047 5048 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 5049 { 5050 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 5051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5052 5053 if ((channel >= 0 && channel <= 3) && 5054 dsi->vc[channel].dssdev == dssdev) { 5055 dsi->vc[channel].dssdev = NULL; 5056 dsi->vc[channel].vc_id = 0; 5057 } 5058 } 5059 5060 5061 static int dsi_get_clocks(struct platform_device *dsidev) 5062 { 5063 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5064 struct clk *clk; 5065 5066 clk = devm_clk_get(&dsidev->dev, "fck"); 5067 if (IS_ERR(clk)) { 5068 DSSERR("can't get fck\n"); 5069 return PTR_ERR(clk); 5070 } 5071 5072 dsi->dss_clk = clk; 5073 5074 return 0; 5075 } 5076 5077 static int dsi_connect(struct omap_dss_device *dssdev, 5078 struct omap_dss_device *dst) 5079 { 5080 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 5081 enum omap_channel dispc_channel = dssdev->dispc_channel; 5082 int r; 5083 5084 r = dsi_regulator_init(dsidev); 5085 if (r) 5086 return r; 5087 5088 r = dss_mgr_connect(dispc_channel, dssdev); 5089 if (r) 5090 return r; 5091 5092 r = omapdss_output_set_device(dssdev, dst); 5093 if (r) { 5094 DSSERR("failed to connect output to new device: %s\n", 5095 dssdev->name); 5096 dss_mgr_disconnect(dispc_channel, dssdev); 5097 return r; 5098 } 5099 5100 return 0; 5101 } 5102 5103 static void dsi_disconnect(struct omap_dss_device *dssdev, 5104 struct omap_dss_device *dst) 5105 { 5106 enum omap_channel dispc_channel = dssdev->dispc_channel; 5107 5108 WARN_ON(dst != dssdev->dst); 5109 5110 if (dst != dssdev->dst) 5111 return; 5112 5113 omapdss_output_unset_device(dssdev); 5114 5115 dss_mgr_disconnect(dispc_channel, dssdev); 5116 } 5117 5118 static const struct omapdss_dsi_ops dsi_ops = { 5119 .connect = dsi_connect, 5120 .disconnect = dsi_disconnect, 5121 5122 .bus_lock = dsi_bus_lock, 5123 .bus_unlock = dsi_bus_unlock, 5124 5125 .enable = dsi_display_enable, 5126 .disable = dsi_display_disable, 5127 5128 .enable_hs = dsi_vc_enable_hs, 5129 5130 .configure_pins = dsi_configure_pins, 5131 .set_config = dsi_set_config, 5132 5133 .enable_video_output = dsi_enable_video_output, 5134 .disable_video_output = dsi_disable_video_output, 5135 5136 .update = dsi_update, 5137 5138 .enable_te = dsi_enable_te, 5139 5140 .request_vc = dsi_request_vc, 5141 .set_vc_id = dsi_set_vc_id, 5142 .release_vc = dsi_release_vc, 5143 5144 .dcs_write = dsi_vc_dcs_write, 5145 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 5146 .dcs_read = dsi_vc_dcs_read, 5147 5148 .gen_write = dsi_vc_generic_write, 5149 .gen_write_nosync = dsi_vc_generic_write_nosync, 5150 .gen_read = dsi_vc_generic_read, 5151 5152 .bta_sync = dsi_vc_send_bta_sync, 5153 5154 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5155 }; 5156 5157 static void dsi_init_output(struct platform_device *dsidev) 5158 { 5159 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5160 struct omap_dss_device *out = &dsi->output; 5161 5162 out->dev = &dsidev->dev; 5163 out->id = dsi->module_id == 0 ? 5164 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5165 5166 out->output_type = OMAP_DISPLAY_TYPE_DSI; 5167 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5168 out->dispc_channel = dsi_get_channel(dsi); 5169 out->ops.dsi = &dsi_ops; 5170 out->owner = THIS_MODULE; 5171 5172 omapdss_register_output(out); 5173 } 5174 5175 static void dsi_uninit_output(struct platform_device *dsidev) 5176 { 5177 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5178 struct omap_dss_device *out = &dsi->output; 5179 5180 omapdss_unregister_output(out); 5181 } 5182 5183 static int dsi_probe_of(struct platform_device *pdev) 5184 { 5185 struct device_node *node = pdev->dev.of_node; 5186 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5187 struct property *prop; 5188 u32 lane_arr[10]; 5189 int len, num_pins; 5190 int r, i; 5191 struct device_node *ep; 5192 struct omap_dsi_pin_config pin_cfg; 5193 5194 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 5195 if (!ep) 5196 return 0; 5197 5198 prop = of_find_property(ep, "lanes", &len); 5199 if (prop == NULL) { 5200 dev_err(&pdev->dev, "failed to find lane data\n"); 5201 r = -EINVAL; 5202 goto err; 5203 } 5204 5205 num_pins = len / sizeof(u32); 5206 5207 if (num_pins < 4 || num_pins % 2 != 0 || 5208 num_pins > dsi->num_lanes_supported * 2) { 5209 dev_err(&pdev->dev, "bad number of lanes\n"); 5210 r = -EINVAL; 5211 goto err; 5212 } 5213 5214 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5215 if (r) { 5216 dev_err(&pdev->dev, "failed to read lane data\n"); 5217 goto err; 5218 } 5219 5220 pin_cfg.num_pins = num_pins; 5221 for (i = 0; i < num_pins; ++i) 5222 pin_cfg.pins[i] = (int)lane_arr[i]; 5223 5224 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5225 if (r) { 5226 dev_err(&pdev->dev, "failed to configure pins"); 5227 goto err; 5228 } 5229 5230 of_node_put(ep); 5231 5232 return 0; 5233 5234 err: 5235 of_node_put(ep); 5236 return r; 5237 } 5238 5239 static const struct dss_pll_ops dsi_pll_ops = { 5240 .enable = dsi_pll_enable, 5241 .disable = dsi_pll_disable, 5242 .set_config = dss_pll_write_config_type_a, 5243 }; 5244 5245 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5246 .type = DSS_PLL_TYPE_A, 5247 5248 .n_max = (1 << 7) - 1, 5249 .m_max = (1 << 11) - 1, 5250 .mX_max = (1 << 4) - 1, 5251 .fint_min = 750000, 5252 .fint_max = 2100000, 5253 .clkdco_low = 1000000000, 5254 .clkdco_max = 1800000000, 5255 5256 .n_msb = 7, 5257 .n_lsb = 1, 5258 .m_msb = 18, 5259 .m_lsb = 8, 5260 5261 .mX_msb[0] = 22, 5262 .mX_lsb[0] = 19, 5263 .mX_msb[1] = 26, 5264 .mX_lsb[1] = 23, 5265 5266 .has_stopmode = true, 5267 .has_freqsel = true, 5268 .has_selfreqdco = false, 5269 .has_refsel = false, 5270 }; 5271 5272 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5273 .type = DSS_PLL_TYPE_A, 5274 5275 .n_max = (1 << 8) - 1, 5276 .m_max = (1 << 12) - 1, 5277 .mX_max = (1 << 5) - 1, 5278 .fint_min = 500000, 5279 .fint_max = 2500000, 5280 .clkdco_low = 1000000000, 5281 .clkdco_max = 1800000000, 5282 5283 .n_msb = 8, 5284 .n_lsb = 1, 5285 .m_msb = 20, 5286 .m_lsb = 9, 5287 5288 .mX_msb[0] = 25, 5289 .mX_lsb[0] = 21, 5290 .mX_msb[1] = 30, 5291 .mX_lsb[1] = 26, 5292 5293 .has_stopmode = true, 5294 .has_freqsel = false, 5295 .has_selfreqdco = false, 5296 .has_refsel = false, 5297 }; 5298 5299 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5300 .type = DSS_PLL_TYPE_A, 5301 5302 .n_max = (1 << 8) - 1, 5303 .m_max = (1 << 12) - 1, 5304 .mX_max = (1 << 5) - 1, 5305 .fint_min = 150000, 5306 .fint_max = 52000000, 5307 .clkdco_low = 1000000000, 5308 .clkdco_max = 1800000000, 5309 5310 .n_msb = 8, 5311 .n_lsb = 1, 5312 .m_msb = 20, 5313 .m_lsb = 9, 5314 5315 .mX_msb[0] = 25, 5316 .mX_lsb[0] = 21, 5317 .mX_msb[1] = 30, 5318 .mX_lsb[1] = 26, 5319 5320 .has_stopmode = true, 5321 .has_freqsel = false, 5322 .has_selfreqdco = true, 5323 .has_refsel = true, 5324 }; 5325 5326 static int dsi_init_pll_data(struct platform_device *dsidev) 5327 { 5328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5329 struct dss_pll *pll = &dsi->pll; 5330 struct clk *clk; 5331 int r; 5332 5333 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5334 if (IS_ERR(clk)) { 5335 DSSERR("can't get sys_clk\n"); 5336 return PTR_ERR(clk); 5337 } 5338 5339 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5340 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5341 pll->clkin = clk; 5342 pll->base = dsi->pll_base; 5343 pll->hw = dsi->data->pll_hw; 5344 pll->ops = &dsi_pll_ops; 5345 5346 r = dss_pll_register(pll); 5347 if (r) 5348 return r; 5349 5350 return 0; 5351 } 5352 5353 /* DSI1 HW IP initialisation */ 5354 static const struct dsi_of_data dsi_of_data_omap34xx = { 5355 .model = DSI_MODEL_OMAP3, 5356 .pll_hw = &dss_omap3_dsi_pll_hw, 5357 .modules = (const struct dsi_module_id_data[]) { 5358 { .address = 0x4804fc00, .id = 0, }, 5359 { }, 5360 }, 5361 .max_fck_freq = 173000000, 5362 .max_pll_lpdiv = (1 << 13) - 1, 5363 .quirks = DSI_QUIRK_REVERSE_TXCLKESC, 5364 }; 5365 5366 static const struct dsi_of_data dsi_of_data_omap36xx = { 5367 .model = DSI_MODEL_OMAP3, 5368 .pll_hw = &dss_omap3_dsi_pll_hw, 5369 .modules = (const struct dsi_module_id_data[]) { 5370 { .address = 0x4804fc00, .id = 0, }, 5371 { }, 5372 }, 5373 .max_fck_freq = 173000000, 5374 .max_pll_lpdiv = (1 << 13) - 1, 5375 .quirks = DSI_QUIRK_PLL_PWR_BUG, 5376 }; 5377 5378 static const struct dsi_of_data dsi_of_data_omap4 = { 5379 .model = DSI_MODEL_OMAP4, 5380 .pll_hw = &dss_omap4_dsi_pll_hw, 5381 .modules = (const struct dsi_module_id_data[]) { 5382 { .address = 0x58004000, .id = 0, }, 5383 { .address = 0x58005000, .id = 1, }, 5384 { }, 5385 }, 5386 .max_fck_freq = 170000000, 5387 .max_pll_lpdiv = (1 << 13) - 1, 5388 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5389 | DSI_QUIRK_GNQ, 5390 }; 5391 5392 static const struct dsi_of_data dsi_of_data_omap5 = { 5393 .model = DSI_MODEL_OMAP5, 5394 .pll_hw = &dss_omap5_dsi_pll_hw, 5395 .modules = (const struct dsi_module_id_data[]) { 5396 { .address = 0x58004000, .id = 0, }, 5397 { .address = 0x58009000, .id = 1, }, 5398 { }, 5399 }, 5400 .max_fck_freq = 209250000, 5401 .max_pll_lpdiv = (1 << 13) - 1, 5402 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5403 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, 5404 }; 5405 5406 static const struct of_device_id dsi_of_match[] = { 5407 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, 5408 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, 5409 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, 5410 {}, 5411 }; 5412 5413 static const struct soc_device_attribute dsi_soc_devices[] = { 5414 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, 5415 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 5416 { /* sentinel */ } 5417 }; 5418 static int dsi_bind(struct device *dev, struct device *master, void *data) 5419 { 5420 struct platform_device *dsidev = to_platform_device(dev); 5421 const struct soc_device_attribute *soc; 5422 const struct dsi_module_id_data *d; 5423 u32 rev; 5424 int r, i; 5425 struct dsi_data *dsi; 5426 struct resource *dsi_mem; 5427 struct resource *res; 5428 5429 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5430 if (!dsi) 5431 return -ENOMEM; 5432 5433 dsi->pdev = dsidev; 5434 dev_set_drvdata(&dsidev->dev, dsi); 5435 5436 spin_lock_init(&dsi->irq_lock); 5437 spin_lock_init(&dsi->errors_lock); 5438 dsi->errors = 0; 5439 5440 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5441 spin_lock_init(&dsi->irq_stats_lock); 5442 dsi->irq_stats.last_reset = jiffies; 5443 #endif 5444 5445 mutex_init(&dsi->lock); 5446 sema_init(&dsi->bus_lock, 1); 5447 5448 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5449 dsi_framedone_timeout_work_callback); 5450 5451 #ifdef DSI_CATCH_MISSING_TE 5452 init_timer(&dsi->te_timer); 5453 dsi->te_timer.function = dsi_te_timeout; 5454 dsi->te_timer.data = 0; 5455 #endif 5456 5457 dsi_mem = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5458 dsi->proto_base = devm_ioremap_resource(&dsidev->dev, dsi_mem); 5459 if (IS_ERR(dsi->proto_base)) 5460 return PTR_ERR(dsi->proto_base); 5461 5462 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5463 dsi->phy_base = devm_ioremap_resource(&dsidev->dev, res); 5464 if (IS_ERR(dsi->phy_base)) 5465 return PTR_ERR(dsi->phy_base); 5466 5467 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5468 dsi->pll_base = devm_ioremap_resource(&dsidev->dev, res); 5469 if (IS_ERR(dsi->pll_base)) 5470 return PTR_ERR(dsi->pll_base); 5471 5472 dsi->irq = platform_get_irq(dsi->pdev, 0); 5473 if (dsi->irq < 0) { 5474 DSSERR("platform_get_irq failed\n"); 5475 return -ENODEV; 5476 } 5477 5478 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5479 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5480 if (r < 0) { 5481 DSSERR("request_irq failed\n"); 5482 return r; 5483 } 5484 5485 soc = soc_device_match(dsi_soc_devices); 5486 if (soc) 5487 dsi->data = soc->data; 5488 else 5489 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; 5490 5491 d = dsi->data->modules; 5492 while (d->address != 0 && d->address != dsi_mem->start) 5493 d++; 5494 5495 if (d->address == 0) { 5496 DSSERR("unsupported DSI module\n"); 5497 return -ENODEV; 5498 } 5499 5500 dsi->module_id = d->id; 5501 5502 if (dsi->data->model == DSI_MODEL_OMAP4 || 5503 dsi->data->model == DSI_MODEL_OMAP5) { 5504 struct device_node *np; 5505 5506 /* 5507 * The OMAP4/5 display DT bindings don't reference the padconf 5508 * syscon. Our only option to retrieve it is to find it by name. 5509 */ 5510 np = of_find_node_by_name(NULL, 5511 dsi->data->model == DSI_MODEL_OMAP4 ? 5512 "omap4_padconf_global" : "omap5_padconf_global"); 5513 if (!np) 5514 return -ENODEV; 5515 5516 dsi->syscon = syscon_node_to_regmap(np); 5517 of_node_put(np); 5518 } 5519 5520 /* DSI VCs initialization */ 5521 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5522 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5523 dsi->vc[i].dssdev = NULL; 5524 dsi->vc[i].vc_id = 0; 5525 } 5526 5527 r = dsi_get_clocks(dsidev); 5528 if (r) 5529 return r; 5530 5531 dsi_init_pll_data(dsidev); 5532 5533 pm_runtime_enable(&dsidev->dev); 5534 5535 r = dsi_runtime_get(dsidev); 5536 if (r) 5537 goto err_runtime_get; 5538 5539 rev = dsi_read_reg(dsidev, DSI_REVISION); 5540 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5541 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5542 5543 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5544 * of data to 3 by default */ 5545 if (dsi->data->quirks & DSI_QUIRK_GNQ) 5546 /* NB_DATA_LANES */ 5547 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5548 else 5549 dsi->num_lanes_supported = 3; 5550 5551 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5552 5553 dsi_init_output(dsidev); 5554 5555 r = dsi_probe_of(dsidev); 5556 if (r) { 5557 DSSERR("Invalid DSI DT data\n"); 5558 goto err_probe_of; 5559 } 5560 5561 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, &dsidev->dev); 5562 if (r) 5563 DSSERR("Failed to populate DSI child devices: %d\n", r); 5564 5565 dsi_runtime_put(dsidev); 5566 5567 if (dsi->module_id == 0) 5568 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5569 else if (dsi->module_id == 1) 5570 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5571 5572 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5573 if (dsi->module_id == 0) 5574 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5575 else if (dsi->module_id == 1) 5576 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5577 #endif 5578 5579 return 0; 5580 5581 err_probe_of: 5582 dsi_uninit_output(dsidev); 5583 dsi_runtime_put(dsidev); 5584 5585 err_runtime_get: 5586 pm_runtime_disable(&dsidev->dev); 5587 return r; 5588 } 5589 5590 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5591 { 5592 struct platform_device *dsidev = to_platform_device(dev); 5593 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5594 5595 of_platform_depopulate(&dsidev->dev); 5596 5597 WARN_ON(dsi->scp_clk_refcount > 0); 5598 5599 dss_pll_unregister(&dsi->pll); 5600 5601 dsi_uninit_output(dsidev); 5602 5603 pm_runtime_disable(&dsidev->dev); 5604 5605 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5606 regulator_disable(dsi->vdds_dsi_reg); 5607 dsi->vdds_dsi_enabled = false; 5608 } 5609 } 5610 5611 static const struct component_ops dsi_component_ops = { 5612 .bind = dsi_bind, 5613 .unbind = dsi_unbind, 5614 }; 5615 5616 static int dsi_probe(struct platform_device *pdev) 5617 { 5618 return component_add(&pdev->dev, &dsi_component_ops); 5619 } 5620 5621 static int dsi_remove(struct platform_device *pdev) 5622 { 5623 component_del(&pdev->dev, &dsi_component_ops); 5624 return 0; 5625 } 5626 5627 static int dsi_runtime_suspend(struct device *dev) 5628 { 5629 struct platform_device *pdev = to_platform_device(dev); 5630 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5631 5632 dsi->is_enabled = false; 5633 /* ensure the irq handler sees the is_enabled value */ 5634 smp_wmb(); 5635 /* wait for current handler to finish before turning the DSI off */ 5636 synchronize_irq(dsi->irq); 5637 5638 dispc_runtime_put(); 5639 5640 return 0; 5641 } 5642 5643 static int dsi_runtime_resume(struct device *dev) 5644 { 5645 struct platform_device *pdev = to_platform_device(dev); 5646 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5647 int r; 5648 5649 r = dispc_runtime_get(); 5650 if (r) 5651 return r; 5652 5653 dsi->is_enabled = true; 5654 /* ensure the irq handler sees the is_enabled value */ 5655 smp_wmb(); 5656 5657 return 0; 5658 } 5659 5660 static const struct dev_pm_ops dsi_pm_ops = { 5661 .runtime_suspend = dsi_runtime_suspend, 5662 .runtime_resume = dsi_runtime_resume, 5663 }; 5664 5665 static struct platform_driver omap_dsihw_driver = { 5666 .probe = dsi_probe, 5667 .remove = dsi_remove, 5668 .driver = { 5669 .name = "omapdss_dsi", 5670 .pm = &dsi_pm_ops, 5671 .of_match_table = dsi_of_match, 5672 .suppress_bind_attrs = true, 5673 }, 5674 }; 5675 5676 int __init dsi_init_platform_driver(void) 5677 { 5678 return platform_driver_register(&omap_dsihw_driver); 5679 } 5680 5681 void dsi_uninit_platform_driver(void) 5682 { 5683 platform_driver_unregister(&omap_dsihw_driver); 5684 } 5685