1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "DPI" 22 23 #include <linux/kernel.h> 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/errno.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/string.h> 31 #include <linux/of.h> 32 #include <linux/clk.h> 33 #include <linux/sys_soc.h> 34 35 #include "omapdss.h" 36 #include "dss.h" 37 38 struct dpi_data { 39 struct platform_device *pdev; 40 enum dss_model dss_model; 41 struct dss_device *dss; 42 43 struct regulator *vdds_dsi_reg; 44 enum dss_clk_source clk_src; 45 struct dss_pll *pll; 46 47 struct mutex lock; 48 49 struct videomode vm; 50 struct dss_lcd_mgr_config mgr_config; 51 int data_lines; 52 53 struct omap_dss_device output; 54 }; 55 56 static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev) 57 { 58 return container_of(dssdev, struct dpi_data, output); 59 } 60 61 static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi, 62 enum omap_channel channel) 63 { 64 /* 65 * Possible clock sources: 66 * LCD1: FCK/PLL1_1/HDMI_PLL 67 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) 68 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) 69 */ 70 71 switch (channel) { 72 case OMAP_DSS_CHANNEL_LCD: 73 { 74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1)) 75 return DSS_CLK_SRC_PLL1_1; 76 break; 77 } 78 case OMAP_DSS_CHANNEL_LCD2: 79 { 80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 81 return DSS_CLK_SRC_PLL1_3; 82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3)) 83 return DSS_CLK_SRC_PLL2_3; 84 break; 85 } 86 case OMAP_DSS_CHANNEL_LCD3: 87 { 88 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1)) 89 return DSS_CLK_SRC_PLL2_1; 90 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 91 return DSS_CLK_SRC_PLL1_3; 92 break; 93 } 94 default: 95 break; 96 } 97 98 return DSS_CLK_SRC_FCK; 99 } 100 101 static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) 102 { 103 enum omap_channel channel = dpi->output.dispc_channel; 104 105 /* 106 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL 107 * would also be used for DISPC fclk. Meaning, when the DPI output is 108 * disabled, DISPC clock will be disabled, and TV out will stop. 109 */ 110 switch (dpi->dss_model) { 111 case DSS_MODEL_OMAP2: 112 case DSS_MODEL_OMAP3: 113 return DSS_CLK_SRC_FCK; 114 115 case DSS_MODEL_OMAP4: 116 switch (channel) { 117 case OMAP_DSS_CHANNEL_LCD: 118 return DSS_CLK_SRC_PLL1_1; 119 case OMAP_DSS_CHANNEL_LCD2: 120 return DSS_CLK_SRC_PLL2_1; 121 default: 122 return DSS_CLK_SRC_FCK; 123 } 124 125 case DSS_MODEL_OMAP5: 126 switch (channel) { 127 case OMAP_DSS_CHANNEL_LCD: 128 return DSS_CLK_SRC_PLL1_1; 129 case OMAP_DSS_CHANNEL_LCD3: 130 return DSS_CLK_SRC_PLL2_1; 131 case OMAP_DSS_CHANNEL_LCD2: 132 default: 133 return DSS_CLK_SRC_FCK; 134 } 135 136 case DSS_MODEL_DRA7: 137 return dpi_get_clk_src_dra7xx(dpi, channel); 138 139 default: 140 return DSS_CLK_SRC_FCK; 141 } 142 } 143 144 struct dpi_clk_calc_ctx { 145 struct dpi_data *dpi; 146 unsigned int clkout_idx; 147 148 /* inputs */ 149 150 unsigned long pck_min, pck_max; 151 152 /* outputs */ 153 154 struct dss_pll_clock_info pll_cinfo; 155 unsigned long fck; 156 struct dispc_clock_info dispc_cinfo; 157 }; 158 159 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 160 unsigned long pck, void *data) 161 { 162 struct dpi_clk_calc_ctx *ctx = data; 163 164 /* 165 * Odd dividers give us uneven duty cycle, causing problem when level 166 * shifted. So skip all odd dividers when the pixel clock is on the 167 * higher side. 168 */ 169 if (ctx->pck_min >= 100000000) { 170 if (lckd > 1 && lckd % 2 != 0) 171 return false; 172 173 if (pckd > 1 && pckd % 2 != 0) 174 return false; 175 } 176 177 ctx->dispc_cinfo.lck_div = lckd; 178 ctx->dispc_cinfo.pck_div = pckd; 179 ctx->dispc_cinfo.lck = lck; 180 ctx->dispc_cinfo.pck = pck; 181 182 return true; 183 } 184 185 186 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 187 void *data) 188 { 189 struct dpi_clk_calc_ctx *ctx = data; 190 191 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 192 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 193 194 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, 195 ctx->pck_min, ctx->pck_max, 196 dpi_calc_dispc_cb, ctx); 197 } 198 199 200 static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, 201 unsigned long clkdco, 202 void *data) 203 { 204 struct dpi_clk_calc_ctx *ctx = data; 205 206 ctx->pll_cinfo.n = n; 207 ctx->pll_cinfo.m = m; 208 ctx->pll_cinfo.fint = fint; 209 ctx->pll_cinfo.clkdco = clkdco; 210 211 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco, 212 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss), 213 dpi_calc_hsdiv_cb, ctx); 214 } 215 216 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 217 { 218 struct dpi_clk_calc_ctx *ctx = data; 219 220 ctx->fck = fck; 221 222 return dispc_div_calc(ctx->dpi->dss->dispc, fck, 223 ctx->pck_min, ctx->pck_max, 224 dpi_calc_dispc_cb, ctx); 225 } 226 227 static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 228 struct dpi_clk_calc_ctx *ctx) 229 { 230 unsigned long clkin; 231 232 memset(ctx, 0, sizeof(*ctx)); 233 ctx->dpi = dpi; 234 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); 235 236 clkin = clk_get_rate(dpi->pll->clkin); 237 238 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { 239 unsigned long pll_min, pll_max; 240 241 ctx->pck_min = pck - 1000; 242 ctx->pck_max = pck + 1000; 243 244 pll_min = 0; 245 pll_max = 0; 246 247 return dss_pll_calc_a(ctx->dpi->pll, clkin, 248 pll_min, pll_max, 249 dpi_calc_pll_cb, ctx); 250 } else { /* DSS_PLL_TYPE_B */ 251 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); 252 253 ctx->dispc_cinfo.lck_div = 1; 254 ctx->dispc_cinfo.pck_div = 1; 255 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; 256 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; 257 258 return true; 259 } 260 } 261 262 static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck, 263 struct dpi_clk_calc_ctx *ctx) 264 { 265 int i; 266 267 /* 268 * DSS fck gives us very few possibilities, so finding a good pixel 269 * clock may not be possible. We try multiple times to find the clock, 270 * each time widening the pixel clock range we look for, up to 271 * +/- ~15MHz. 272 */ 273 274 for (i = 0; i < 25; ++i) { 275 bool ok; 276 277 memset(ctx, 0, sizeof(*ctx)); 278 ctx->dpi = dpi; 279 if (pck > 1000 * i * i * i) 280 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); 281 else 282 ctx->pck_min = 0; 283 ctx->pck_max = pck + 1000 * i * i * i; 284 285 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min, 286 dpi_calc_dss_cb, ctx); 287 if (ok) 288 return ok; 289 } 290 291 return false; 292 } 293 294 295 296 static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel, 297 unsigned long pck_req, unsigned long *fck, int *lck_div, 298 int *pck_div) 299 { 300 struct dpi_clk_calc_ctx ctx; 301 int r; 302 bool ok; 303 304 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); 305 if (!ok) 306 return -EINVAL; 307 308 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 309 if (r) 310 return r; 311 312 dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src); 313 314 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 315 316 *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 317 *lck_div = ctx.dispc_cinfo.lck_div; 318 *pck_div = ctx.dispc_cinfo.pck_div; 319 320 return 0; 321 } 322 323 static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req, 324 unsigned long *fck, int *lck_div, int *pck_div) 325 { 326 struct dpi_clk_calc_ctx ctx; 327 int r; 328 bool ok; 329 330 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx); 331 if (!ok) 332 return -EINVAL; 333 334 r = dss_set_fck_rate(dpi->dss, ctx.fck); 335 if (r) 336 return r; 337 338 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 339 340 *fck = ctx.fck; 341 *lck_div = ctx.dispc_cinfo.lck_div; 342 *pck_div = ctx.dispc_cinfo.pck_div; 343 344 return 0; 345 } 346 347 static int dpi_set_mode(struct dpi_data *dpi) 348 { 349 struct videomode *vm = &dpi->vm; 350 int lck_div = 0, pck_div = 0; 351 unsigned long fck = 0; 352 unsigned long pck; 353 int r = 0; 354 355 if (dpi->pll) 356 r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel, 357 vm->pixelclock, &fck, &lck_div, &pck_div); 358 else 359 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck, 360 &lck_div, &pck_div); 361 if (r) 362 return r; 363 364 pck = fck / lck_div / pck_div; 365 366 if (pck != vm->pixelclock) { 367 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 368 vm->pixelclock, pck); 369 370 vm->pixelclock = pck; 371 } 372 373 dss_mgr_set_timings(&dpi->output, vm); 374 375 return 0; 376 } 377 378 static void dpi_config_lcd_manager(struct dpi_data *dpi) 379 { 380 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 381 382 dpi->mgr_config.stallmode = false; 383 dpi->mgr_config.fifohandcheck = false; 384 385 dpi->mgr_config.video_port_width = dpi->data_lines; 386 387 dpi->mgr_config.lcden_sig_polarity = 0; 388 389 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config); 390 } 391 392 static int dpi_display_enable(struct omap_dss_device *dssdev) 393 { 394 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 395 struct omap_dss_device *out = &dpi->output; 396 int r; 397 398 mutex_lock(&dpi->lock); 399 400 if (!out->dispc_channel_connected) { 401 DSSERR("failed to enable display: no output/manager\n"); 402 r = -ENODEV; 403 goto err_no_out_mgr; 404 } 405 406 if (dpi->vdds_dsi_reg) { 407 r = regulator_enable(dpi->vdds_dsi_reg); 408 if (r) 409 goto err_reg_enable; 410 } 411 412 r = dispc_runtime_get(dpi->dss->dispc); 413 if (r) 414 goto err_get_dispc; 415 416 r = dss_dpi_select_source(dpi->dss, out->port_num, out->dispc_channel); 417 if (r) 418 goto err_src_sel; 419 420 if (dpi->pll) { 421 r = dss_pll_enable(dpi->pll); 422 if (r) 423 goto err_pll_init; 424 } 425 426 r = dpi_set_mode(dpi); 427 if (r) 428 goto err_set_mode; 429 430 dpi_config_lcd_manager(dpi); 431 432 mdelay(2); 433 434 r = dss_mgr_enable(&dpi->output); 435 if (r) 436 goto err_mgr_enable; 437 438 mutex_unlock(&dpi->lock); 439 440 return 0; 441 442 err_mgr_enable: 443 err_set_mode: 444 if (dpi->pll) 445 dss_pll_disable(dpi->pll); 446 err_pll_init: 447 err_src_sel: 448 dispc_runtime_put(dpi->dss->dispc); 449 err_get_dispc: 450 if (dpi->vdds_dsi_reg) 451 regulator_disable(dpi->vdds_dsi_reg); 452 err_reg_enable: 453 err_no_out_mgr: 454 mutex_unlock(&dpi->lock); 455 return r; 456 } 457 458 static void dpi_display_disable(struct omap_dss_device *dssdev) 459 { 460 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 461 462 mutex_lock(&dpi->lock); 463 464 dss_mgr_disable(&dpi->output); 465 466 if (dpi->pll) { 467 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel, 468 DSS_CLK_SRC_FCK); 469 dss_pll_disable(dpi->pll); 470 } 471 472 dispc_runtime_put(dpi->dss->dispc); 473 474 if (dpi->vdds_dsi_reg) 475 regulator_disable(dpi->vdds_dsi_reg); 476 477 mutex_unlock(&dpi->lock); 478 } 479 480 static void dpi_set_timings(struct omap_dss_device *dssdev, 481 struct videomode *vm) 482 { 483 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 484 485 DSSDBG("dpi_set_timings\n"); 486 487 mutex_lock(&dpi->lock); 488 489 dpi->vm = *vm; 490 491 mutex_unlock(&dpi->lock); 492 } 493 494 static void dpi_get_timings(struct omap_dss_device *dssdev, 495 struct videomode *vm) 496 { 497 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 498 499 mutex_lock(&dpi->lock); 500 501 *vm = dpi->vm; 502 503 mutex_unlock(&dpi->lock); 504 } 505 506 static int dpi_check_timings(struct omap_dss_device *dssdev, 507 struct videomode *vm) 508 { 509 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 510 enum omap_channel channel = dpi->output.dispc_channel; 511 int lck_div, pck_div; 512 unsigned long fck; 513 unsigned long pck; 514 struct dpi_clk_calc_ctx ctx; 515 bool ok; 516 517 if (vm->hactive % 8 != 0) 518 return -EINVAL; 519 520 if (!dispc_mgr_timings_ok(dpi->dss->dispc, channel, vm)) 521 return -EINVAL; 522 523 if (vm->pixelclock == 0) 524 return -EINVAL; 525 526 if (dpi->pll) { 527 ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx); 528 if (!ok) 529 return -EINVAL; 530 531 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 532 } else { 533 ok = dpi_dss_clk_calc(dpi, vm->pixelclock, &ctx); 534 if (!ok) 535 return -EINVAL; 536 537 fck = ctx.fck; 538 } 539 540 lck_div = ctx.dispc_cinfo.lck_div; 541 pck_div = ctx.dispc_cinfo.pck_div; 542 543 pck = fck / lck_div / pck_div; 544 545 vm->pixelclock = pck; 546 547 return 0; 548 } 549 550 static int dpi_verify_pll(struct dss_pll *pll) 551 { 552 int r; 553 554 /* do initial setup with the PLL to see if it is operational */ 555 556 r = dss_pll_enable(pll); 557 if (r) 558 return r; 559 560 dss_pll_disable(pll); 561 562 return 0; 563 } 564 565 static const struct soc_device_attribute dpi_soc_devices[] = { 566 { .machine = "OMAP3[456]*" }, 567 { .machine = "[AD]M37*" }, 568 { /* sentinel */ } 569 }; 570 571 static int dpi_init_regulator(struct dpi_data *dpi) 572 { 573 struct regulator *vdds_dsi; 574 575 /* 576 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and 577 * DM37xx only. 578 */ 579 if (!soc_device_match(dpi_soc_devices)) 580 return 0; 581 582 if (dpi->vdds_dsi_reg) 583 return 0; 584 585 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi"); 586 if (IS_ERR(vdds_dsi)) { 587 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 588 DSSERR("can't get VDDS_DSI regulator\n"); 589 return PTR_ERR(vdds_dsi); 590 } 591 592 dpi->vdds_dsi_reg = vdds_dsi; 593 594 return 0; 595 } 596 597 static void dpi_init_pll(struct dpi_data *dpi) 598 { 599 struct dss_pll *pll; 600 601 if (dpi->pll) 602 return; 603 604 dpi->clk_src = dpi_get_clk_src(dpi); 605 606 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src); 607 if (!pll) 608 return; 609 610 if (dpi_verify_pll(pll)) { 611 DSSWARN("PLL not operational\n"); 612 return; 613 } 614 615 dpi->pll = pll; 616 } 617 618 /* 619 * Return a hardcoded channel for the DPI output. This should work for 620 * current use cases, but this can be later expanded to either resolve 621 * the channel in some more dynamic manner, or get the channel as a user 622 * parameter. 623 */ 624 static enum omap_channel dpi_get_channel(struct dpi_data *dpi, int port_num) 625 { 626 switch (dpi->dss_model) { 627 case DSS_MODEL_OMAP2: 628 case DSS_MODEL_OMAP3: 629 return OMAP_DSS_CHANNEL_LCD; 630 631 case DSS_MODEL_DRA7: 632 switch (port_num) { 633 case 2: 634 return OMAP_DSS_CHANNEL_LCD3; 635 case 1: 636 return OMAP_DSS_CHANNEL_LCD2; 637 case 0: 638 default: 639 return OMAP_DSS_CHANNEL_LCD; 640 } 641 642 case DSS_MODEL_OMAP4: 643 return OMAP_DSS_CHANNEL_LCD2; 644 645 case DSS_MODEL_OMAP5: 646 return OMAP_DSS_CHANNEL_LCD3; 647 648 default: 649 DSSWARN("unsupported DSS version\n"); 650 return OMAP_DSS_CHANNEL_LCD; 651 } 652 } 653 654 static int dpi_connect(struct omap_dss_device *dssdev, 655 struct omap_dss_device *dst) 656 { 657 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 658 int r; 659 660 r = dpi_init_regulator(dpi); 661 if (r) 662 return r; 663 664 dpi_init_pll(dpi); 665 666 r = dss_mgr_connect(&dpi->output, dssdev); 667 if (r) 668 return r; 669 670 r = omapdss_output_set_device(dssdev, dst); 671 if (r) { 672 DSSERR("failed to connect output to new device: %s\n", 673 dst->name); 674 dss_mgr_disconnect(&dpi->output, dssdev); 675 return r; 676 } 677 678 return 0; 679 } 680 681 static void dpi_disconnect(struct omap_dss_device *dssdev, 682 struct omap_dss_device *dst) 683 { 684 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 685 686 WARN_ON(dst != dssdev->dst); 687 688 if (dst != dssdev->dst) 689 return; 690 691 omapdss_output_unset_device(dssdev); 692 693 dss_mgr_disconnect(&dpi->output, dssdev); 694 } 695 696 static const struct omapdss_dpi_ops dpi_ops = { 697 .connect = dpi_connect, 698 .disconnect = dpi_disconnect, 699 700 .enable = dpi_display_enable, 701 .disable = dpi_display_disable, 702 703 .check_timings = dpi_check_timings, 704 .set_timings = dpi_set_timings, 705 .get_timings = dpi_get_timings, 706 }; 707 708 static void dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) 709 { 710 struct omap_dss_device *out = &dpi->output; 711 int r; 712 u32 port_num; 713 714 r = of_property_read_u32(port, "reg", &port_num); 715 if (r) 716 port_num = 0; 717 718 switch (port_num) { 719 case 2: 720 out->name = "dpi.2"; 721 break; 722 case 1: 723 out->name = "dpi.1"; 724 break; 725 case 0: 726 default: 727 out->name = "dpi.0"; 728 break; 729 } 730 731 out->dev = &dpi->pdev->dev; 732 out->id = OMAP_DSS_OUTPUT_DPI; 733 out->output_type = OMAP_DISPLAY_TYPE_DPI; 734 out->dispc_channel = dpi_get_channel(dpi, port_num); 735 out->port_num = port_num; 736 out->ops.dpi = &dpi_ops; 737 out->owner = THIS_MODULE; 738 739 omapdss_register_output(out); 740 } 741 742 static void dpi_uninit_output_port(struct device_node *port) 743 { 744 struct dpi_data *dpi = port->data; 745 struct omap_dss_device *out = &dpi->output; 746 747 omapdss_unregister_output(out); 748 } 749 750 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 751 struct device_node *port, enum dss_model dss_model) 752 { 753 struct dpi_data *dpi; 754 struct device_node *ep; 755 u32 datalines; 756 int r; 757 758 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); 759 if (!dpi) 760 return -ENOMEM; 761 762 ep = of_get_next_child(port, NULL); 763 if (!ep) 764 return 0; 765 766 r = of_property_read_u32(ep, "data-lines", &datalines); 767 if (r) { 768 DSSERR("failed to parse datalines\n"); 769 goto err_datalines; 770 } 771 772 dpi->data_lines = datalines; 773 774 of_node_put(ep); 775 776 dpi->pdev = pdev; 777 dpi->dss_model = dss_model; 778 dpi->dss = dss; 779 port->data = dpi; 780 781 mutex_init(&dpi->lock); 782 783 dpi_init_output_port(dpi, port); 784 785 return 0; 786 787 err_datalines: 788 of_node_put(ep); 789 790 return r; 791 } 792 793 void dpi_uninit_port(struct device_node *port) 794 { 795 struct dpi_data *dpi = port->data; 796 797 if (!dpi) 798 return; 799 800 dpi_uninit_output_port(port); 801 } 802