1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "DPI" 22 23 #include <linux/kernel.h> 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/errno.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/string.h> 31 #include <linux/of.h> 32 #include <linux/clk.h> 33 #include <linux/sys_soc.h> 34 35 #include "omapdss.h" 36 #include "dss.h" 37 38 struct dpi_data { 39 struct platform_device *pdev; 40 enum dss_model dss_model; 41 struct dss_device *dss; 42 43 struct regulator *vdds_dsi_reg; 44 enum dss_clk_source clk_src; 45 struct dss_pll *pll; 46 47 struct mutex lock; 48 49 struct videomode vm; 50 struct dss_lcd_mgr_config mgr_config; 51 int data_lines; 52 53 struct omap_dss_device output; 54 }; 55 56 static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev) 57 { 58 return container_of(dssdev, struct dpi_data, output); 59 } 60 61 static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi, 62 enum omap_channel channel) 63 { 64 /* 65 * Possible clock sources: 66 * LCD1: FCK/PLL1_1/HDMI_PLL 67 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) 68 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) 69 */ 70 71 switch (channel) { 72 case OMAP_DSS_CHANNEL_LCD: 73 { 74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1)) 75 return DSS_CLK_SRC_PLL1_1; 76 break; 77 } 78 case OMAP_DSS_CHANNEL_LCD2: 79 { 80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 81 return DSS_CLK_SRC_PLL1_3; 82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3)) 83 return DSS_CLK_SRC_PLL2_3; 84 break; 85 } 86 case OMAP_DSS_CHANNEL_LCD3: 87 { 88 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1)) 89 return DSS_CLK_SRC_PLL2_1; 90 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 91 return DSS_CLK_SRC_PLL1_3; 92 break; 93 } 94 default: 95 break; 96 } 97 98 return DSS_CLK_SRC_FCK; 99 } 100 101 static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) 102 { 103 enum omap_channel channel = dpi->output.dispc_channel; 104 105 /* 106 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL 107 * would also be used for DISPC fclk. Meaning, when the DPI output is 108 * disabled, DISPC clock will be disabled, and TV out will stop. 109 */ 110 switch (dpi->dss_model) { 111 case DSS_MODEL_OMAP2: 112 case DSS_MODEL_OMAP3: 113 return DSS_CLK_SRC_FCK; 114 115 case DSS_MODEL_OMAP4: 116 switch (channel) { 117 case OMAP_DSS_CHANNEL_LCD: 118 return DSS_CLK_SRC_PLL1_1; 119 case OMAP_DSS_CHANNEL_LCD2: 120 return DSS_CLK_SRC_PLL2_1; 121 default: 122 return DSS_CLK_SRC_FCK; 123 } 124 125 case DSS_MODEL_OMAP5: 126 switch (channel) { 127 case OMAP_DSS_CHANNEL_LCD: 128 return DSS_CLK_SRC_PLL1_1; 129 case OMAP_DSS_CHANNEL_LCD3: 130 return DSS_CLK_SRC_PLL2_1; 131 case OMAP_DSS_CHANNEL_LCD2: 132 default: 133 return DSS_CLK_SRC_FCK; 134 } 135 136 case DSS_MODEL_DRA7: 137 return dpi_get_clk_src_dra7xx(dpi, channel); 138 139 default: 140 return DSS_CLK_SRC_FCK; 141 } 142 } 143 144 struct dpi_clk_calc_ctx { 145 struct dss_pll *pll; 146 unsigned int clkout_idx; 147 148 /* inputs */ 149 150 unsigned long pck_min, pck_max; 151 152 /* outputs */ 153 154 struct dss_pll_clock_info pll_cinfo; 155 unsigned long fck; 156 struct dispc_clock_info dispc_cinfo; 157 }; 158 159 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 160 unsigned long pck, void *data) 161 { 162 struct dpi_clk_calc_ctx *ctx = data; 163 164 /* 165 * Odd dividers give us uneven duty cycle, causing problem when level 166 * shifted. So skip all odd dividers when the pixel clock is on the 167 * higher side. 168 */ 169 if (ctx->pck_min >= 100000000) { 170 if (lckd > 1 && lckd % 2 != 0) 171 return false; 172 173 if (pckd > 1 && pckd % 2 != 0) 174 return false; 175 } 176 177 ctx->dispc_cinfo.lck_div = lckd; 178 ctx->dispc_cinfo.pck_div = pckd; 179 ctx->dispc_cinfo.lck = lck; 180 ctx->dispc_cinfo.pck = pck; 181 182 return true; 183 } 184 185 186 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 187 void *data) 188 { 189 struct dpi_clk_calc_ctx *ctx = data; 190 191 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 192 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 193 194 return dispc_div_calc(ctx->pll->dss->dispc, dispc, 195 ctx->pck_min, ctx->pck_max, 196 dpi_calc_dispc_cb, ctx); 197 } 198 199 200 static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, 201 unsigned long clkdco, 202 void *data) 203 { 204 struct dpi_clk_calc_ctx *ctx = data; 205 206 ctx->pll_cinfo.n = n; 207 ctx->pll_cinfo.m = m; 208 ctx->pll_cinfo.fint = fint; 209 ctx->pll_cinfo.clkdco = clkdco; 210 211 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, 212 ctx->pck_min, dss_get_max_fck_rate(ctx->pll->dss), 213 dpi_calc_hsdiv_cb, ctx); 214 } 215 216 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 217 { 218 struct dpi_clk_calc_ctx *ctx = data; 219 220 ctx->fck = fck; 221 222 return dispc_div_calc(ctx->pll->dss->dispc, fck, 223 ctx->pck_min, ctx->pck_max, 224 dpi_calc_dispc_cb, ctx); 225 } 226 227 static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 228 struct dpi_clk_calc_ctx *ctx) 229 { 230 unsigned long clkin; 231 232 memset(ctx, 0, sizeof(*ctx)); 233 ctx->pll = dpi->pll; 234 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); 235 236 clkin = clk_get_rate(dpi->pll->clkin); 237 238 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { 239 unsigned long pll_min, pll_max; 240 241 ctx->pck_min = pck - 1000; 242 ctx->pck_max = pck + 1000; 243 244 pll_min = 0; 245 pll_max = 0; 246 247 return dss_pll_calc_a(ctx->pll, clkin, 248 pll_min, pll_max, 249 dpi_calc_pll_cb, ctx); 250 } else { /* DSS_PLL_TYPE_B */ 251 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); 252 253 ctx->dispc_cinfo.lck_div = 1; 254 ctx->dispc_cinfo.pck_div = 1; 255 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; 256 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; 257 258 return true; 259 } 260 } 261 262 static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck, 263 struct dpi_clk_calc_ctx *ctx) 264 { 265 int i; 266 267 /* 268 * DSS fck gives us very few possibilities, so finding a good pixel 269 * clock may not be possible. We try multiple times to find the clock, 270 * each time widening the pixel clock range we look for, up to 271 * +/- ~15MHz. 272 */ 273 274 for (i = 0; i < 25; ++i) { 275 bool ok; 276 277 memset(ctx, 0, sizeof(*ctx)); 278 if (pck > 1000 * i * i * i) 279 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); 280 else 281 ctx->pck_min = 0; 282 ctx->pck_max = pck + 1000 * i * i * i; 283 284 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min, 285 dpi_calc_dss_cb, ctx); 286 if (ok) 287 return ok; 288 } 289 290 return false; 291 } 292 293 294 295 static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel, 296 unsigned long pck_req, unsigned long *fck, int *lck_div, 297 int *pck_div) 298 { 299 struct dpi_clk_calc_ctx ctx; 300 int r; 301 bool ok; 302 303 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); 304 if (!ok) 305 return -EINVAL; 306 307 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 308 if (r) 309 return r; 310 311 dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src); 312 313 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 314 315 *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 316 *lck_div = ctx.dispc_cinfo.lck_div; 317 *pck_div = ctx.dispc_cinfo.pck_div; 318 319 return 0; 320 } 321 322 static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req, 323 unsigned long *fck, int *lck_div, int *pck_div) 324 { 325 struct dpi_clk_calc_ctx ctx; 326 int r; 327 bool ok; 328 329 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx); 330 if (!ok) 331 return -EINVAL; 332 333 r = dss_set_fck_rate(dpi->dss, ctx.fck); 334 if (r) 335 return r; 336 337 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 338 339 *fck = ctx.fck; 340 *lck_div = ctx.dispc_cinfo.lck_div; 341 *pck_div = ctx.dispc_cinfo.pck_div; 342 343 return 0; 344 } 345 346 static int dpi_set_mode(struct dpi_data *dpi) 347 { 348 struct videomode *vm = &dpi->vm; 349 int lck_div = 0, pck_div = 0; 350 unsigned long fck = 0; 351 unsigned long pck; 352 int r = 0; 353 354 if (dpi->pll) 355 r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel, 356 vm->pixelclock, &fck, &lck_div, &pck_div); 357 else 358 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck, 359 &lck_div, &pck_div); 360 if (r) 361 return r; 362 363 pck = fck / lck_div / pck_div; 364 365 if (pck != vm->pixelclock) { 366 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 367 vm->pixelclock, pck); 368 369 vm->pixelclock = pck; 370 } 371 372 dss_mgr_set_timings(&dpi->output, vm); 373 374 return 0; 375 } 376 377 static void dpi_config_lcd_manager(struct dpi_data *dpi) 378 { 379 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 380 381 dpi->mgr_config.stallmode = false; 382 dpi->mgr_config.fifohandcheck = false; 383 384 dpi->mgr_config.video_port_width = dpi->data_lines; 385 386 dpi->mgr_config.lcden_sig_polarity = 0; 387 388 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config); 389 } 390 391 static int dpi_display_enable(struct omap_dss_device *dssdev) 392 { 393 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 394 struct omap_dss_device *out = &dpi->output; 395 int r; 396 397 mutex_lock(&dpi->lock); 398 399 if (!out->dispc_channel_connected) { 400 DSSERR("failed to enable display: no output/manager\n"); 401 r = -ENODEV; 402 goto err_no_out_mgr; 403 } 404 405 if (dpi->vdds_dsi_reg) { 406 r = regulator_enable(dpi->vdds_dsi_reg); 407 if (r) 408 goto err_reg_enable; 409 } 410 411 r = dispc_runtime_get(dpi->dss->dispc); 412 if (r) 413 goto err_get_dispc; 414 415 r = dss_dpi_select_source(dpi->dss, out->port_num, out->dispc_channel); 416 if (r) 417 goto err_src_sel; 418 419 if (dpi->pll) { 420 r = dss_pll_enable(dpi->pll); 421 if (r) 422 goto err_pll_init; 423 } 424 425 r = dpi_set_mode(dpi); 426 if (r) 427 goto err_set_mode; 428 429 dpi_config_lcd_manager(dpi); 430 431 mdelay(2); 432 433 r = dss_mgr_enable(&dpi->output); 434 if (r) 435 goto err_mgr_enable; 436 437 mutex_unlock(&dpi->lock); 438 439 return 0; 440 441 err_mgr_enable: 442 err_set_mode: 443 if (dpi->pll) 444 dss_pll_disable(dpi->pll); 445 err_pll_init: 446 err_src_sel: 447 dispc_runtime_put(dpi->dss->dispc); 448 err_get_dispc: 449 if (dpi->vdds_dsi_reg) 450 regulator_disable(dpi->vdds_dsi_reg); 451 err_reg_enable: 452 err_no_out_mgr: 453 mutex_unlock(&dpi->lock); 454 return r; 455 } 456 457 static void dpi_display_disable(struct omap_dss_device *dssdev) 458 { 459 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 460 461 mutex_lock(&dpi->lock); 462 463 dss_mgr_disable(&dpi->output); 464 465 if (dpi->pll) { 466 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel, 467 DSS_CLK_SRC_FCK); 468 dss_pll_disable(dpi->pll); 469 } 470 471 dispc_runtime_put(dpi->dss->dispc); 472 473 if (dpi->vdds_dsi_reg) 474 regulator_disable(dpi->vdds_dsi_reg); 475 476 mutex_unlock(&dpi->lock); 477 } 478 479 static void dpi_set_timings(struct omap_dss_device *dssdev, 480 struct videomode *vm) 481 { 482 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 483 484 DSSDBG("dpi_set_timings\n"); 485 486 mutex_lock(&dpi->lock); 487 488 dpi->vm = *vm; 489 490 mutex_unlock(&dpi->lock); 491 } 492 493 static void dpi_get_timings(struct omap_dss_device *dssdev, 494 struct videomode *vm) 495 { 496 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 497 498 mutex_lock(&dpi->lock); 499 500 *vm = dpi->vm; 501 502 mutex_unlock(&dpi->lock); 503 } 504 505 static int dpi_check_timings(struct omap_dss_device *dssdev, 506 struct videomode *vm) 507 { 508 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 509 enum omap_channel channel = dpi->output.dispc_channel; 510 int lck_div, pck_div; 511 unsigned long fck; 512 unsigned long pck; 513 struct dpi_clk_calc_ctx ctx; 514 bool ok; 515 516 if (vm->hactive % 8 != 0) 517 return -EINVAL; 518 519 if (!dispc_mgr_timings_ok(dpi->dss->dispc, channel, vm)) 520 return -EINVAL; 521 522 if (vm->pixelclock == 0) 523 return -EINVAL; 524 525 if (dpi->pll) { 526 ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx); 527 if (!ok) 528 return -EINVAL; 529 530 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 531 } else { 532 ok = dpi_dss_clk_calc(dpi, vm->pixelclock, &ctx); 533 if (!ok) 534 return -EINVAL; 535 536 fck = ctx.fck; 537 } 538 539 lck_div = ctx.dispc_cinfo.lck_div; 540 pck_div = ctx.dispc_cinfo.pck_div; 541 542 pck = fck / lck_div / pck_div; 543 544 vm->pixelclock = pck; 545 546 return 0; 547 } 548 549 static int dpi_verify_pll(struct dss_pll *pll) 550 { 551 int r; 552 553 /* do initial setup with the PLL to see if it is operational */ 554 555 r = dss_pll_enable(pll); 556 if (r) 557 return r; 558 559 dss_pll_disable(pll); 560 561 return 0; 562 } 563 564 static const struct soc_device_attribute dpi_soc_devices[] = { 565 { .machine = "OMAP3[456]*" }, 566 { .machine = "[AD]M37*" }, 567 { /* sentinel */ } 568 }; 569 570 static int dpi_init_regulator(struct dpi_data *dpi) 571 { 572 struct regulator *vdds_dsi; 573 574 /* 575 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and 576 * DM37xx only. 577 */ 578 if (!soc_device_match(dpi_soc_devices)) 579 return 0; 580 581 if (dpi->vdds_dsi_reg) 582 return 0; 583 584 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi"); 585 if (IS_ERR(vdds_dsi)) { 586 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 587 DSSERR("can't get VDDS_DSI regulator\n"); 588 return PTR_ERR(vdds_dsi); 589 } 590 591 dpi->vdds_dsi_reg = vdds_dsi; 592 593 return 0; 594 } 595 596 static void dpi_init_pll(struct dpi_data *dpi) 597 { 598 struct dss_pll *pll; 599 600 if (dpi->pll) 601 return; 602 603 dpi->clk_src = dpi_get_clk_src(dpi); 604 605 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src); 606 if (!pll) 607 return; 608 609 if (dpi_verify_pll(pll)) { 610 DSSWARN("PLL not operational\n"); 611 return; 612 } 613 614 dpi->pll = pll; 615 } 616 617 /* 618 * Return a hardcoded channel for the DPI output. This should work for 619 * current use cases, but this can be later expanded to either resolve 620 * the channel in some more dynamic manner, or get the channel as a user 621 * parameter. 622 */ 623 static enum omap_channel dpi_get_channel(struct dpi_data *dpi, int port_num) 624 { 625 switch (dpi->dss_model) { 626 case DSS_MODEL_OMAP2: 627 case DSS_MODEL_OMAP3: 628 return OMAP_DSS_CHANNEL_LCD; 629 630 case DSS_MODEL_DRA7: 631 switch (port_num) { 632 case 2: 633 return OMAP_DSS_CHANNEL_LCD3; 634 case 1: 635 return OMAP_DSS_CHANNEL_LCD2; 636 case 0: 637 default: 638 return OMAP_DSS_CHANNEL_LCD; 639 } 640 641 case DSS_MODEL_OMAP4: 642 return OMAP_DSS_CHANNEL_LCD2; 643 644 case DSS_MODEL_OMAP5: 645 return OMAP_DSS_CHANNEL_LCD3; 646 647 default: 648 DSSWARN("unsupported DSS version\n"); 649 return OMAP_DSS_CHANNEL_LCD; 650 } 651 } 652 653 static int dpi_connect(struct omap_dss_device *dssdev, 654 struct omap_dss_device *dst) 655 { 656 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 657 int r; 658 659 r = dpi_init_regulator(dpi); 660 if (r) 661 return r; 662 663 dpi_init_pll(dpi); 664 665 r = dss_mgr_connect(&dpi->output, dssdev); 666 if (r) 667 return r; 668 669 r = omapdss_output_set_device(dssdev, dst); 670 if (r) { 671 DSSERR("failed to connect output to new device: %s\n", 672 dst->name); 673 dss_mgr_disconnect(&dpi->output, dssdev); 674 return r; 675 } 676 677 return 0; 678 } 679 680 static void dpi_disconnect(struct omap_dss_device *dssdev, 681 struct omap_dss_device *dst) 682 { 683 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 684 685 WARN_ON(dst != dssdev->dst); 686 687 if (dst != dssdev->dst) 688 return; 689 690 omapdss_output_unset_device(dssdev); 691 692 dss_mgr_disconnect(&dpi->output, dssdev); 693 } 694 695 static const struct omapdss_dpi_ops dpi_ops = { 696 .connect = dpi_connect, 697 .disconnect = dpi_disconnect, 698 699 .enable = dpi_display_enable, 700 .disable = dpi_display_disable, 701 702 .check_timings = dpi_check_timings, 703 .set_timings = dpi_set_timings, 704 .get_timings = dpi_get_timings, 705 }; 706 707 static void dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) 708 { 709 struct omap_dss_device *out = &dpi->output; 710 int r; 711 u32 port_num; 712 713 r = of_property_read_u32(port, "reg", &port_num); 714 if (r) 715 port_num = 0; 716 717 switch (port_num) { 718 case 2: 719 out->name = "dpi.2"; 720 break; 721 case 1: 722 out->name = "dpi.1"; 723 break; 724 case 0: 725 default: 726 out->name = "dpi.0"; 727 break; 728 } 729 730 out->dev = &dpi->pdev->dev; 731 out->id = OMAP_DSS_OUTPUT_DPI; 732 out->output_type = OMAP_DISPLAY_TYPE_DPI; 733 out->dispc_channel = dpi_get_channel(dpi, port_num); 734 out->port_num = port_num; 735 out->ops.dpi = &dpi_ops; 736 out->owner = THIS_MODULE; 737 738 omapdss_register_output(out); 739 } 740 741 static void dpi_uninit_output_port(struct device_node *port) 742 { 743 struct dpi_data *dpi = port->data; 744 struct omap_dss_device *out = &dpi->output; 745 746 omapdss_unregister_output(out); 747 } 748 749 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 750 struct device_node *port, enum dss_model dss_model) 751 { 752 struct dpi_data *dpi; 753 struct device_node *ep; 754 u32 datalines; 755 int r; 756 757 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); 758 if (!dpi) 759 return -ENOMEM; 760 761 ep = of_get_next_child(port, NULL); 762 if (!ep) 763 return 0; 764 765 r = of_property_read_u32(ep, "data-lines", &datalines); 766 if (r) { 767 DSSERR("failed to parse datalines\n"); 768 goto err_datalines; 769 } 770 771 dpi->data_lines = datalines; 772 773 of_node_put(ep); 774 775 dpi->pdev = pdev; 776 dpi->dss_model = dss_model; 777 dpi->dss = dss; 778 port->data = dpi; 779 780 mutex_init(&dpi->lock); 781 782 dpi_init_output_port(dpi, port); 783 784 return 0; 785 786 err_datalines: 787 of_node_put(ep); 788 789 return r; 790 } 791 792 void dpi_uninit_port(struct device_node *port) 793 { 794 struct dpi_data *dpi = port->data; 795 796 if (!dpi) 797 return; 798 799 dpi_uninit_output_port(port); 800 } 801