1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define DSS_SUBSYS_NAME "DPI" 22 23 #include <linux/kernel.h> 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/errno.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/string.h> 31 #include <linux/of.h> 32 #include <linux/clk.h> 33 #include <linux/sys_soc.h> 34 35 #include "omapdss.h" 36 #include "dss.h" 37 38 struct dpi_data { 39 struct platform_device *pdev; 40 enum dss_model dss_model; 41 struct dss_device *dss; 42 unsigned int id; 43 44 struct regulator *vdds_dsi_reg; 45 enum dss_clk_source clk_src; 46 struct dss_pll *pll; 47 48 struct mutex lock; 49 50 struct dss_lcd_mgr_config mgr_config; 51 unsigned long pixelclock; 52 int data_lines; 53 54 struct omap_dss_device output; 55 }; 56 57 static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev) 58 { 59 return container_of(dssdev, struct dpi_data, output); 60 } 61 62 static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi, 63 enum omap_channel channel) 64 { 65 /* 66 * Possible clock sources: 67 * LCD1: FCK/PLL1_1/HDMI_PLL 68 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) 69 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) 70 */ 71 72 switch (channel) { 73 case OMAP_DSS_CHANNEL_LCD: 74 { 75 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1)) 76 return DSS_CLK_SRC_PLL1_1; 77 break; 78 } 79 case OMAP_DSS_CHANNEL_LCD2: 80 { 81 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 82 return DSS_CLK_SRC_PLL1_3; 83 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3)) 84 return DSS_CLK_SRC_PLL2_3; 85 break; 86 } 87 case OMAP_DSS_CHANNEL_LCD3: 88 { 89 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1)) 90 return DSS_CLK_SRC_PLL2_1; 91 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 92 return DSS_CLK_SRC_PLL1_3; 93 break; 94 } 95 default: 96 break; 97 } 98 99 return DSS_CLK_SRC_FCK; 100 } 101 102 static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) 103 { 104 enum omap_channel channel = dpi->output.dispc_channel; 105 106 /* 107 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL 108 * would also be used for DISPC fclk. Meaning, when the DPI output is 109 * disabled, DISPC clock will be disabled, and TV out will stop. 110 */ 111 switch (dpi->dss_model) { 112 case DSS_MODEL_OMAP2: 113 case DSS_MODEL_OMAP3: 114 return DSS_CLK_SRC_FCK; 115 116 case DSS_MODEL_OMAP4: 117 switch (channel) { 118 case OMAP_DSS_CHANNEL_LCD: 119 return DSS_CLK_SRC_PLL1_1; 120 case OMAP_DSS_CHANNEL_LCD2: 121 return DSS_CLK_SRC_PLL2_1; 122 default: 123 return DSS_CLK_SRC_FCK; 124 } 125 126 case DSS_MODEL_OMAP5: 127 switch (channel) { 128 case OMAP_DSS_CHANNEL_LCD: 129 return DSS_CLK_SRC_PLL1_1; 130 case OMAP_DSS_CHANNEL_LCD3: 131 return DSS_CLK_SRC_PLL2_1; 132 case OMAP_DSS_CHANNEL_LCD2: 133 default: 134 return DSS_CLK_SRC_FCK; 135 } 136 137 case DSS_MODEL_DRA7: 138 return dpi_get_clk_src_dra7xx(dpi, channel); 139 140 default: 141 return DSS_CLK_SRC_FCK; 142 } 143 } 144 145 struct dpi_clk_calc_ctx { 146 struct dpi_data *dpi; 147 unsigned int clkout_idx; 148 149 /* inputs */ 150 151 unsigned long pck_min, pck_max; 152 153 /* outputs */ 154 155 struct dss_pll_clock_info pll_cinfo; 156 unsigned long fck; 157 struct dispc_clock_info dispc_cinfo; 158 }; 159 160 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 161 unsigned long pck, void *data) 162 { 163 struct dpi_clk_calc_ctx *ctx = data; 164 165 /* 166 * Odd dividers give us uneven duty cycle, causing problem when level 167 * shifted. So skip all odd dividers when the pixel clock is on the 168 * higher side. 169 */ 170 if (ctx->pck_min >= 100000000) { 171 if (lckd > 1 && lckd % 2 != 0) 172 return false; 173 174 if (pckd > 1 && pckd % 2 != 0) 175 return false; 176 } 177 178 ctx->dispc_cinfo.lck_div = lckd; 179 ctx->dispc_cinfo.pck_div = pckd; 180 ctx->dispc_cinfo.lck = lck; 181 ctx->dispc_cinfo.pck = pck; 182 183 return true; 184 } 185 186 187 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 188 void *data) 189 { 190 struct dpi_clk_calc_ctx *ctx = data; 191 192 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 193 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 194 195 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, 196 ctx->pck_min, ctx->pck_max, 197 dpi_calc_dispc_cb, ctx); 198 } 199 200 201 static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, 202 unsigned long clkdco, 203 void *data) 204 { 205 struct dpi_clk_calc_ctx *ctx = data; 206 207 ctx->pll_cinfo.n = n; 208 ctx->pll_cinfo.m = m; 209 ctx->pll_cinfo.fint = fint; 210 ctx->pll_cinfo.clkdco = clkdco; 211 212 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco, 213 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss), 214 dpi_calc_hsdiv_cb, ctx); 215 } 216 217 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 218 { 219 struct dpi_clk_calc_ctx *ctx = data; 220 221 ctx->fck = fck; 222 223 return dispc_div_calc(ctx->dpi->dss->dispc, fck, 224 ctx->pck_min, ctx->pck_max, 225 dpi_calc_dispc_cb, ctx); 226 } 227 228 static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 229 struct dpi_clk_calc_ctx *ctx) 230 { 231 unsigned long clkin; 232 233 memset(ctx, 0, sizeof(*ctx)); 234 ctx->dpi = dpi; 235 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); 236 237 clkin = clk_get_rate(dpi->pll->clkin); 238 239 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { 240 unsigned long pll_min, pll_max; 241 242 ctx->pck_min = pck - 1000; 243 ctx->pck_max = pck + 1000; 244 245 pll_min = 0; 246 pll_max = 0; 247 248 return dss_pll_calc_a(ctx->dpi->pll, clkin, 249 pll_min, pll_max, 250 dpi_calc_pll_cb, ctx); 251 } else { /* DSS_PLL_TYPE_B */ 252 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); 253 254 ctx->dispc_cinfo.lck_div = 1; 255 ctx->dispc_cinfo.pck_div = 1; 256 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; 257 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; 258 259 return true; 260 } 261 } 262 263 static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck, 264 struct dpi_clk_calc_ctx *ctx) 265 { 266 int i; 267 268 /* 269 * DSS fck gives us very few possibilities, so finding a good pixel 270 * clock may not be possible. We try multiple times to find the clock, 271 * each time widening the pixel clock range we look for, up to 272 * +/- ~15MHz. 273 */ 274 275 for (i = 0; i < 25; ++i) { 276 bool ok; 277 278 memset(ctx, 0, sizeof(*ctx)); 279 ctx->dpi = dpi; 280 if (pck > 1000 * i * i * i) 281 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); 282 else 283 ctx->pck_min = 0; 284 ctx->pck_max = pck + 1000 * i * i * i; 285 286 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min, 287 dpi_calc_dss_cb, ctx); 288 if (ok) 289 return ok; 290 } 291 292 return false; 293 } 294 295 296 297 static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel, 298 unsigned long pck_req, unsigned long *fck, int *lck_div, 299 int *pck_div) 300 { 301 struct dpi_clk_calc_ctx ctx; 302 int r; 303 bool ok; 304 305 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); 306 if (!ok) 307 return -EINVAL; 308 309 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 310 if (r) 311 return r; 312 313 dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src); 314 315 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 316 317 *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 318 *lck_div = ctx.dispc_cinfo.lck_div; 319 *pck_div = ctx.dispc_cinfo.pck_div; 320 321 return 0; 322 } 323 324 static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req, 325 unsigned long *fck, int *lck_div, int *pck_div) 326 { 327 struct dpi_clk_calc_ctx ctx; 328 int r; 329 bool ok; 330 331 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx); 332 if (!ok) 333 return -EINVAL; 334 335 r = dss_set_fck_rate(dpi->dss, ctx.fck); 336 if (r) 337 return r; 338 339 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 340 341 *fck = ctx.fck; 342 *lck_div = ctx.dispc_cinfo.lck_div; 343 *pck_div = ctx.dispc_cinfo.pck_div; 344 345 return 0; 346 } 347 348 static int dpi_set_mode(struct dpi_data *dpi) 349 { 350 int lck_div = 0, pck_div = 0; 351 unsigned long fck = 0; 352 int r = 0; 353 354 if (dpi->pll) 355 r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel, 356 dpi->pixelclock, &fck, &lck_div, &pck_div); 357 else 358 r = dpi_set_dispc_clk(dpi, dpi->pixelclock, &fck, 359 &lck_div, &pck_div); 360 if (r) 361 return r; 362 363 return 0; 364 } 365 366 static void dpi_config_lcd_manager(struct dpi_data *dpi) 367 { 368 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 369 370 dpi->mgr_config.stallmode = false; 371 dpi->mgr_config.fifohandcheck = false; 372 373 dpi->mgr_config.video_port_width = dpi->data_lines; 374 375 dpi->mgr_config.lcden_sig_polarity = 0; 376 377 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config); 378 } 379 380 static void dpi_display_enable(struct omap_dss_device *dssdev) 381 { 382 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 383 struct omap_dss_device *out = &dpi->output; 384 int r; 385 386 mutex_lock(&dpi->lock); 387 388 if (dpi->vdds_dsi_reg) { 389 r = regulator_enable(dpi->vdds_dsi_reg); 390 if (r) 391 goto err_reg_enable; 392 } 393 394 r = dispc_runtime_get(dpi->dss->dispc); 395 if (r) 396 goto err_get_dispc; 397 398 r = dss_dpi_select_source(dpi->dss, dpi->id, out->dispc_channel); 399 if (r) 400 goto err_src_sel; 401 402 if (dpi->pll) { 403 r = dss_pll_enable(dpi->pll); 404 if (r) 405 goto err_pll_init; 406 } 407 408 r = dpi_set_mode(dpi); 409 if (r) 410 goto err_set_mode; 411 412 dpi_config_lcd_manager(dpi); 413 414 mdelay(2); 415 416 r = dss_mgr_enable(&dpi->output); 417 if (r) 418 goto err_mgr_enable; 419 420 mutex_unlock(&dpi->lock); 421 422 return; 423 424 err_mgr_enable: 425 err_set_mode: 426 if (dpi->pll) 427 dss_pll_disable(dpi->pll); 428 err_pll_init: 429 err_src_sel: 430 dispc_runtime_put(dpi->dss->dispc); 431 err_get_dispc: 432 if (dpi->vdds_dsi_reg) 433 regulator_disable(dpi->vdds_dsi_reg); 434 err_reg_enable: 435 mutex_unlock(&dpi->lock); 436 } 437 438 static void dpi_display_disable(struct omap_dss_device *dssdev) 439 { 440 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 441 442 mutex_lock(&dpi->lock); 443 444 dss_mgr_disable(&dpi->output); 445 446 if (dpi->pll) { 447 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel, 448 DSS_CLK_SRC_FCK); 449 dss_pll_disable(dpi->pll); 450 } 451 452 dispc_runtime_put(dpi->dss->dispc); 453 454 if (dpi->vdds_dsi_reg) 455 regulator_disable(dpi->vdds_dsi_reg); 456 457 mutex_unlock(&dpi->lock); 458 } 459 460 static void dpi_set_timings(struct omap_dss_device *dssdev, 461 const struct drm_display_mode *mode) 462 { 463 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 464 465 DSSDBG("dpi_set_timings\n"); 466 467 mutex_lock(&dpi->lock); 468 469 dpi->pixelclock = mode->clock * 1000; 470 471 mutex_unlock(&dpi->lock); 472 } 473 474 static int dpi_check_timings(struct omap_dss_device *dssdev, 475 struct drm_display_mode *mode) 476 { 477 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 478 int lck_div, pck_div; 479 unsigned long fck; 480 unsigned long pck; 481 struct dpi_clk_calc_ctx ctx; 482 bool ok; 483 484 if (mode->hdisplay % 8 != 0) 485 return -EINVAL; 486 487 if (mode->clock == 0) 488 return -EINVAL; 489 490 if (dpi->pll) { 491 ok = dpi_pll_clk_calc(dpi, mode->clock * 1000, &ctx); 492 if (!ok) 493 return -EINVAL; 494 495 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 496 } else { 497 ok = dpi_dss_clk_calc(dpi, mode->clock * 1000, &ctx); 498 if (!ok) 499 return -EINVAL; 500 501 fck = ctx.fck; 502 } 503 504 lck_div = ctx.dispc_cinfo.lck_div; 505 pck_div = ctx.dispc_cinfo.pck_div; 506 507 pck = fck / lck_div / pck_div; 508 509 mode->clock = pck / 1000; 510 511 return 0; 512 } 513 514 static int dpi_verify_pll(struct dss_pll *pll) 515 { 516 int r; 517 518 /* do initial setup with the PLL to see if it is operational */ 519 520 r = dss_pll_enable(pll); 521 if (r) 522 return r; 523 524 dss_pll_disable(pll); 525 526 return 0; 527 } 528 529 static void dpi_init_pll(struct dpi_data *dpi) 530 { 531 struct dss_pll *pll; 532 533 if (dpi->pll) 534 return; 535 536 dpi->clk_src = dpi_get_clk_src(dpi); 537 538 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src); 539 if (!pll) 540 return; 541 542 if (dpi_verify_pll(pll)) { 543 DSSWARN("PLL not operational\n"); 544 return; 545 } 546 547 dpi->pll = pll; 548 } 549 550 /* 551 * Return a hardcoded channel for the DPI output. This should work for 552 * current use cases, but this can be later expanded to either resolve 553 * the channel in some more dynamic manner, or get the channel as a user 554 * parameter. 555 */ 556 static enum omap_channel dpi_get_channel(struct dpi_data *dpi) 557 { 558 switch (dpi->dss_model) { 559 case DSS_MODEL_OMAP2: 560 case DSS_MODEL_OMAP3: 561 return OMAP_DSS_CHANNEL_LCD; 562 563 case DSS_MODEL_DRA7: 564 switch (dpi->id) { 565 case 2: 566 return OMAP_DSS_CHANNEL_LCD3; 567 case 1: 568 return OMAP_DSS_CHANNEL_LCD2; 569 case 0: 570 default: 571 return OMAP_DSS_CHANNEL_LCD; 572 } 573 574 case DSS_MODEL_OMAP4: 575 return OMAP_DSS_CHANNEL_LCD2; 576 577 case DSS_MODEL_OMAP5: 578 return OMAP_DSS_CHANNEL_LCD3; 579 580 default: 581 DSSWARN("unsupported DSS version\n"); 582 return OMAP_DSS_CHANNEL_LCD; 583 } 584 } 585 586 static int dpi_connect(struct omap_dss_device *src, 587 struct omap_dss_device *dst) 588 { 589 struct dpi_data *dpi = dpi_get_data_from_dssdev(dst); 590 591 dpi_init_pll(dpi); 592 593 return omapdss_device_connect(dst->dss, dst, dst->next); 594 } 595 596 static void dpi_disconnect(struct omap_dss_device *src, 597 struct omap_dss_device *dst) 598 { 599 omapdss_device_disconnect(dst, dst->next); 600 } 601 602 static const struct omap_dss_device_ops dpi_ops = { 603 .connect = dpi_connect, 604 .disconnect = dpi_disconnect, 605 606 .enable = dpi_display_enable, 607 .disable = dpi_display_disable, 608 609 .check_timings = dpi_check_timings, 610 .set_timings = dpi_set_timings, 611 }; 612 613 static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) 614 { 615 struct omap_dss_device *out = &dpi->output; 616 u32 port_num = 0; 617 int r; 618 619 of_property_read_u32(port, "reg", &port_num); 620 dpi->id = port_num <= 2 ? port_num : 0; 621 622 switch (port_num) { 623 case 2: 624 out->name = "dpi.2"; 625 break; 626 case 1: 627 out->name = "dpi.1"; 628 break; 629 case 0: 630 default: 631 out->name = "dpi.0"; 632 break; 633 } 634 635 out->dev = &dpi->pdev->dev; 636 out->id = OMAP_DSS_OUTPUT_DPI; 637 out->type = OMAP_DISPLAY_TYPE_DPI; 638 out->dispc_channel = dpi_get_channel(dpi); 639 out->of_ports = BIT(port_num); 640 out->ops = &dpi_ops; 641 out->owner = THIS_MODULE; 642 643 r = omapdss_device_init_output(out); 644 if (r < 0) 645 return r; 646 647 omapdss_device_register(out); 648 649 return 0; 650 } 651 652 static void dpi_uninit_output_port(struct device_node *port) 653 { 654 struct dpi_data *dpi = port->data; 655 struct omap_dss_device *out = &dpi->output; 656 657 omapdss_device_unregister(out); 658 omapdss_device_cleanup_output(out); 659 } 660 661 static const struct soc_device_attribute dpi_soc_devices[] = { 662 { .machine = "OMAP3[456]*" }, 663 { .machine = "[AD]M37*" }, 664 { /* sentinel */ } 665 }; 666 667 static int dpi_init_regulator(struct dpi_data *dpi) 668 { 669 struct regulator *vdds_dsi; 670 671 /* 672 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and 673 * DM37xx only. 674 */ 675 if (!soc_device_match(dpi_soc_devices)) 676 return 0; 677 678 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi"); 679 if (IS_ERR(vdds_dsi)) { 680 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 681 DSSERR("can't get VDDS_DSI regulator\n"); 682 return PTR_ERR(vdds_dsi); 683 } 684 685 dpi->vdds_dsi_reg = vdds_dsi; 686 687 return 0; 688 } 689 690 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 691 struct device_node *port, enum dss_model dss_model) 692 { 693 struct dpi_data *dpi; 694 struct device_node *ep; 695 u32 datalines; 696 int r; 697 698 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); 699 if (!dpi) 700 return -ENOMEM; 701 702 ep = of_get_next_child(port, NULL); 703 if (!ep) 704 return 0; 705 706 r = of_property_read_u32(ep, "data-lines", &datalines); 707 of_node_put(ep); 708 if (r) { 709 DSSERR("failed to parse datalines\n"); 710 return r; 711 } 712 713 dpi->data_lines = datalines; 714 715 dpi->pdev = pdev; 716 dpi->dss_model = dss_model; 717 dpi->dss = dss; 718 port->data = dpi; 719 720 mutex_init(&dpi->lock); 721 722 r = dpi_init_regulator(dpi); 723 if (r) 724 return r; 725 726 return dpi_init_output_port(dpi, port); 727 } 728 729 void dpi_uninit_port(struct device_node *port) 730 { 731 struct dpi_data *dpi = port->data; 732 733 if (!dpi) 734 return; 735 736 dpi_uninit_output_port(port); 737 } 738