xref: /openbmc/linux/drivers/gpu/drm/omapdrm/dss/dispc.h (revision 4da722ca)
1 /*
2  * linux/drivers/video/omap2/dss/dispc.h
3  *
4  * Copyright (C) 2011 Texas Instruments
5  * Author: Archit Taneja <archit@ti.com>
6  *
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License version 2 as published by
10  * the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef __OMAP2_DISPC_REG_H
22 #define __OMAP2_DISPC_REG_H
23 
24 /* DISPC common registers */
25 #define DISPC_REVISION			0x0000
26 #define DISPC_SYSCONFIG			0x0010
27 #define DISPC_SYSSTATUS			0x0014
28 #define DISPC_IRQSTATUS			0x0018
29 #define DISPC_IRQENABLE			0x001C
30 #define DISPC_CONTROL			0x0040
31 #define DISPC_CONFIG			0x0044
32 #define DISPC_CAPABLE			0x0048
33 #define DISPC_LINE_STATUS		0x005C
34 #define DISPC_LINE_NUMBER		0x0060
35 #define DISPC_GLOBAL_ALPHA		0x0074
36 #define DISPC_CONTROL2			0x0238
37 #define DISPC_CONFIG2			0x0620
38 #define DISPC_DIVISOR			0x0804
39 #define DISPC_GLOBAL_BUFFER		0x0800
40 #define DISPC_CONTROL3                  0x0848
41 #define DISPC_CONFIG3                   0x084C
42 #define DISPC_MSTANDBY_CTRL		0x0858
43 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE	0x085C
44 
45 #define DISPC_GAMMA_TABLE0		0x0630
46 #define DISPC_GAMMA_TABLE1		0x0634
47 #define DISPC_GAMMA_TABLE2		0x0638
48 #define DISPC_GAMMA_TABLE3		0x0850
49 
50 /* DISPC overlay registers */
51 #define DISPC_OVL_BA0(n)		(DISPC_OVL_BASE(n) + \
52 					DISPC_BA0_OFFSET(n))
53 #define DISPC_OVL_BA1(n)		(DISPC_OVL_BASE(n) + \
54 					DISPC_BA1_OFFSET(n))
55 #define DISPC_OVL_BA0_UV(n)		(DISPC_OVL_BASE(n) + \
56 					DISPC_BA0_UV_OFFSET(n))
57 #define DISPC_OVL_BA1_UV(n)		(DISPC_OVL_BASE(n) + \
58 					DISPC_BA1_UV_OFFSET(n))
59 #define DISPC_OVL_POSITION(n)		(DISPC_OVL_BASE(n) + \
60 					DISPC_POS_OFFSET(n))
61 #define DISPC_OVL_SIZE(n)		(DISPC_OVL_BASE(n) + \
62 					DISPC_SIZE_OFFSET(n))
63 #define DISPC_OVL_ATTRIBUTES(n)		(DISPC_OVL_BASE(n) + \
64 					DISPC_ATTR_OFFSET(n))
65 #define DISPC_OVL_ATTRIBUTES2(n)	(DISPC_OVL_BASE(n) + \
66 					DISPC_ATTR2_OFFSET(n))
67 #define DISPC_OVL_FIFO_THRESHOLD(n)	(DISPC_OVL_BASE(n) + \
68 					DISPC_FIFO_THRESH_OFFSET(n))
69 #define DISPC_OVL_FIFO_SIZE_STATUS(n)	(DISPC_OVL_BASE(n) + \
70 					DISPC_FIFO_SIZE_STATUS_OFFSET(n))
71 #define DISPC_OVL_ROW_INC(n)		(DISPC_OVL_BASE(n) + \
72 					DISPC_ROW_INC_OFFSET(n))
73 #define DISPC_OVL_PIXEL_INC(n)		(DISPC_OVL_BASE(n) + \
74 					DISPC_PIX_INC_OFFSET(n))
75 #define DISPC_OVL_WINDOW_SKIP(n)	(DISPC_OVL_BASE(n) + \
76 					DISPC_WINDOW_SKIP_OFFSET(n))
77 #define DISPC_OVL_TABLE_BA(n)		(DISPC_OVL_BASE(n) + \
78 					DISPC_TABLE_BA_OFFSET(n))
79 #define DISPC_OVL_FIR(n)		(DISPC_OVL_BASE(n) + \
80 					DISPC_FIR_OFFSET(n))
81 #define DISPC_OVL_FIR2(n)		(DISPC_OVL_BASE(n) + \
82 					DISPC_FIR2_OFFSET(n))
83 #define DISPC_OVL_PICTURE_SIZE(n)	(DISPC_OVL_BASE(n) + \
84 					DISPC_PIC_SIZE_OFFSET(n))
85 #define DISPC_OVL_ACCU0(n)		(DISPC_OVL_BASE(n) + \
86 					DISPC_ACCU0_OFFSET(n))
87 #define DISPC_OVL_ACCU1(n)		(DISPC_OVL_BASE(n) + \
88 					DISPC_ACCU1_OFFSET(n))
89 #define DISPC_OVL_ACCU2_0(n)		(DISPC_OVL_BASE(n) + \
90 					DISPC_ACCU2_0_OFFSET(n))
91 #define DISPC_OVL_ACCU2_1(n)		(DISPC_OVL_BASE(n) + \
92 					DISPC_ACCU2_1_OFFSET(n))
93 #define DISPC_OVL_FIR_COEF_H(n, i)	(DISPC_OVL_BASE(n) + \
94 					DISPC_FIR_COEF_H_OFFSET(n, i))
95 #define DISPC_OVL_FIR_COEF_HV(n, i)	(DISPC_OVL_BASE(n) + \
96 					DISPC_FIR_COEF_HV_OFFSET(n, i))
97 #define DISPC_OVL_FIR_COEF_H2(n, i)	(DISPC_OVL_BASE(n) + \
98 					DISPC_FIR_COEF_H2_OFFSET(n, i))
99 #define DISPC_OVL_FIR_COEF_HV2(n, i)	(DISPC_OVL_BASE(n) + \
100 					DISPC_FIR_COEF_HV2_OFFSET(n, i))
101 #define DISPC_OVL_CONV_COEF(n, i)	(DISPC_OVL_BASE(n) + \
102 					DISPC_CONV_COEF_OFFSET(n, i))
103 #define DISPC_OVL_FIR_COEF_V(n, i)	(DISPC_OVL_BASE(n) + \
104 					DISPC_FIR_COEF_V_OFFSET(n, i))
105 #define DISPC_OVL_FIR_COEF_V2(n, i)	(DISPC_OVL_BASE(n) + \
106 					DISPC_FIR_COEF_V2_OFFSET(n, i))
107 #define DISPC_OVL_PRELOAD(n)		(DISPC_OVL_BASE(n) + \
108 					DISPC_PRELOAD_OFFSET(n))
109 #define DISPC_OVL_MFLAG_THRESHOLD(n)	DISPC_MFLAG_THRESHOLD_OFFSET(n)
110 
111 /* DISPC up/downsampling FIR filter coefficient structure */
112 struct dispc_coef {
113 	s8 hc4_vc22;
114 	s8 hc3_vc2;
115 	u8 hc2_vc1;
116 	s8 hc1_vc0;
117 	s8 hc0_vc00;
118 };
119 
120 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
121 
122 /* DISPC manager/channel specific registers */
123 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
124 {
125 	switch (channel) {
126 	case OMAP_DSS_CHANNEL_LCD:
127 		return 0x004C;
128 	case OMAP_DSS_CHANNEL_DIGIT:
129 		return 0x0050;
130 	case OMAP_DSS_CHANNEL_LCD2:
131 		return 0x03AC;
132 	case OMAP_DSS_CHANNEL_LCD3:
133 		return 0x0814;
134 	default:
135 		BUG();
136 		return 0;
137 	}
138 }
139 
140 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
141 {
142 	switch (channel) {
143 	case OMAP_DSS_CHANNEL_LCD:
144 		return 0x0054;
145 	case OMAP_DSS_CHANNEL_DIGIT:
146 		return 0x0058;
147 	case OMAP_DSS_CHANNEL_LCD2:
148 		return 0x03B0;
149 	case OMAP_DSS_CHANNEL_LCD3:
150 		return 0x0818;
151 	default:
152 		BUG();
153 		return 0;
154 	}
155 }
156 
157 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
158 {
159 	switch (channel) {
160 	case OMAP_DSS_CHANNEL_LCD:
161 		return 0x0064;
162 	case OMAP_DSS_CHANNEL_DIGIT:
163 		BUG();
164 		return 0;
165 	case OMAP_DSS_CHANNEL_LCD2:
166 		return 0x0400;
167 	case OMAP_DSS_CHANNEL_LCD3:
168 		return 0x0840;
169 	default:
170 		BUG();
171 		return 0;
172 	}
173 }
174 
175 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
176 {
177 	switch (channel) {
178 	case OMAP_DSS_CHANNEL_LCD:
179 		return 0x0068;
180 	case OMAP_DSS_CHANNEL_DIGIT:
181 		BUG();
182 		return 0;
183 	case OMAP_DSS_CHANNEL_LCD2:
184 		return 0x0404;
185 	case OMAP_DSS_CHANNEL_LCD3:
186 		return 0x0844;
187 	default:
188 		BUG();
189 		return 0;
190 	}
191 }
192 
193 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
194 {
195 	switch (channel) {
196 	case OMAP_DSS_CHANNEL_LCD:
197 		return 0x006C;
198 	case OMAP_DSS_CHANNEL_DIGIT:
199 		BUG();
200 		return 0;
201 	case OMAP_DSS_CHANNEL_LCD2:
202 		return 0x0408;
203 	case OMAP_DSS_CHANNEL_LCD3:
204 		return 0x083C;
205 	default:
206 		BUG();
207 		return 0;
208 	}
209 }
210 
211 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
212 {
213 	switch (channel) {
214 	case OMAP_DSS_CHANNEL_LCD:
215 		return 0x0070;
216 	case OMAP_DSS_CHANNEL_DIGIT:
217 		BUG();
218 		return 0;
219 	case OMAP_DSS_CHANNEL_LCD2:
220 		return 0x040C;
221 	case OMAP_DSS_CHANNEL_LCD3:
222 		return 0x0838;
223 	default:
224 		BUG();
225 		return 0;
226 	}
227 }
228 
229 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
230 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
231 {
232 	switch (channel) {
233 	case OMAP_DSS_CHANNEL_LCD:
234 		return 0x007C;
235 	case OMAP_DSS_CHANNEL_DIGIT:
236 		return 0x0078;
237 	case OMAP_DSS_CHANNEL_LCD2:
238 		return 0x03CC;
239 	case OMAP_DSS_CHANNEL_LCD3:
240 		return 0x0834;
241 	default:
242 		BUG();
243 		return 0;
244 	}
245 }
246 
247 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
248 {
249 	switch (channel) {
250 	case OMAP_DSS_CHANNEL_LCD:
251 		return 0x01D4;
252 	case OMAP_DSS_CHANNEL_DIGIT:
253 		BUG();
254 		return 0;
255 	case OMAP_DSS_CHANNEL_LCD2:
256 		return 0x03C0;
257 	case OMAP_DSS_CHANNEL_LCD3:
258 		return 0x0828;
259 	default:
260 		BUG();
261 		return 0;
262 	}
263 }
264 
265 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
266 {
267 	switch (channel) {
268 	case OMAP_DSS_CHANNEL_LCD:
269 		return 0x01D8;
270 	case OMAP_DSS_CHANNEL_DIGIT:
271 		BUG();
272 		return 0;
273 	case OMAP_DSS_CHANNEL_LCD2:
274 		return 0x03C4;
275 	case OMAP_DSS_CHANNEL_LCD3:
276 		return 0x082C;
277 	default:
278 		BUG();
279 		return 0;
280 	}
281 }
282 
283 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
284 {
285 	switch (channel) {
286 	case OMAP_DSS_CHANNEL_LCD:
287 		return 0x01DC;
288 	case OMAP_DSS_CHANNEL_DIGIT:
289 		BUG();
290 		return 0;
291 	case OMAP_DSS_CHANNEL_LCD2:
292 		return 0x03C8;
293 	case OMAP_DSS_CHANNEL_LCD3:
294 		return 0x0830;
295 	default:
296 		BUG();
297 		return 0;
298 	}
299 }
300 
301 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
302 {
303 	switch (channel) {
304 	case OMAP_DSS_CHANNEL_LCD:
305 		return 0x0220;
306 	case OMAP_DSS_CHANNEL_DIGIT:
307 		BUG();
308 		return 0;
309 	case OMAP_DSS_CHANNEL_LCD2:
310 		return 0x03BC;
311 	case OMAP_DSS_CHANNEL_LCD3:
312 		return 0x0824;
313 	default:
314 		BUG();
315 		return 0;
316 	}
317 }
318 
319 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
320 {
321 	switch (channel) {
322 	case OMAP_DSS_CHANNEL_LCD:
323 		return 0x0224;
324 	case OMAP_DSS_CHANNEL_DIGIT:
325 		BUG();
326 		return 0;
327 	case OMAP_DSS_CHANNEL_LCD2:
328 		return 0x03B8;
329 	case OMAP_DSS_CHANNEL_LCD3:
330 		return 0x0820;
331 	default:
332 		BUG();
333 		return 0;
334 	}
335 }
336 
337 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
338 {
339 	switch (channel) {
340 	case OMAP_DSS_CHANNEL_LCD:
341 		return 0x0228;
342 	case OMAP_DSS_CHANNEL_DIGIT:
343 		BUG();
344 		return 0;
345 	case OMAP_DSS_CHANNEL_LCD2:
346 		return 0x03B4;
347 	case OMAP_DSS_CHANNEL_LCD3:
348 		return 0x081C;
349 	default:
350 		BUG();
351 		return 0;
352 	}
353 }
354 
355 /* DISPC overlay register base addresses */
356 static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
357 {
358 	switch (plane) {
359 	case OMAP_DSS_GFX:
360 		return 0x0080;
361 	case OMAP_DSS_VIDEO1:
362 		return 0x00BC;
363 	case OMAP_DSS_VIDEO2:
364 		return 0x014C;
365 	case OMAP_DSS_VIDEO3:
366 		return 0x0300;
367 	case OMAP_DSS_WB:
368 		return 0x0500;
369 	default:
370 		BUG();
371 		return 0;
372 	}
373 }
374 
375 /* DISPC overlay register offsets */
376 static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
377 {
378 	switch (plane) {
379 	case OMAP_DSS_GFX:
380 	case OMAP_DSS_VIDEO1:
381 	case OMAP_DSS_VIDEO2:
382 		return 0x0000;
383 	case OMAP_DSS_VIDEO3:
384 	case OMAP_DSS_WB:
385 		return 0x0008;
386 	default:
387 		BUG();
388 		return 0;
389 	}
390 }
391 
392 static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
393 {
394 	switch (plane) {
395 	case OMAP_DSS_GFX:
396 	case OMAP_DSS_VIDEO1:
397 	case OMAP_DSS_VIDEO2:
398 		return 0x0004;
399 	case OMAP_DSS_VIDEO3:
400 	case OMAP_DSS_WB:
401 		return 0x000C;
402 	default:
403 		BUG();
404 		return 0;
405 	}
406 }
407 
408 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
409 {
410 	switch (plane) {
411 	case OMAP_DSS_GFX:
412 		BUG();
413 		return 0;
414 	case OMAP_DSS_VIDEO1:
415 		return 0x0544;
416 	case OMAP_DSS_VIDEO2:
417 		return 0x04BC;
418 	case OMAP_DSS_VIDEO3:
419 		return 0x0310;
420 	case OMAP_DSS_WB:
421 		return 0x0118;
422 	default:
423 		BUG();
424 		return 0;
425 	}
426 }
427 
428 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
429 {
430 	switch (plane) {
431 	case OMAP_DSS_GFX:
432 		BUG();
433 		return 0;
434 	case OMAP_DSS_VIDEO1:
435 		return 0x0548;
436 	case OMAP_DSS_VIDEO2:
437 		return 0x04C0;
438 	case OMAP_DSS_VIDEO3:
439 		return 0x0314;
440 	case OMAP_DSS_WB:
441 		return 0x011C;
442 	default:
443 		BUG();
444 		return 0;
445 	}
446 }
447 
448 static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
449 {
450 	switch (plane) {
451 	case OMAP_DSS_GFX:
452 	case OMAP_DSS_VIDEO1:
453 	case OMAP_DSS_VIDEO2:
454 		return 0x0008;
455 	case OMAP_DSS_VIDEO3:
456 		return 0x009C;
457 	default:
458 		BUG();
459 		return 0;
460 	}
461 }
462 
463 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
464 {
465 	switch (plane) {
466 	case OMAP_DSS_GFX:
467 	case OMAP_DSS_VIDEO1:
468 	case OMAP_DSS_VIDEO2:
469 		return 0x000C;
470 	case OMAP_DSS_VIDEO3:
471 	case OMAP_DSS_WB:
472 		return 0x00A8;
473 	default:
474 		BUG();
475 		return 0;
476 	}
477 }
478 
479 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
480 {
481 	switch (plane) {
482 	case OMAP_DSS_GFX:
483 		return 0x0020;
484 	case OMAP_DSS_VIDEO1:
485 	case OMAP_DSS_VIDEO2:
486 		return 0x0010;
487 	case OMAP_DSS_VIDEO3:
488 	case OMAP_DSS_WB:
489 		return 0x0070;
490 	default:
491 		BUG();
492 		return 0;
493 	}
494 }
495 
496 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
497 {
498 	switch (plane) {
499 	case OMAP_DSS_GFX:
500 		BUG();
501 		return 0;
502 	case OMAP_DSS_VIDEO1:
503 		return 0x0568;
504 	case OMAP_DSS_VIDEO2:
505 		return 0x04DC;
506 	case OMAP_DSS_VIDEO3:
507 		return 0x032C;
508 	case OMAP_DSS_WB:
509 		return 0x0310;
510 	default:
511 		BUG();
512 		return 0;
513 	}
514 }
515 
516 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
517 {
518 	switch (plane) {
519 	case OMAP_DSS_GFX:
520 		return 0x0024;
521 	case OMAP_DSS_VIDEO1:
522 	case OMAP_DSS_VIDEO2:
523 		return 0x0014;
524 	case OMAP_DSS_VIDEO3:
525 	case OMAP_DSS_WB:
526 		return 0x008C;
527 	default:
528 		BUG();
529 		return 0;
530 	}
531 }
532 
533 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
534 {
535 	switch (plane) {
536 	case OMAP_DSS_GFX:
537 		return 0x0028;
538 	case OMAP_DSS_VIDEO1:
539 	case OMAP_DSS_VIDEO2:
540 		return 0x0018;
541 	case OMAP_DSS_VIDEO3:
542 	case OMAP_DSS_WB:
543 		return 0x0088;
544 	default:
545 		BUG();
546 		return 0;
547 	}
548 }
549 
550 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
551 {
552 	switch (plane) {
553 	case OMAP_DSS_GFX:
554 		return 0x002C;
555 	case OMAP_DSS_VIDEO1:
556 	case OMAP_DSS_VIDEO2:
557 		return 0x001C;
558 	case OMAP_DSS_VIDEO3:
559 	case OMAP_DSS_WB:
560 		return 0x00A4;
561 	default:
562 		BUG();
563 		return 0;
564 	}
565 }
566 
567 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
568 {
569 	switch (plane) {
570 	case OMAP_DSS_GFX:
571 		return 0x0030;
572 	case OMAP_DSS_VIDEO1:
573 	case OMAP_DSS_VIDEO2:
574 		return 0x0020;
575 	case OMAP_DSS_VIDEO3:
576 	case OMAP_DSS_WB:
577 		return 0x0098;
578 	default:
579 		BUG();
580 		return 0;
581 	}
582 }
583 
584 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
585 {
586 	switch (plane) {
587 	case OMAP_DSS_GFX:
588 		return 0x0034;
589 	case OMAP_DSS_VIDEO1:
590 	case OMAP_DSS_VIDEO2:
591 	case OMAP_DSS_VIDEO3:
592 		BUG();
593 		return 0;
594 	default:
595 		BUG();
596 		return 0;
597 	}
598 }
599 
600 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
601 {
602 	switch (plane) {
603 	case OMAP_DSS_GFX:
604 		return 0x0038;
605 	case OMAP_DSS_VIDEO1:
606 	case OMAP_DSS_VIDEO2:
607 	case OMAP_DSS_VIDEO3:
608 		BUG();
609 		return 0;
610 	default:
611 		BUG();
612 		return 0;
613 	}
614 }
615 
616 static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
617 {
618 	switch (plane) {
619 	case OMAP_DSS_GFX:
620 		BUG();
621 		return 0;
622 	case OMAP_DSS_VIDEO1:
623 	case OMAP_DSS_VIDEO2:
624 		return 0x0024;
625 	case OMAP_DSS_VIDEO3:
626 	case OMAP_DSS_WB:
627 		return 0x0090;
628 	default:
629 		BUG();
630 		return 0;
631 	}
632 }
633 
634 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
635 {
636 	switch (plane) {
637 	case OMAP_DSS_GFX:
638 		BUG();
639 		return 0;
640 	case OMAP_DSS_VIDEO1:
641 		return 0x0580;
642 	case OMAP_DSS_VIDEO2:
643 		return 0x055C;
644 	case OMAP_DSS_VIDEO3:
645 		return 0x0424;
646 	case OMAP_DSS_WB:
647 		return 0x290;
648 	default:
649 		BUG();
650 		return 0;
651 	}
652 }
653 
654 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
655 {
656 	switch (plane) {
657 	case OMAP_DSS_GFX:
658 		BUG();
659 		return 0;
660 	case OMAP_DSS_VIDEO1:
661 	case OMAP_DSS_VIDEO2:
662 		return 0x0028;
663 	case OMAP_DSS_VIDEO3:
664 	case OMAP_DSS_WB:
665 		return 0x0094;
666 	default:
667 		BUG();
668 		return 0;
669 	}
670 }
671 
672 
673 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
674 {
675 	switch (plane) {
676 	case OMAP_DSS_GFX:
677 		BUG();
678 		return 0;
679 	case OMAP_DSS_VIDEO1:
680 	case OMAP_DSS_VIDEO2:
681 		return 0x002C;
682 	case OMAP_DSS_VIDEO3:
683 	case OMAP_DSS_WB:
684 		return 0x0000;
685 	default:
686 		BUG();
687 		return 0;
688 	}
689 }
690 
691 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
692 {
693 	switch (plane) {
694 	case OMAP_DSS_GFX:
695 		BUG();
696 		return 0;
697 	case OMAP_DSS_VIDEO1:
698 		return 0x0584;
699 	case OMAP_DSS_VIDEO2:
700 		return 0x0560;
701 	case OMAP_DSS_VIDEO3:
702 		return 0x0428;
703 	case OMAP_DSS_WB:
704 		return 0x0294;
705 	default:
706 		BUG();
707 		return 0;
708 	}
709 }
710 
711 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
712 {
713 	switch (plane) {
714 	case OMAP_DSS_GFX:
715 		BUG();
716 		return 0;
717 	case OMAP_DSS_VIDEO1:
718 	case OMAP_DSS_VIDEO2:
719 		return 0x0030;
720 	case OMAP_DSS_VIDEO3:
721 	case OMAP_DSS_WB:
722 		return 0x0004;
723 	default:
724 		BUG();
725 		return 0;
726 	}
727 }
728 
729 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
730 {
731 	switch (plane) {
732 	case OMAP_DSS_GFX:
733 		BUG();
734 		return 0;
735 	case OMAP_DSS_VIDEO1:
736 		return 0x0588;
737 	case OMAP_DSS_VIDEO2:
738 		return 0x0564;
739 	case OMAP_DSS_VIDEO3:
740 		return 0x042C;
741 	case OMAP_DSS_WB:
742 		return 0x0298;
743 	default:
744 		BUG();
745 		return 0;
746 	}
747 }
748 
749 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
750 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
751 {
752 	switch (plane) {
753 	case OMAP_DSS_GFX:
754 		BUG();
755 		return 0;
756 	case OMAP_DSS_VIDEO1:
757 	case OMAP_DSS_VIDEO2:
758 		return 0x0034 + i * 0x8;
759 	case OMAP_DSS_VIDEO3:
760 	case OMAP_DSS_WB:
761 		return 0x0010 + i * 0x8;
762 	default:
763 		BUG();
764 		return 0;
765 	}
766 }
767 
768 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
769 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
770 {
771 	switch (plane) {
772 	case OMAP_DSS_GFX:
773 		BUG();
774 		return 0;
775 	case OMAP_DSS_VIDEO1:
776 		return 0x058C + i * 0x8;
777 	case OMAP_DSS_VIDEO2:
778 		return 0x0568 + i * 0x8;
779 	case OMAP_DSS_VIDEO3:
780 		return 0x0430 + i * 0x8;
781 	case OMAP_DSS_WB:
782 		return 0x02A0 + i * 0x8;
783 	default:
784 		BUG();
785 		return 0;
786 	}
787 }
788 
789 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
790 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
791 {
792 	switch (plane) {
793 	case OMAP_DSS_GFX:
794 		BUG();
795 		return 0;
796 	case OMAP_DSS_VIDEO1:
797 	case OMAP_DSS_VIDEO2:
798 		return 0x0038 + i * 0x8;
799 	case OMAP_DSS_VIDEO3:
800 	case OMAP_DSS_WB:
801 		return 0x0014 + i * 0x8;
802 	default:
803 		BUG();
804 		return 0;
805 	}
806 }
807 
808 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
809 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
810 {
811 	switch (plane) {
812 	case OMAP_DSS_GFX:
813 		BUG();
814 		return 0;
815 	case OMAP_DSS_VIDEO1:
816 		return 0x0590 + i * 8;
817 	case OMAP_DSS_VIDEO2:
818 		return 0x056C + i * 0x8;
819 	case OMAP_DSS_VIDEO3:
820 		return 0x0434 + i * 0x8;
821 	case OMAP_DSS_WB:
822 		return 0x02A4 + i * 0x8;
823 	default:
824 		BUG();
825 		return 0;
826 	}
827 }
828 
829 /* coef index i = {0, 1, 2, 3, 4,} */
830 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
831 {
832 	switch (plane) {
833 	case OMAP_DSS_GFX:
834 		BUG();
835 		return 0;
836 	case OMAP_DSS_VIDEO1:
837 	case OMAP_DSS_VIDEO2:
838 	case OMAP_DSS_VIDEO3:
839 	case OMAP_DSS_WB:
840 		return 0x0074 + i * 0x4;
841 	default:
842 		BUG();
843 		return 0;
844 	}
845 }
846 
847 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
848 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
849 {
850 	switch (plane) {
851 	case OMAP_DSS_GFX:
852 		BUG();
853 		return 0;
854 	case OMAP_DSS_VIDEO1:
855 		return 0x0124 + i * 0x4;
856 	case OMAP_DSS_VIDEO2:
857 		return 0x00B4 + i * 0x4;
858 	case OMAP_DSS_VIDEO3:
859 	case OMAP_DSS_WB:
860 		return 0x0050 + i * 0x4;
861 	default:
862 		BUG();
863 		return 0;
864 	}
865 }
866 
867 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
868 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
869 {
870 	switch (plane) {
871 	case OMAP_DSS_GFX:
872 		BUG();
873 		return 0;
874 	case OMAP_DSS_VIDEO1:
875 		return 0x05CC + i * 0x4;
876 	case OMAP_DSS_VIDEO2:
877 		return 0x05A8 + i * 0x4;
878 	case OMAP_DSS_VIDEO3:
879 		return 0x0470 + i * 0x4;
880 	case OMAP_DSS_WB:
881 		return 0x02E0 + i * 0x4;
882 	default:
883 		BUG();
884 		return 0;
885 	}
886 }
887 
888 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
889 {
890 	switch (plane) {
891 	case OMAP_DSS_GFX:
892 		return 0x01AC;
893 	case OMAP_DSS_VIDEO1:
894 		return 0x0174;
895 	case OMAP_DSS_VIDEO2:
896 		return 0x00E8;
897 	case OMAP_DSS_VIDEO3:
898 		return 0x00A0;
899 	default:
900 		BUG();
901 		return 0;
902 	}
903 }
904 
905 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
906 {
907 	switch (plane) {
908 	case OMAP_DSS_GFX:
909 		return 0x0860;
910 	case OMAP_DSS_VIDEO1:
911 		return 0x0864;
912 	case OMAP_DSS_VIDEO2:
913 		return 0x0868;
914 	case OMAP_DSS_VIDEO3:
915 		return 0x086c;
916 	case OMAP_DSS_WB:
917 		return 0x0870;
918 	default:
919 		BUG();
920 		return 0;
921 	}
922 }
923 #endif
924