1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 * 6 * Some code and ideas taken from drivers/video/omap/ driver 7 * by Imre Deak. 8 */ 9 10 #define DSS_SUBSYS_NAME "DISPC" 11 12 #include <linux/kernel.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/vmalloc.h> 15 #include <linux/export.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/jiffies.h> 19 #include <linux/seq_file.h> 20 #include <linux/delay.h> 21 #include <linux/workqueue.h> 22 #include <linux/hardirq.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/sizes.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/regmap.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/component.h> 31 #include <linux/sys_soc.h> 32 #include <drm/drm_fourcc.h> 33 #include <drm/drm_blend.h> 34 35 #include "omapdss.h" 36 #include "dss.h" 37 #include "dispc.h" 38 39 struct dispc_device; 40 41 /* DISPC */ 42 #define DISPC_SZ_REGS SZ_4K 43 44 enum omap_burst_size { 45 BURST_SIZE_X2 = 0, 46 BURST_SIZE_X4 = 1, 47 BURST_SIZE_X8 = 2, 48 }; 49 50 #define REG_GET(dispc, idx, start, end) \ 51 FLD_GET(dispc_read_reg(dispc, idx), start, end) 52 53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ 54 dispc_write_reg(dispc, idx, \ 55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end)) 56 57 /* DISPC has feature id */ 58 enum dispc_feature_id { 59 FEAT_LCDENABLEPOL, 60 FEAT_LCDENABLESIGNAL, 61 FEAT_PCKFREEENABLE, 62 FEAT_FUNCGATED, 63 FEAT_MGR_LCD2, 64 FEAT_MGR_LCD3, 65 FEAT_LINEBUFFERSPLIT, 66 FEAT_ROWREPEATENABLE, 67 FEAT_RESIZECONF, 68 /* Independent core clk divider */ 69 FEAT_CORE_CLK_DIV, 70 FEAT_HANDLE_UV_SEPARATE, 71 FEAT_ATTR2, 72 FEAT_CPR, 73 FEAT_PRELOAD, 74 FEAT_FIR_COEF_V, 75 FEAT_ALPHA_FIXED_ZORDER, 76 FEAT_ALPHA_FREE_ZORDER, 77 FEAT_FIFO_MERGE, 78 /* An unknown HW bug causing the normal FIFO thresholds not to work */ 79 FEAT_OMAP3_DSI_FIFO_BUG, 80 FEAT_BURST_2D, 81 FEAT_MFLAG, 82 }; 83 84 struct dispc_features { 85 u8 sw_start; 86 u8 fp_start; 87 u8 bp_start; 88 u16 sw_max; 89 u16 vp_max; 90 u16 hp_max; 91 u8 mgr_width_start; 92 u8 mgr_height_start; 93 u16 mgr_width_max; 94 u16 mgr_height_max; 95 unsigned long max_lcd_pclk; 96 unsigned long max_tv_pclk; 97 unsigned int max_downscale; 98 unsigned int max_line_width; 99 unsigned int min_pcd; 100 int (*calc_scaling)(struct dispc_device *dispc, 101 unsigned long pclk, unsigned long lclk, 102 const struct videomode *vm, 103 u16 width, u16 height, u16 out_width, u16 out_height, 104 u32 fourcc, bool *five_taps, 105 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 106 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 107 unsigned long (*calc_core_clk) (unsigned long pclk, 108 u16 width, u16 height, u16 out_width, u16 out_height, 109 bool mem_to_mem); 110 u8 num_fifos; 111 const enum dispc_feature_id *features; 112 unsigned int num_features; 113 const struct dss_reg_field *reg_fields; 114 const unsigned int num_reg_fields; 115 const enum omap_overlay_caps *overlay_caps; 116 const u32 **supported_color_modes; 117 const u32 *supported_scaler_color_modes; 118 unsigned int num_mgrs; 119 unsigned int num_ovls; 120 unsigned int buffer_size_unit; 121 unsigned int burst_size_unit; 122 123 /* swap GFX & WB fifos */ 124 bool gfx_fifo_workaround:1; 125 126 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 127 bool no_framedone_tv:1; 128 129 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 130 bool mstandby_workaround:1; 131 132 bool set_max_preload:1; 133 134 /* PIXEL_INC is not added to the last pixel of a line */ 135 bool last_pixel_inc_missing:1; 136 137 /* POL_FREQ has ALIGN bit */ 138 bool supports_sync_align:1; 139 140 bool has_writeback:1; 141 142 bool supports_double_pixel:1; 143 144 /* 145 * Field order for VENC is different than HDMI. We should handle this in 146 * some intelligent manner, but as the SoCs have either HDMI or VENC, 147 * never both, we can just use this flag for now. 148 */ 149 bool reverse_ilace_field_order:1; 150 151 bool has_gamma_table:1; 152 153 bool has_gamma_i734_bug:1; 154 }; 155 156 #define DISPC_MAX_NR_FIFOS 5 157 #define DISPC_MAX_CHANNEL_GAMMA 4 158 159 struct dispc_device { 160 struct platform_device *pdev; 161 void __iomem *base; 162 struct dss_device *dss; 163 164 struct dss_debugfs_entry *debugfs; 165 166 int irq; 167 irq_handler_t user_handler; 168 void *user_data; 169 170 unsigned long core_clk_rate; 171 unsigned long tv_pclk_rate; 172 173 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 174 /* maps which plane is using a fifo. fifo-id -> plane-id */ 175 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 176 177 bool ctx_valid; 178 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 179 180 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA]; 181 182 const struct dispc_features *feat; 183 184 bool is_enabled; 185 186 struct regmap *syscon_pol; 187 u32 syscon_pol_offset; 188 }; 189 190 enum omap_color_component { 191 /* used for all color formats for OMAP3 and earlier 192 * and for RGB and Y color component on OMAP4 193 */ 194 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 195 /* used for UV component for 196 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12 197 * color formats on OMAP4 198 */ 199 DISPC_COLOR_COMPONENT_UV = 1 << 1, 200 }; 201 202 enum mgr_reg_fields { 203 DISPC_MGR_FLD_ENABLE, 204 DISPC_MGR_FLD_STNTFT, 205 DISPC_MGR_FLD_GO, 206 DISPC_MGR_FLD_TFTDATALINES, 207 DISPC_MGR_FLD_STALLMODE, 208 DISPC_MGR_FLD_TCKENABLE, 209 DISPC_MGR_FLD_TCKSELECTION, 210 DISPC_MGR_FLD_CPR, 211 DISPC_MGR_FLD_FIFOHANDCHECK, 212 /* used to maintain a count of the above fields */ 213 DISPC_MGR_FLD_NUM, 214 }; 215 216 /* DISPC register field id */ 217 enum dispc_feat_reg_field { 218 FEAT_REG_FIRHINC, 219 FEAT_REG_FIRVINC, 220 FEAT_REG_FIFOHIGHTHRESHOLD, 221 FEAT_REG_FIFOLOWTHRESHOLD, 222 FEAT_REG_FIFOSIZE, 223 FEAT_REG_HORIZONTALACCU, 224 FEAT_REG_VERTICALACCU, 225 }; 226 227 struct dispc_reg_field { 228 u16 reg; 229 u8 high; 230 u8 low; 231 }; 232 233 struct dispc_gamma_desc { 234 u32 len; 235 u32 bits; 236 u16 reg; 237 bool has_index; 238 }; 239 240 static const struct { 241 const char *name; 242 u32 vsync_irq; 243 u32 framedone_irq; 244 u32 sync_lost_irq; 245 struct dispc_gamma_desc gamma; 246 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 247 } mgr_desc[] = { 248 [OMAP_DSS_CHANNEL_LCD] = { 249 .name = "LCD", 250 .vsync_irq = DISPC_IRQ_VSYNC, 251 .framedone_irq = DISPC_IRQ_FRAMEDONE, 252 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 253 .gamma = { 254 .len = 256, 255 .bits = 8, 256 .reg = DISPC_GAMMA_TABLE0, 257 .has_index = true, 258 }, 259 .reg_desc = { 260 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 261 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 262 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 263 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 264 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 265 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 266 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 267 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 268 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 269 }, 270 }, 271 [OMAP_DSS_CHANNEL_DIGIT] = { 272 .name = "DIGIT", 273 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 274 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 275 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 276 .gamma = { 277 .len = 1024, 278 .bits = 10, 279 .reg = DISPC_GAMMA_TABLE2, 280 .has_index = false, 281 }, 282 .reg_desc = { 283 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 284 [DISPC_MGR_FLD_STNTFT] = { }, 285 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 286 [DISPC_MGR_FLD_TFTDATALINES] = { }, 287 [DISPC_MGR_FLD_STALLMODE] = { }, 288 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 289 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 290 [DISPC_MGR_FLD_CPR] = { }, 291 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 292 }, 293 }, 294 [OMAP_DSS_CHANNEL_LCD2] = { 295 .name = "LCD2", 296 .vsync_irq = DISPC_IRQ_VSYNC2, 297 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 298 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 299 .gamma = { 300 .len = 256, 301 .bits = 8, 302 .reg = DISPC_GAMMA_TABLE1, 303 .has_index = true, 304 }, 305 .reg_desc = { 306 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 307 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 308 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 309 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 310 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 311 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 312 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 313 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 314 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 315 }, 316 }, 317 [OMAP_DSS_CHANNEL_LCD3] = { 318 .name = "LCD3", 319 .vsync_irq = DISPC_IRQ_VSYNC3, 320 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 321 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 322 .gamma = { 323 .len = 256, 324 .bits = 8, 325 .reg = DISPC_GAMMA_TABLE3, 326 .has_index = true, 327 }, 328 .reg_desc = { 329 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 330 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 331 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 332 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 333 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 334 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 335 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 336 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 337 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 338 }, 339 }, 340 }; 341 342 static unsigned long dispc_fclk_rate(struct dispc_device *dispc); 343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc); 344 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, 345 enum omap_channel channel); 346 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, 347 enum omap_channel channel); 348 349 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, 350 enum omap_plane_id plane); 351 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, 352 enum omap_plane_id plane); 353 354 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask); 355 356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) 357 { 358 __raw_writel(val, dispc->base + idx); 359 } 360 361 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) 362 { 363 return __raw_readl(dispc->base + idx); 364 } 365 366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, 367 enum mgr_reg_fields regfld) 368 { 369 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld]; 370 371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); 372 } 373 374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, 375 enum mgr_reg_fields regfld, int val) 376 { 377 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld]; 378 379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); 380 } 381 382 static int dispc_get_num_ovls(struct dispc_device *dispc) 383 { 384 return dispc->feat->num_ovls; 385 } 386 387 static int dispc_get_num_mgrs(struct dispc_device *dispc) 388 { 389 return dispc->feat->num_mgrs; 390 } 391 392 static void dispc_get_reg_field(struct dispc_device *dispc, 393 enum dispc_feat_reg_field id, 394 u8 *start, u8 *end) 395 { 396 if (id >= dispc->feat->num_reg_fields) 397 BUG(); 398 399 *start = dispc->feat->reg_fields[id].start; 400 *end = dispc->feat->reg_fields[id].end; 401 } 402 403 static bool dispc_has_feature(struct dispc_device *dispc, 404 enum dispc_feature_id id) 405 { 406 unsigned int i; 407 408 for (i = 0; i < dispc->feat->num_features; i++) { 409 if (dispc->feat->features[i] == id) 410 return true; 411 } 412 413 return false; 414 } 415 416 #define SR(dispc, reg) \ 417 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg) 418 #define RR(dispc, reg) \ 419 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)]) 420 421 static void dispc_save_context(struct dispc_device *dispc) 422 { 423 int i, j; 424 425 DSSDBG("dispc_save_context\n"); 426 427 SR(dispc, IRQENABLE); 428 SR(dispc, CONTROL); 429 SR(dispc, CONFIG); 430 SR(dispc, LINE_NUMBER); 431 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 432 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 433 SR(dispc, GLOBAL_ALPHA); 434 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 435 SR(dispc, CONTROL2); 436 SR(dispc, CONFIG2); 437 } 438 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 439 SR(dispc, CONTROL3); 440 SR(dispc, CONFIG3); 441 } 442 443 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 444 SR(dispc, DEFAULT_COLOR(i)); 445 SR(dispc, TRANS_COLOR(i)); 446 SR(dispc, SIZE_MGR(i)); 447 if (i == OMAP_DSS_CHANNEL_DIGIT) 448 continue; 449 SR(dispc, TIMING_H(i)); 450 SR(dispc, TIMING_V(i)); 451 SR(dispc, POL_FREQ(i)); 452 SR(dispc, DIVISORo(i)); 453 454 SR(dispc, DATA_CYCLE1(i)); 455 SR(dispc, DATA_CYCLE2(i)); 456 SR(dispc, DATA_CYCLE3(i)); 457 458 if (dispc_has_feature(dispc, FEAT_CPR)) { 459 SR(dispc, CPR_COEF_R(i)); 460 SR(dispc, CPR_COEF_G(i)); 461 SR(dispc, CPR_COEF_B(i)); 462 } 463 } 464 465 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 466 SR(dispc, OVL_BA0(i)); 467 SR(dispc, OVL_BA1(i)); 468 SR(dispc, OVL_POSITION(i)); 469 SR(dispc, OVL_SIZE(i)); 470 SR(dispc, OVL_ATTRIBUTES(i)); 471 SR(dispc, OVL_FIFO_THRESHOLD(i)); 472 SR(dispc, OVL_ROW_INC(i)); 473 SR(dispc, OVL_PIXEL_INC(i)); 474 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 475 SR(dispc, OVL_PRELOAD(i)); 476 if (i == OMAP_DSS_GFX) { 477 SR(dispc, OVL_WINDOW_SKIP(i)); 478 SR(dispc, OVL_TABLE_BA(i)); 479 continue; 480 } 481 SR(dispc, OVL_FIR(i)); 482 SR(dispc, OVL_PICTURE_SIZE(i)); 483 SR(dispc, OVL_ACCU0(i)); 484 SR(dispc, OVL_ACCU1(i)); 485 486 for (j = 0; j < 8; j++) 487 SR(dispc, OVL_FIR_COEF_H(i, j)); 488 489 for (j = 0; j < 8; j++) 490 SR(dispc, OVL_FIR_COEF_HV(i, j)); 491 492 for (j = 0; j < 5; j++) 493 SR(dispc, OVL_CONV_COEF(i, j)); 494 495 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 496 for (j = 0; j < 8; j++) 497 SR(dispc, OVL_FIR_COEF_V(i, j)); 498 } 499 500 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 501 SR(dispc, OVL_BA0_UV(i)); 502 SR(dispc, OVL_BA1_UV(i)); 503 SR(dispc, OVL_FIR2(i)); 504 SR(dispc, OVL_ACCU2_0(i)); 505 SR(dispc, OVL_ACCU2_1(i)); 506 507 for (j = 0; j < 8; j++) 508 SR(dispc, OVL_FIR_COEF_H2(i, j)); 509 510 for (j = 0; j < 8; j++) 511 SR(dispc, OVL_FIR_COEF_HV2(i, j)); 512 513 for (j = 0; j < 8; j++) 514 SR(dispc, OVL_FIR_COEF_V2(i, j)); 515 } 516 if (dispc_has_feature(dispc, FEAT_ATTR2)) 517 SR(dispc, OVL_ATTRIBUTES2(i)); 518 } 519 520 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 521 SR(dispc, DIVISOR); 522 523 dispc->ctx_valid = true; 524 525 DSSDBG("context saved\n"); 526 } 527 528 static void dispc_restore_context(struct dispc_device *dispc) 529 { 530 int i, j; 531 532 DSSDBG("dispc_restore_context\n"); 533 534 if (!dispc->ctx_valid) 535 return; 536 537 /*RR(dispc, IRQENABLE);*/ 538 /*RR(dispc, CONTROL);*/ 539 RR(dispc, CONFIG); 540 RR(dispc, LINE_NUMBER); 541 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 542 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 543 RR(dispc, GLOBAL_ALPHA); 544 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 545 RR(dispc, CONFIG2); 546 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 547 RR(dispc, CONFIG3); 548 549 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 550 RR(dispc, DEFAULT_COLOR(i)); 551 RR(dispc, TRANS_COLOR(i)); 552 RR(dispc, SIZE_MGR(i)); 553 if (i == OMAP_DSS_CHANNEL_DIGIT) 554 continue; 555 RR(dispc, TIMING_H(i)); 556 RR(dispc, TIMING_V(i)); 557 RR(dispc, POL_FREQ(i)); 558 RR(dispc, DIVISORo(i)); 559 560 RR(dispc, DATA_CYCLE1(i)); 561 RR(dispc, DATA_CYCLE2(i)); 562 RR(dispc, DATA_CYCLE3(i)); 563 564 if (dispc_has_feature(dispc, FEAT_CPR)) { 565 RR(dispc, CPR_COEF_R(i)); 566 RR(dispc, CPR_COEF_G(i)); 567 RR(dispc, CPR_COEF_B(i)); 568 } 569 } 570 571 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 572 RR(dispc, OVL_BA0(i)); 573 RR(dispc, OVL_BA1(i)); 574 RR(dispc, OVL_POSITION(i)); 575 RR(dispc, OVL_SIZE(i)); 576 RR(dispc, OVL_ATTRIBUTES(i)); 577 RR(dispc, OVL_FIFO_THRESHOLD(i)); 578 RR(dispc, OVL_ROW_INC(i)); 579 RR(dispc, OVL_PIXEL_INC(i)); 580 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 581 RR(dispc, OVL_PRELOAD(i)); 582 if (i == OMAP_DSS_GFX) { 583 RR(dispc, OVL_WINDOW_SKIP(i)); 584 RR(dispc, OVL_TABLE_BA(i)); 585 continue; 586 } 587 RR(dispc, OVL_FIR(i)); 588 RR(dispc, OVL_PICTURE_SIZE(i)); 589 RR(dispc, OVL_ACCU0(i)); 590 RR(dispc, OVL_ACCU1(i)); 591 592 for (j = 0; j < 8; j++) 593 RR(dispc, OVL_FIR_COEF_H(i, j)); 594 595 for (j = 0; j < 8; j++) 596 RR(dispc, OVL_FIR_COEF_HV(i, j)); 597 598 for (j = 0; j < 5; j++) 599 RR(dispc, OVL_CONV_COEF(i, j)); 600 601 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 602 for (j = 0; j < 8; j++) 603 RR(dispc, OVL_FIR_COEF_V(i, j)); 604 } 605 606 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 607 RR(dispc, OVL_BA0_UV(i)); 608 RR(dispc, OVL_BA1_UV(i)); 609 RR(dispc, OVL_FIR2(i)); 610 RR(dispc, OVL_ACCU2_0(i)); 611 RR(dispc, OVL_ACCU2_1(i)); 612 613 for (j = 0; j < 8; j++) 614 RR(dispc, OVL_FIR_COEF_H2(i, j)); 615 616 for (j = 0; j < 8; j++) 617 RR(dispc, OVL_FIR_COEF_HV2(i, j)); 618 619 for (j = 0; j < 8; j++) 620 RR(dispc, OVL_FIR_COEF_V2(i, j)); 621 } 622 if (dispc_has_feature(dispc, FEAT_ATTR2)) 623 RR(dispc, OVL_ATTRIBUTES2(i)); 624 } 625 626 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 627 RR(dispc, DIVISOR); 628 629 /* enable last, because LCD & DIGIT enable are here */ 630 RR(dispc, CONTROL); 631 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 632 RR(dispc, CONTROL2); 633 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 634 RR(dispc, CONTROL3); 635 /* clear spurious SYNC_LOST_DIGIT interrupts */ 636 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); 637 638 /* 639 * enable last so IRQs won't trigger before 640 * the context is fully restored 641 */ 642 RR(dispc, IRQENABLE); 643 644 DSSDBG("context restored\n"); 645 } 646 647 #undef SR 648 #undef RR 649 650 int dispc_runtime_get(struct dispc_device *dispc) 651 { 652 int r; 653 654 DSSDBG("dispc_runtime_get\n"); 655 656 r = pm_runtime_get_sync(&dispc->pdev->dev); 657 WARN_ON(r < 0); 658 return r < 0 ? r : 0; 659 } 660 661 void dispc_runtime_put(struct dispc_device *dispc) 662 { 663 int r; 664 665 DSSDBG("dispc_runtime_put\n"); 666 667 r = pm_runtime_put_sync(&dispc->pdev->dev); 668 WARN_ON(r < 0 && r != -ENOSYS); 669 } 670 671 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, 672 enum omap_channel channel) 673 { 674 return mgr_desc[channel].vsync_irq; 675 } 676 677 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, 678 enum omap_channel channel) 679 { 680 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) 681 return 0; 682 683 return mgr_desc[channel].framedone_irq; 684 } 685 686 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, 687 enum omap_channel channel) 688 { 689 return mgr_desc[channel].sync_lost_irq; 690 } 691 692 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) 693 { 694 return DISPC_IRQ_FRAMEDONEWB; 695 } 696 697 static void dispc_mgr_enable(struct dispc_device *dispc, 698 enum omap_channel channel, bool enable) 699 { 700 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); 701 /* flush posted write */ 702 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); 703 } 704 705 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, 706 enum omap_channel channel) 707 { 708 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); 709 } 710 711 static bool dispc_mgr_go_busy(struct dispc_device *dispc, 712 enum omap_channel channel) 713 { 714 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; 715 } 716 717 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) 718 { 719 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); 720 WARN_ON(dispc_mgr_go_busy(dispc, channel)); 721 722 DSSDBG("GO %s\n", mgr_desc[channel].name); 723 724 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); 725 } 726 727 static bool dispc_wb_go_busy(struct dispc_device *dispc) 728 { 729 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; 730 } 731 732 static void dispc_wb_go(struct dispc_device *dispc) 733 { 734 enum omap_plane_id plane = OMAP_DSS_WB; 735 bool enable, go; 736 737 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 738 739 if (!enable) 740 return; 741 742 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; 743 if (go) { 744 DSSERR("GO bit not down for WB\n"); 745 return; 746 } 747 748 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); 749 } 750 751 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, 752 enum omap_plane_id plane, int reg, 753 u32 value) 754 { 755 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); 756 } 757 758 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, 759 enum omap_plane_id plane, int reg, 760 u32 value) 761 { 762 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); 763 } 764 765 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, 766 enum omap_plane_id plane, int reg, 767 u32 value) 768 { 769 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); 770 } 771 772 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, 773 enum omap_plane_id plane, int reg, 774 u32 value) 775 { 776 BUG_ON(plane == OMAP_DSS_GFX); 777 778 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); 779 } 780 781 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, 782 enum omap_plane_id plane, int reg, 783 u32 value) 784 { 785 BUG_ON(plane == OMAP_DSS_GFX); 786 787 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 788 } 789 790 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, 791 enum omap_plane_id plane, int reg, 792 u32 value) 793 { 794 BUG_ON(plane == OMAP_DSS_GFX); 795 796 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); 797 } 798 799 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, 800 enum omap_plane_id plane, int fir_hinc, 801 int fir_vinc, int five_taps, 802 enum omap_color_component color_comp) 803 { 804 const struct dispc_coef *h_coef, *v_coef; 805 int i; 806 807 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 808 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 809 810 if (!h_coef || !v_coef) { 811 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", 812 __func__); 813 return; 814 } 815 816 for (i = 0; i < 8; i++) { 817 u32 h, hv; 818 819 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 820 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 821 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 822 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 823 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 824 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 825 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 826 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 827 828 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 829 dispc_ovl_write_firh_reg(dispc, plane, i, h); 830 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); 831 } else { 832 dispc_ovl_write_firh2_reg(dispc, plane, i, h); 833 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); 834 } 835 836 } 837 838 if (five_taps) { 839 for (i = 0; i < 8; i++) { 840 u32 v; 841 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 842 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 843 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 844 dispc_ovl_write_firv_reg(dispc, plane, i, v); 845 else 846 dispc_ovl_write_firv2_reg(dispc, plane, i, v); 847 } 848 } 849 } 850 851 struct csc_coef_yuv2rgb { 852 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr; 853 bool full_range; 854 }; 855 856 struct csc_coef_rgb2yuv { 857 int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb; 858 bool full_range; 859 }; 860 861 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, 862 enum omap_plane_id plane, 863 const struct csc_coef_yuv2rgb *ct) 864 { 865 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 866 867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 871 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 872 873 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 874 875 #undef CVAL 876 } 877 878 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc, 879 const struct csc_coef_rgb2yuv *ct) 880 { 881 const enum omap_plane_id plane = OMAP_DSS_WB; 882 883 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 884 885 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); 886 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); 887 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); 888 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); 889 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); 890 891 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 892 893 #undef CVAL 894 } 895 896 static void dispc_setup_color_conv_coef(struct dispc_device *dispc) 897 { 898 int i; 899 int num_ovl = dispc_get_num_ovls(dispc); 900 901 /* YUV -> RGB, ITU-R BT.601, limited range */ 902 const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = { 903 298, 0, 409, /* ry, rcb, rcr */ 904 298, -100, -208, /* gy, gcb, gcr */ 905 298, 516, 0, /* by, bcb, bcr */ 906 false, /* limited range */ 907 }; 908 909 /* RGB -> YUV, ITU-R BT.601, limited range */ 910 const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = { 911 66, 129, 25, /* yr, yg, yb */ 912 -38, -74, 112, /* cbr, cbg, cbb */ 913 112, -94, -18, /* crr, crg, crb */ 914 false, /* limited range */ 915 }; 916 917 for (i = 1; i < num_ovl; i++) 918 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim); 919 920 if (dispc->feat->has_writeback) 921 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim); 922 } 923 924 static void dispc_ovl_set_ba0(struct dispc_device *dispc, 925 enum omap_plane_id plane, u32 paddr) 926 { 927 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); 928 } 929 930 static void dispc_ovl_set_ba1(struct dispc_device *dispc, 931 enum omap_plane_id plane, u32 paddr) 932 { 933 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); 934 } 935 936 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, 937 enum omap_plane_id plane, u32 paddr) 938 { 939 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); 940 } 941 942 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, 943 enum omap_plane_id plane, u32 paddr) 944 { 945 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); 946 } 947 948 static void dispc_ovl_set_pos(struct dispc_device *dispc, 949 enum omap_plane_id plane, 950 enum omap_overlay_caps caps, int x, int y) 951 { 952 u32 val; 953 954 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 955 return; 956 957 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 958 959 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); 960 } 961 962 static void dispc_ovl_set_input_size(struct dispc_device *dispc, 963 enum omap_plane_id plane, int width, 964 int height) 965 { 966 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 967 968 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 969 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); 970 else 971 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); 972 } 973 974 static void dispc_ovl_set_output_size(struct dispc_device *dispc, 975 enum omap_plane_id plane, int width, 976 int height) 977 { 978 u32 val; 979 980 BUG_ON(plane == OMAP_DSS_GFX); 981 982 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 983 984 if (plane == OMAP_DSS_WB) 985 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); 986 else 987 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); 988 } 989 990 static void dispc_ovl_set_zorder(struct dispc_device *dispc, 991 enum omap_plane_id plane, 992 enum omap_overlay_caps caps, u8 zorder) 993 { 994 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 995 return; 996 997 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 998 } 999 1000 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) 1001 { 1002 int i; 1003 1004 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 1005 return; 1006 1007 for (i = 0; i < dispc_get_num_ovls(dispc); i++) 1008 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 1009 } 1010 1011 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, 1012 enum omap_plane_id plane, 1013 enum omap_overlay_caps caps, 1014 bool enable) 1015 { 1016 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 1017 return; 1018 1019 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 1020 } 1021 1022 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, 1023 enum omap_plane_id plane, 1024 enum omap_overlay_caps caps, 1025 u8 global_alpha) 1026 { 1027 static const unsigned int shifts[] = { 0, 8, 16, 24, }; 1028 int shift; 1029 1030 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 1031 return; 1032 1033 shift = shifts[plane]; 1034 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 1035 } 1036 1037 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, 1038 enum omap_plane_id plane, s32 inc) 1039 { 1040 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); 1041 } 1042 1043 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, 1044 enum omap_plane_id plane, s32 inc) 1045 { 1046 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); 1047 } 1048 1049 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, 1050 enum omap_plane_id plane, u32 fourcc) 1051 { 1052 u32 m = 0; 1053 if (plane != OMAP_DSS_GFX) { 1054 switch (fourcc) { 1055 case DRM_FORMAT_NV12: 1056 m = 0x0; break; 1057 case DRM_FORMAT_XRGB4444: 1058 m = 0x1; break; 1059 case DRM_FORMAT_RGBA4444: 1060 m = 0x2; break; 1061 case DRM_FORMAT_RGBX4444: 1062 m = 0x4; break; 1063 case DRM_FORMAT_ARGB4444: 1064 m = 0x5; break; 1065 case DRM_FORMAT_RGB565: 1066 m = 0x6; break; 1067 case DRM_FORMAT_ARGB1555: 1068 m = 0x7; break; 1069 case DRM_FORMAT_XRGB8888: 1070 m = 0x8; break; 1071 case DRM_FORMAT_RGB888: 1072 m = 0x9; break; 1073 case DRM_FORMAT_YUYV: 1074 m = 0xa; break; 1075 case DRM_FORMAT_UYVY: 1076 m = 0xb; break; 1077 case DRM_FORMAT_ARGB8888: 1078 m = 0xc; break; 1079 case DRM_FORMAT_RGBA8888: 1080 m = 0xd; break; 1081 case DRM_FORMAT_RGBX8888: 1082 m = 0xe; break; 1083 case DRM_FORMAT_XRGB1555: 1084 m = 0xf; break; 1085 default: 1086 BUG(); return; 1087 } 1088 } else { 1089 switch (fourcc) { 1090 case DRM_FORMAT_RGBX4444: 1091 m = 0x4; break; 1092 case DRM_FORMAT_ARGB4444: 1093 m = 0x5; break; 1094 case DRM_FORMAT_RGB565: 1095 m = 0x6; break; 1096 case DRM_FORMAT_ARGB1555: 1097 m = 0x7; break; 1098 case DRM_FORMAT_XRGB8888: 1099 m = 0x8; break; 1100 case DRM_FORMAT_RGB888: 1101 m = 0x9; break; 1102 case DRM_FORMAT_XRGB4444: 1103 m = 0xa; break; 1104 case DRM_FORMAT_RGBA4444: 1105 m = 0xb; break; 1106 case DRM_FORMAT_ARGB8888: 1107 m = 0xc; break; 1108 case DRM_FORMAT_RGBA8888: 1109 m = 0xd; break; 1110 case DRM_FORMAT_RGBX8888: 1111 m = 0xe; break; 1112 case DRM_FORMAT_XRGB1555: 1113 m = 0xf; break; 1114 default: 1115 BUG(); return; 1116 } 1117 } 1118 1119 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 1120 } 1121 1122 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, 1123 enum omap_plane_id plane, 1124 enum omap_dss_rotation_type rotation) 1125 { 1126 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) 1127 return; 1128 1129 if (rotation == OMAP_DSS_ROT_TILER) 1130 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 1131 else 1132 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 1133 } 1134 1135 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, 1136 enum omap_plane_id plane, 1137 enum omap_channel channel) 1138 { 1139 int shift; 1140 u32 val; 1141 int chan = 0, chan2 = 0; 1142 1143 switch (plane) { 1144 case OMAP_DSS_GFX: 1145 shift = 8; 1146 break; 1147 case OMAP_DSS_VIDEO1: 1148 case OMAP_DSS_VIDEO2: 1149 case OMAP_DSS_VIDEO3: 1150 shift = 16; 1151 break; 1152 default: 1153 BUG(); 1154 return; 1155 } 1156 1157 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1158 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 1159 switch (channel) { 1160 case OMAP_DSS_CHANNEL_LCD: 1161 chan = 0; 1162 chan2 = 0; 1163 break; 1164 case OMAP_DSS_CHANNEL_DIGIT: 1165 chan = 1; 1166 chan2 = 0; 1167 break; 1168 case OMAP_DSS_CHANNEL_LCD2: 1169 chan = 0; 1170 chan2 = 1; 1171 break; 1172 case OMAP_DSS_CHANNEL_LCD3: 1173 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 1174 chan = 0; 1175 chan2 = 2; 1176 } else { 1177 BUG(); 1178 return; 1179 } 1180 break; 1181 case OMAP_DSS_CHANNEL_WB: 1182 chan = 0; 1183 chan2 = 3; 1184 break; 1185 default: 1186 BUG(); 1187 return; 1188 } 1189 1190 val = FLD_MOD(val, chan, shift, shift); 1191 val = FLD_MOD(val, chan2, 31, 30); 1192 } else { 1193 val = FLD_MOD(val, channel, shift, shift); 1194 } 1195 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); 1196 } 1197 1198 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, 1199 enum omap_plane_id plane) 1200 { 1201 int shift; 1202 u32 val; 1203 1204 switch (plane) { 1205 case OMAP_DSS_GFX: 1206 shift = 8; 1207 break; 1208 case OMAP_DSS_VIDEO1: 1209 case OMAP_DSS_VIDEO2: 1210 case OMAP_DSS_VIDEO3: 1211 shift = 16; 1212 break; 1213 default: 1214 BUG(); 1215 return 0; 1216 } 1217 1218 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1219 1220 if (FLD_GET(val, shift, shift) == 1) 1221 return OMAP_DSS_CHANNEL_DIGIT; 1222 1223 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) 1224 return OMAP_DSS_CHANNEL_LCD; 1225 1226 switch (FLD_GET(val, 31, 30)) { 1227 case 0: 1228 default: 1229 return OMAP_DSS_CHANNEL_LCD; 1230 case 1: 1231 return OMAP_DSS_CHANNEL_LCD2; 1232 case 2: 1233 return OMAP_DSS_CHANNEL_LCD3; 1234 case 3: 1235 return OMAP_DSS_CHANNEL_WB; 1236 } 1237 } 1238 1239 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, 1240 enum omap_plane_id plane, 1241 enum omap_burst_size burst_size) 1242 { 1243 static const unsigned int shifts[] = { 6, 14, 14, 14, 14, }; 1244 int shift; 1245 1246 shift = shifts[plane]; 1247 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, 1248 shift + 1, shift); 1249 } 1250 1251 static void dispc_configure_burst_sizes(struct dispc_device *dispc) 1252 { 1253 int i; 1254 const int burst_size = BURST_SIZE_X8; 1255 1256 /* Configure burst size always to maximum size */ 1257 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) 1258 dispc_ovl_set_burst_size(dispc, i, burst_size); 1259 if (dispc->feat->has_writeback) 1260 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); 1261 } 1262 1263 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, 1264 enum omap_plane_id plane) 1265 { 1266 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1267 return dispc->feat->burst_size_unit * 8; 1268 } 1269 1270 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, 1271 enum omap_plane_id plane, u32 fourcc) 1272 { 1273 const u32 *modes; 1274 unsigned int i; 1275 1276 modes = dispc->feat->supported_color_modes[plane]; 1277 1278 for (i = 0; modes[i]; ++i) { 1279 if (modes[i] == fourcc) 1280 return true; 1281 } 1282 1283 return false; 1284 } 1285 1286 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, 1287 enum omap_plane_id plane) 1288 { 1289 return dispc->feat->supported_color_modes[plane]; 1290 } 1291 1292 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, 1293 enum omap_channel channel, bool enable) 1294 { 1295 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1296 return; 1297 1298 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); 1299 } 1300 1301 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, 1302 enum omap_channel channel, 1303 const struct omap_dss_cpr_coefs *coefs) 1304 { 1305 u32 coef_r, coef_g, coef_b; 1306 1307 if (!dss_mgr_is_lcd(channel)) 1308 return; 1309 1310 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1311 FLD_VAL(coefs->rb, 9, 0); 1312 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1313 FLD_VAL(coefs->gb, 9, 0); 1314 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1315 FLD_VAL(coefs->bb, 9, 0); 1316 1317 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); 1318 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); 1319 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); 1320 } 1321 1322 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, 1323 enum omap_plane_id plane, bool enable) 1324 { 1325 u32 val; 1326 1327 BUG_ON(plane == OMAP_DSS_GFX); 1328 1329 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1330 val = FLD_MOD(val, enable, 9, 9); 1331 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); 1332 } 1333 1334 static void dispc_ovl_enable_replication(struct dispc_device *dispc, 1335 enum omap_plane_id plane, 1336 enum omap_overlay_caps caps, 1337 bool enable) 1338 { 1339 static const unsigned int shifts[] = { 5, 10, 10, 10 }; 1340 int shift; 1341 1342 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1343 return; 1344 1345 shift = shifts[plane]; 1346 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1347 } 1348 1349 static void dispc_mgr_set_size(struct dispc_device *dispc, 1350 enum omap_channel channel, u16 width, u16 height) 1351 { 1352 u32 val; 1353 1354 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | 1355 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); 1356 1357 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); 1358 } 1359 1360 static void dispc_init_fifos(struct dispc_device *dispc) 1361 { 1362 u32 size; 1363 int fifo; 1364 u8 start, end; 1365 u32 unit; 1366 int i; 1367 1368 unit = dispc->feat->buffer_size_unit; 1369 1370 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); 1371 1372 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { 1373 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), 1374 start, end); 1375 size *= unit; 1376 dispc->fifo_size[fifo] = size; 1377 1378 /* 1379 * By default fifos are mapped directly to overlays, fifo 0 to 1380 * ovl 0, fifo 1 to ovl 1, etc. 1381 */ 1382 dispc->fifo_assignment[fifo] = fifo; 1383 } 1384 1385 /* 1386 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1387 * causes problems with certain use cases, like using the tiler in 2D 1388 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1389 * giving GFX plane a larger fifo. WB but should work fine with a 1390 * smaller fifo. 1391 */ 1392 if (dispc->feat->gfx_fifo_workaround) { 1393 u32 v; 1394 1395 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); 1396 1397 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1398 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1399 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1400 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1401 1402 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); 1403 1404 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1405 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1406 } 1407 1408 /* 1409 * Setup default fifo thresholds. 1410 */ 1411 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { 1412 u32 low, high; 1413 const bool use_fifomerge = false; 1414 const bool manual_update = false; 1415 1416 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, 1417 use_fifomerge, manual_update); 1418 1419 dispc_ovl_set_fifo_threshold(dispc, i, low, high); 1420 } 1421 1422 if (dispc->feat->has_writeback) { 1423 u32 low, high; 1424 const bool use_fifomerge = false; 1425 const bool manual_update = false; 1426 1427 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, 1428 &low, &high, use_fifomerge, 1429 manual_update); 1430 1431 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); 1432 } 1433 } 1434 1435 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, 1436 enum omap_plane_id plane) 1437 { 1438 int fifo; 1439 u32 size = 0; 1440 1441 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { 1442 if (dispc->fifo_assignment[fifo] == plane) 1443 size += dispc->fifo_size[fifo]; 1444 } 1445 1446 return size; 1447 } 1448 1449 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, 1450 enum omap_plane_id plane, 1451 u32 low, u32 high) 1452 { 1453 u8 hi_start, hi_end, lo_start, lo_end; 1454 u32 unit; 1455 1456 unit = dispc->feat->buffer_size_unit; 1457 1458 WARN_ON(low % unit != 0); 1459 WARN_ON(high % unit != 0); 1460 1461 low /= unit; 1462 high /= unit; 1463 1464 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, 1465 &hi_start, &hi_end); 1466 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, 1467 &lo_start, &lo_end); 1468 1469 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1470 plane, 1471 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1472 lo_start, lo_end) * unit, 1473 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1474 hi_start, hi_end) * unit, 1475 low * unit, high * unit); 1476 1477 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1478 FLD_VAL(high, hi_start, hi_end) | 1479 FLD_VAL(low, lo_start, lo_end)); 1480 1481 /* 1482 * configure the preload to the pipeline's high threhold, if HT it's too 1483 * large for the preload field, set the threshold to the maximum value 1484 * that can be held by the preload register 1485 */ 1486 if (dispc_has_feature(dispc, FEAT_PRELOAD) && 1487 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) 1488 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), 1489 min(high, 0xfffu)); 1490 } 1491 1492 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) 1493 { 1494 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { 1495 WARN_ON(enable); 1496 return; 1497 } 1498 1499 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1500 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1501 } 1502 1503 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, 1504 enum omap_plane_id plane, 1505 u32 *fifo_low, u32 *fifo_high, 1506 bool use_fifomerge, bool manual_update) 1507 { 1508 /* 1509 * All sizes are in bytes. Both the buffer and burst are made of 1510 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1511 */ 1512 unsigned int buf_unit = dispc->feat->buffer_size_unit; 1513 unsigned int ovl_fifo_size, total_fifo_size, burst_size; 1514 int i; 1515 1516 burst_size = dispc_ovl_get_burst_size(dispc, plane); 1517 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); 1518 1519 if (use_fifomerge) { 1520 total_fifo_size = 0; 1521 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) 1522 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); 1523 } else { 1524 total_fifo_size = ovl_fifo_size; 1525 } 1526 1527 /* 1528 * We use the same low threshold for both fifomerge and non-fifomerge 1529 * cases, but for fifomerge we calculate the high threshold using the 1530 * combined fifo size 1531 */ 1532 1533 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { 1534 *fifo_low = ovl_fifo_size - burst_size * 2; 1535 *fifo_high = total_fifo_size - burst_size; 1536 } else if (plane == OMAP_DSS_WB) { 1537 /* 1538 * Most optimal configuration for writeback is to push out data 1539 * to the interconnect the moment writeback pushes enough pixels 1540 * in the FIFO to form a burst 1541 */ 1542 *fifo_low = 0; 1543 *fifo_high = burst_size; 1544 } else { 1545 *fifo_low = ovl_fifo_size - burst_size; 1546 *fifo_high = total_fifo_size - buf_unit; 1547 } 1548 } 1549 1550 static void dispc_ovl_set_mflag(struct dispc_device *dispc, 1551 enum omap_plane_id plane, bool enable) 1552 { 1553 int bit; 1554 1555 if (plane == OMAP_DSS_GFX) 1556 bit = 14; 1557 else 1558 bit = 23; 1559 1560 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1561 } 1562 1563 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, 1564 enum omap_plane_id plane, 1565 int low, int high) 1566 { 1567 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), 1568 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1569 } 1570 1571 static void dispc_init_mflag(struct dispc_device *dispc) 1572 { 1573 int i; 1574 1575 /* 1576 * HACK: NV12 color format and MFLAG seem to have problems working 1577 * together: using two displays, and having an NV12 overlay on one of 1578 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1579 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1580 * remove the errors, but there doesn't seem to be a clear logic on 1581 * which values work and which not. 1582 * 1583 * As a work-around, set force MFLAG to always on. 1584 */ 1585 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1586 (1 << 0) | /* MFLAG_CTRL = force always on */ 1587 (0 << 2)); /* MFLAG_START = disable */ 1588 1589 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { 1590 u32 size = dispc_ovl_get_fifo_size(dispc, i); 1591 u32 unit = dispc->feat->buffer_size_unit; 1592 u32 low, high; 1593 1594 dispc_ovl_set_mflag(dispc, i, true); 1595 1596 /* 1597 * Simulation team suggests below thesholds: 1598 * HT = fifosize * 5 / 8; 1599 * LT = fifosize * 4 / 8; 1600 */ 1601 1602 low = size * 4 / 8 / unit; 1603 high = size * 5 / 8 / unit; 1604 1605 dispc_ovl_set_mflag_threshold(dispc, i, low, high); 1606 } 1607 1608 if (dispc->feat->has_writeback) { 1609 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); 1610 u32 unit = dispc->feat->buffer_size_unit; 1611 u32 low, high; 1612 1613 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); 1614 1615 /* 1616 * Simulation team suggests below thesholds: 1617 * HT = fifosize * 5 / 8; 1618 * LT = fifosize * 4 / 8; 1619 */ 1620 1621 low = size * 4 / 8 / unit; 1622 high = size * 5 / 8 / unit; 1623 1624 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); 1625 } 1626 } 1627 1628 static void dispc_ovl_set_fir(struct dispc_device *dispc, 1629 enum omap_plane_id plane, 1630 int hinc, int vinc, 1631 enum omap_color_component color_comp) 1632 { 1633 u32 val; 1634 1635 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1636 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1637 1638 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, 1639 &hinc_start, &hinc_end); 1640 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, 1641 &vinc_start, &vinc_end); 1642 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1643 FLD_VAL(hinc, hinc_start, hinc_end); 1644 1645 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); 1646 } else { 1647 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1648 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); 1649 } 1650 } 1651 1652 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, 1653 enum omap_plane_id plane, int haccu, 1654 int vaccu) 1655 { 1656 u32 val; 1657 u8 hor_start, hor_end, vert_start, vert_end; 1658 1659 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, 1660 &hor_start, &hor_end); 1661 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, 1662 &vert_start, &vert_end); 1663 1664 val = FLD_VAL(vaccu, vert_start, vert_end) | 1665 FLD_VAL(haccu, hor_start, hor_end); 1666 1667 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); 1668 } 1669 1670 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, 1671 enum omap_plane_id plane, int haccu, 1672 int vaccu) 1673 { 1674 u32 val; 1675 u8 hor_start, hor_end, vert_start, vert_end; 1676 1677 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, 1678 &hor_start, &hor_end); 1679 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, 1680 &vert_start, &vert_end); 1681 1682 val = FLD_VAL(vaccu, vert_start, vert_end) | 1683 FLD_VAL(haccu, hor_start, hor_end); 1684 1685 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); 1686 } 1687 1688 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, 1689 enum omap_plane_id plane, int haccu, 1690 int vaccu) 1691 { 1692 u32 val; 1693 1694 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1695 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); 1696 } 1697 1698 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, 1699 enum omap_plane_id plane, int haccu, 1700 int vaccu) 1701 { 1702 u32 val; 1703 1704 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1705 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); 1706 } 1707 1708 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, 1709 enum omap_plane_id plane, 1710 u16 orig_width, u16 orig_height, 1711 u16 out_width, u16 out_height, 1712 bool five_taps, u8 rotation, 1713 enum omap_color_component color_comp) 1714 { 1715 int fir_hinc, fir_vinc; 1716 1717 fir_hinc = 1024 * orig_width / out_width; 1718 fir_vinc = 1024 * orig_height / out_height; 1719 1720 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, 1721 color_comp); 1722 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); 1723 } 1724 1725 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, 1726 enum omap_plane_id plane, 1727 u16 orig_width, u16 orig_height, 1728 u16 out_width, u16 out_height, 1729 bool ilace, u32 fourcc, u8 rotation) 1730 { 1731 int h_accu2_0, h_accu2_1; 1732 int v_accu2_0, v_accu2_1; 1733 int chroma_hinc, chroma_vinc; 1734 int idx; 1735 1736 struct accu { 1737 s8 h0_m, h0_n; 1738 s8 h1_m, h1_n; 1739 s8 v0_m, v0_n; 1740 s8 v1_m, v1_n; 1741 }; 1742 1743 const struct accu *accu_table; 1744 const struct accu *accu_val; 1745 1746 static const struct accu accu_nv12[4] = { 1747 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1748 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1749 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1750 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1751 }; 1752 1753 static const struct accu accu_nv12_ilace[4] = { 1754 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1755 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1756 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1757 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1758 }; 1759 1760 static const struct accu accu_yuv[4] = { 1761 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1762 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1763 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1764 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1765 }; 1766 1767 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1768 switch (rotation & DRM_MODE_ROTATE_MASK) { 1769 default: 1770 case DRM_MODE_ROTATE_0: 1771 idx = 0; 1772 break; 1773 case DRM_MODE_ROTATE_90: 1774 idx = 3; 1775 break; 1776 case DRM_MODE_ROTATE_180: 1777 idx = 2; 1778 break; 1779 case DRM_MODE_ROTATE_270: 1780 idx = 1; 1781 break; 1782 } 1783 1784 switch (fourcc) { 1785 case DRM_FORMAT_NV12: 1786 if (ilace) 1787 accu_table = accu_nv12_ilace; 1788 else 1789 accu_table = accu_nv12; 1790 break; 1791 case DRM_FORMAT_YUYV: 1792 case DRM_FORMAT_UYVY: 1793 accu_table = accu_yuv; 1794 break; 1795 default: 1796 BUG(); 1797 return; 1798 } 1799 1800 accu_val = &accu_table[idx]; 1801 1802 chroma_hinc = 1024 * orig_width / out_width; 1803 chroma_vinc = 1024 * orig_height / out_height; 1804 1805 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1806 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1807 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1808 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1809 1810 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); 1811 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); 1812 } 1813 1814 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, 1815 enum omap_plane_id plane, 1816 u16 orig_width, u16 orig_height, 1817 u16 out_width, u16 out_height, 1818 bool ilace, bool five_taps, 1819 bool fieldmode, u32 fourcc, 1820 u8 rotation) 1821 { 1822 int accu0 = 0; 1823 int accu1 = 0; 1824 u32 l; 1825 1826 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, 1827 out_width, out_height, five_taps, 1828 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1829 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1830 1831 /* RESIZEENABLE and VERTICALTAPS */ 1832 l &= ~((0x3 << 5) | (0x1 << 21)); 1833 l |= (orig_width != out_width) ? (1 << 5) : 0; 1834 l |= (orig_height != out_height) ? (1 << 6) : 0; 1835 l |= five_taps ? (1 << 21) : 0; 1836 1837 /* VRESIZECONF and HRESIZECONF */ 1838 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { 1839 l &= ~(0x3 << 7); 1840 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1841 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1842 } 1843 1844 /* LINEBUFFERSPLIT */ 1845 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { 1846 l &= ~(0x1 << 22); 1847 l |= five_taps ? (1 << 22) : 0; 1848 } 1849 1850 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); 1851 1852 /* 1853 * field 0 = even field = bottom field 1854 * field 1 = odd field = top field 1855 */ 1856 if (ilace && !fieldmode) { 1857 accu1 = 0; 1858 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1859 if (accu0 >= 1024/2) { 1860 accu1 = 1024/2; 1861 accu0 -= accu1; 1862 } 1863 } 1864 1865 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); 1866 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); 1867 } 1868 1869 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, 1870 enum omap_plane_id plane, 1871 u16 orig_width, u16 orig_height, 1872 u16 out_width, u16 out_height, 1873 bool ilace, bool five_taps, 1874 bool fieldmode, u32 fourcc, 1875 u8 rotation) 1876 { 1877 int scale_x = out_width != orig_width; 1878 int scale_y = out_height != orig_height; 1879 bool chroma_upscale = plane != OMAP_DSS_WB; 1880 const struct drm_format_info *info; 1881 1882 info = drm_format_info(fourcc); 1883 1884 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) 1885 return; 1886 1887 if (!info->is_yuv) { 1888 /* reset chroma resampling for RGB formats */ 1889 if (plane != OMAP_DSS_WB) 1890 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 1891 0, 8, 8); 1892 return; 1893 } 1894 1895 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, 1896 out_height, ilace, fourcc, rotation); 1897 1898 switch (fourcc) { 1899 case DRM_FORMAT_NV12: 1900 if (chroma_upscale) { 1901 /* UV is subsampled by 2 horizontally and vertically */ 1902 orig_height >>= 1; 1903 orig_width >>= 1; 1904 } else { 1905 /* UV is downsampled by 2 horizontally and vertically */ 1906 orig_height <<= 1; 1907 orig_width <<= 1; 1908 } 1909 1910 break; 1911 case DRM_FORMAT_YUYV: 1912 case DRM_FORMAT_UYVY: 1913 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1914 if (!drm_rotation_90_or_270(rotation)) { 1915 if (chroma_upscale) 1916 /* UV is subsampled by 2 horizontally */ 1917 orig_width >>= 1; 1918 else 1919 /* UV is downsampled by 2 horizontally */ 1920 orig_width <<= 1; 1921 } 1922 1923 /* must use FIR for YUV422 if rotated */ 1924 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0) 1925 scale_x = scale_y = true; 1926 1927 break; 1928 default: 1929 BUG(); 1930 return; 1931 } 1932 1933 if (out_width != orig_width) 1934 scale_x = true; 1935 if (out_height != orig_height) 1936 scale_y = true; 1937 1938 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, 1939 out_width, out_height, five_taps, 1940 rotation, DISPC_COLOR_COMPONENT_UV); 1941 1942 if (plane != OMAP_DSS_WB) 1943 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 1944 (scale_x || scale_y) ? 1 : 0, 8, 8); 1945 1946 /* set H scaling */ 1947 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1948 /* set V scaling */ 1949 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1950 } 1951 1952 static void dispc_ovl_set_scaling(struct dispc_device *dispc, 1953 enum omap_plane_id plane, 1954 u16 orig_width, u16 orig_height, 1955 u16 out_width, u16 out_height, 1956 bool ilace, bool five_taps, 1957 bool fieldmode, u32 fourcc, 1958 u8 rotation) 1959 { 1960 BUG_ON(plane == OMAP_DSS_GFX); 1961 1962 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, 1963 out_width, out_height, ilace, five_taps, 1964 fieldmode, fourcc, rotation); 1965 1966 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, 1967 out_width, out_height, ilace, five_taps, 1968 fieldmode, fourcc, rotation); 1969 } 1970 1971 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, 1972 enum omap_plane_id plane, u8 rotation, 1973 enum omap_dss_rotation_type rotation_type, 1974 u32 fourcc) 1975 { 1976 bool row_repeat = false; 1977 int vidrot = 0; 1978 1979 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1980 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) { 1981 1982 if (rotation & DRM_MODE_REFLECT_X) { 1983 switch (rotation & DRM_MODE_ROTATE_MASK) { 1984 case DRM_MODE_ROTATE_0: 1985 vidrot = 2; 1986 break; 1987 case DRM_MODE_ROTATE_90: 1988 vidrot = 1; 1989 break; 1990 case DRM_MODE_ROTATE_180: 1991 vidrot = 0; 1992 break; 1993 case DRM_MODE_ROTATE_270: 1994 vidrot = 3; 1995 break; 1996 } 1997 } else { 1998 switch (rotation & DRM_MODE_ROTATE_MASK) { 1999 case DRM_MODE_ROTATE_0: 2000 vidrot = 0; 2001 break; 2002 case DRM_MODE_ROTATE_90: 2003 vidrot = 3; 2004 break; 2005 case DRM_MODE_ROTATE_180: 2006 vidrot = 2; 2007 break; 2008 case DRM_MODE_ROTATE_270: 2009 vidrot = 1; 2010 break; 2011 } 2012 } 2013 2014 if (drm_rotation_90_or_270(rotation)) 2015 row_repeat = true; 2016 else 2017 row_repeat = false; 2018 } 2019 2020 /* 2021 * OMAP4/5 Errata i631: 2022 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 2023 * rows beyond the framebuffer, which may cause OCP error. 2024 */ 2025 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) 2026 vidrot = 1; 2027 2028 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 2029 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) 2030 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 2031 row_repeat ? 1 : 0, 18, 18); 2032 2033 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { 2034 bool doublestride = 2035 fourcc == DRM_FORMAT_NV12 && 2036 rotation_type == OMAP_DSS_ROT_TILER && 2037 !drm_rotation_90_or_270(rotation); 2038 2039 /* DOUBLESTRIDE */ 2040 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 2041 doublestride, 22, 22); 2042 } 2043 } 2044 2045 static int color_mode_to_bpp(u32 fourcc) 2046 { 2047 switch (fourcc) { 2048 case DRM_FORMAT_NV12: 2049 return 8; 2050 case DRM_FORMAT_RGBX4444: 2051 case DRM_FORMAT_RGB565: 2052 case DRM_FORMAT_ARGB4444: 2053 case DRM_FORMAT_YUYV: 2054 case DRM_FORMAT_UYVY: 2055 case DRM_FORMAT_RGBA4444: 2056 case DRM_FORMAT_XRGB4444: 2057 case DRM_FORMAT_ARGB1555: 2058 case DRM_FORMAT_XRGB1555: 2059 return 16; 2060 case DRM_FORMAT_RGB888: 2061 return 24; 2062 case DRM_FORMAT_XRGB8888: 2063 case DRM_FORMAT_ARGB8888: 2064 case DRM_FORMAT_RGBA8888: 2065 case DRM_FORMAT_RGBX8888: 2066 return 32; 2067 default: 2068 BUG(); 2069 return 0; 2070 } 2071 } 2072 2073 static s32 pixinc(int pixels, u8 ps) 2074 { 2075 if (pixels == 1) 2076 return 1; 2077 else if (pixels > 1) 2078 return 1 + (pixels - 1) * ps; 2079 else if (pixels < 0) 2080 return 1 - (-pixels + 1) * ps; 2081 else 2082 BUG(); 2083 return 0; 2084 } 2085 2086 static void calc_offset(u16 screen_width, u16 width, 2087 u32 fourcc, bool fieldmode, unsigned int field_offset, 2088 unsigned int *offset0, unsigned int *offset1, 2089 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, 2090 enum omap_dss_rotation_type rotation_type, u8 rotation) 2091 { 2092 u8 ps; 2093 2094 ps = color_mode_to_bpp(fourcc) / 8; 2095 2096 DSSDBG("scrw %d, width %d\n", screen_width, width); 2097 2098 if (rotation_type == OMAP_DSS_ROT_TILER && 2099 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && 2100 drm_rotation_90_or_270(rotation)) { 2101 /* 2102 * HACK: ROW_INC needs to be calculated with TILER units. 2103 * We get such 'screen_width' that multiplying it with the 2104 * YUV422 pixel size gives the correct TILER container width. 2105 * However, 'width' is in pixels and multiplying it with YUV422 2106 * pixel size gives incorrect result. We thus multiply it here 2107 * with 2 to match the 32 bit TILER unit size. 2108 */ 2109 width *= 2; 2110 } 2111 2112 /* 2113 * field 0 = even field = bottom field 2114 * field 1 = odd field = top field 2115 */ 2116 *offset0 = field_offset * screen_width * ps; 2117 *offset1 = 0; 2118 2119 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 2120 (fieldmode ? screen_width : 0), ps); 2121 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) 2122 *pix_inc = pixinc(x_predecim, 2 * ps); 2123 else 2124 *pix_inc = pixinc(x_predecim, ps); 2125 } 2126 2127 /* 2128 * This function is used to avoid synclosts in OMAP3, because of some 2129 * undocumented horizontal position and timing related limitations. 2130 */ 2131 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2132 const struct videomode *vm, u16 pos_x, 2133 u16 width, u16 height, u16 out_width, u16 out_height, 2134 bool five_taps) 2135 { 2136 const int ds = DIV_ROUND_UP(height, out_height); 2137 unsigned long nonactive; 2138 static const u8 limits[3] = { 8, 10, 20 }; 2139 u64 val, blank; 2140 int i; 2141 2142 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + 2143 vm->hback_porch - out_width; 2144 2145 i = 0; 2146 if (out_height < height) 2147 i++; 2148 if (out_width < width) 2149 i++; 2150 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * 2151 lclk, pclk); 2152 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2153 if (blank <= limits[i]) 2154 return -EINVAL; 2155 2156 /* FIXME add checks for 3-tap filter once the limitations are known */ 2157 if (!five_taps) 2158 return 0; 2159 2160 /* 2161 * Pixel data should be prepared before visible display point starts. 2162 * So, atleast DS-2 lines must have already been fetched by DISPC 2163 * during nonactive - pos_x period. 2164 */ 2165 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 2166 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2167 val, max(0, ds - 2) * width); 2168 if (val < max(0, ds - 2) * width) 2169 return -EINVAL; 2170 2171 /* 2172 * All lines need to be refilled during the nonactive period of which 2173 * only one line can be loaded during the active period. So, atleast 2174 * DS - 1 lines should be loaded during nonactive period. 2175 */ 2176 val = div_u64((u64)nonactive * lclk, pclk); 2177 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2178 val, max(0, ds - 1) * width); 2179 if (val < max(0, ds - 1) * width) 2180 return -EINVAL; 2181 2182 return 0; 2183 } 2184 2185 static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2186 const struct videomode *vm, u16 width, 2187 u16 height, u16 out_width, u16 out_height, 2188 u32 fourcc) 2189 { 2190 u32 core_clk = 0; 2191 u64 tmp; 2192 2193 if (height <= out_height && width <= out_width) 2194 return (unsigned long) pclk; 2195 2196 if (height > out_height) { 2197 unsigned int ppl = vm->hactive; 2198 2199 tmp = (u64)pclk * height * out_width; 2200 do_div(tmp, 2 * out_height * ppl); 2201 core_clk = tmp; 2202 2203 if (height > 2 * out_height) { 2204 if (ppl == out_width) 2205 return 0; 2206 2207 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2208 do_div(tmp, 2 * out_height * (ppl - out_width)); 2209 core_clk = max_t(u32, core_clk, tmp); 2210 } 2211 } 2212 2213 if (width > out_width) { 2214 tmp = (u64)pclk * width; 2215 do_div(tmp, out_width); 2216 core_clk = max_t(u32, core_clk, tmp); 2217 2218 if (fourcc == DRM_FORMAT_XRGB8888) 2219 core_clk <<= 1; 2220 } 2221 2222 return core_clk; 2223 } 2224 2225 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2226 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2227 { 2228 if (height > out_height && width > out_width) 2229 return pclk * 4; 2230 else 2231 return pclk * 2; 2232 } 2233 2234 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2235 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2236 { 2237 unsigned int hf, vf; 2238 2239 /* 2240 * FIXME how to determine the 'A' factor 2241 * for the no downscaling case ? 2242 */ 2243 2244 if (width > 3 * out_width) 2245 hf = 4; 2246 else if (width > 2 * out_width) 2247 hf = 3; 2248 else if (width > out_width) 2249 hf = 2; 2250 else 2251 hf = 1; 2252 if (height > out_height) 2253 vf = 2; 2254 else 2255 vf = 1; 2256 2257 return pclk * vf * hf; 2258 } 2259 2260 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2261 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2262 { 2263 /* 2264 * If the overlay/writeback is in mem to mem mode, there are no 2265 * downscaling limitations with respect to pixel clock, return 1 as 2266 * required core clock to represent that we have sufficient enough 2267 * core clock to do maximum downscaling 2268 */ 2269 if (mem_to_mem) 2270 return 1; 2271 2272 if (width > out_width) 2273 return DIV_ROUND_UP(pclk, out_width) * width; 2274 else 2275 return pclk; 2276 } 2277 2278 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, 2279 unsigned long pclk, unsigned long lclk, 2280 const struct videomode *vm, 2281 u16 width, u16 height, 2282 u16 out_width, u16 out_height, 2283 u32 fourcc, bool *five_taps, 2284 int *x_predecim, int *y_predecim, 2285 int *decim_x, int *decim_y, 2286 u16 pos_x, unsigned long *core_clk, 2287 bool mem_to_mem) 2288 { 2289 int error; 2290 u16 in_width, in_height; 2291 int min_factor = min(*decim_x, *decim_y); 2292 const int maxsinglelinewidth = dispc->feat->max_line_width; 2293 2294 *five_taps = false; 2295 2296 do { 2297 in_height = height / *decim_y; 2298 in_width = width / *decim_x; 2299 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, 2300 in_height, out_width, out_height, mem_to_mem); 2301 error = (in_width > maxsinglelinewidth || !*core_clk || 2302 *core_clk > dispc_core_clk_rate(dispc)); 2303 if (error) { 2304 if (*decim_x == *decim_y) { 2305 *decim_x = min_factor; 2306 ++*decim_y; 2307 } else { 2308 swap(*decim_x, *decim_y); 2309 if (*decim_x < *decim_y) 2310 ++*decim_x; 2311 } 2312 } 2313 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2314 2315 if (error) { 2316 DSSERR("failed to find scaling settings\n"); 2317 return -EINVAL; 2318 } 2319 2320 if (in_width > maxsinglelinewidth) { 2321 DSSERR("Cannot scale max input width exceeded\n"); 2322 return -EINVAL; 2323 } 2324 return 0; 2325 } 2326 2327 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, 2328 unsigned long pclk, unsigned long lclk, 2329 const struct videomode *vm, 2330 u16 width, u16 height, 2331 u16 out_width, u16 out_height, 2332 u32 fourcc, bool *five_taps, 2333 int *x_predecim, int *y_predecim, 2334 int *decim_x, int *decim_y, 2335 u16 pos_x, unsigned long *core_clk, 2336 bool mem_to_mem) 2337 { 2338 int error; 2339 u16 in_width, in_height; 2340 const int maxsinglelinewidth = dispc->feat->max_line_width; 2341 2342 do { 2343 in_height = height / *decim_y; 2344 in_width = width / *decim_x; 2345 *five_taps = in_height > out_height; 2346 2347 if (in_width > maxsinglelinewidth) 2348 if (in_height > out_height && 2349 in_height < out_height * 2) 2350 *five_taps = false; 2351 again: 2352 if (*five_taps) 2353 *core_clk = calc_core_clk_five_taps(pclk, vm, 2354 in_width, in_height, out_width, 2355 out_height, fourcc); 2356 else 2357 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, 2358 in_height, out_width, out_height, 2359 mem_to_mem); 2360 2361 error = check_horiz_timing_omap3(pclk, lclk, vm, 2362 pos_x, in_width, in_height, out_width, 2363 out_height, *five_taps); 2364 if (error && *five_taps) { 2365 *five_taps = false; 2366 goto again; 2367 } 2368 2369 error = (error || in_width > maxsinglelinewidth * 2 || 2370 (in_width > maxsinglelinewidth && *five_taps) || 2371 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); 2372 2373 if (!error) { 2374 /* verify that we're inside the limits of scaler */ 2375 if (in_width / 4 > out_width) 2376 error = 1; 2377 2378 if (*five_taps) { 2379 if (in_height / 4 > out_height) 2380 error = 1; 2381 } else { 2382 if (in_height / 2 > out_height) 2383 error = 1; 2384 } 2385 } 2386 2387 if (error) 2388 ++*decim_y; 2389 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2390 2391 if (error) { 2392 DSSERR("failed to find scaling settings\n"); 2393 return -EINVAL; 2394 } 2395 2396 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width, 2397 in_height, out_width, out_height, *five_taps)) { 2398 DSSERR("horizontal timing too tight\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (in_width > (maxsinglelinewidth * 2)) { 2403 DSSERR("Cannot setup scaling\n"); 2404 DSSERR("width exceeds maximum width possible\n"); 2405 return -EINVAL; 2406 } 2407 2408 if (in_width > maxsinglelinewidth && *five_taps) { 2409 DSSERR("cannot setup scaling with five taps\n"); 2410 return -EINVAL; 2411 } 2412 return 0; 2413 } 2414 2415 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, 2416 unsigned long pclk, unsigned long lclk, 2417 const struct videomode *vm, 2418 u16 width, u16 height, 2419 u16 out_width, u16 out_height, 2420 u32 fourcc, bool *five_taps, 2421 int *x_predecim, int *y_predecim, 2422 int *decim_x, int *decim_y, 2423 u16 pos_x, unsigned long *core_clk, 2424 bool mem_to_mem) 2425 { 2426 u16 in_width, in_width_max; 2427 int decim_x_min = *decim_x; 2428 u16 in_height = height / *decim_y; 2429 const int maxsinglelinewidth = dispc->feat->max_line_width; 2430 const int maxdownscale = dispc->feat->max_downscale; 2431 2432 if (mem_to_mem) { 2433 in_width_max = out_width * maxdownscale; 2434 } else { 2435 in_width_max = dispc_core_clk_rate(dispc) 2436 / DIV_ROUND_UP(pclk, out_width); 2437 } 2438 2439 *decim_x = DIV_ROUND_UP(width, in_width_max); 2440 2441 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; 2442 if (*decim_x > *x_predecim) 2443 return -EINVAL; 2444 2445 do { 2446 in_width = width / *decim_x; 2447 } while (*decim_x <= *x_predecim && 2448 in_width > maxsinglelinewidth && ++*decim_x); 2449 2450 if (in_width > maxsinglelinewidth) { 2451 DSSERR("Cannot scale width exceeds max line width\n"); 2452 return -EINVAL; 2453 } 2454 2455 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) { 2456 /* 2457 * Let's disable all scaling that requires horizontal 2458 * decimation with higher factor than 4, until we have 2459 * better estimates of what we can and can not 2460 * do. However, NV12 color format appears to work Ok 2461 * with all decimation factors. 2462 * 2463 * When decimating horizontally by more that 4 the dss 2464 * is not able to fetch the data in burst mode. When 2465 * this happens it is hard to tell if there enough 2466 * bandwidth. Despite what theory says this appears to 2467 * be true also for 16-bit color formats. 2468 */ 2469 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x); 2470 2471 return -EINVAL; 2472 } 2473 2474 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, 2475 out_width, out_height, mem_to_mem); 2476 return 0; 2477 } 2478 2479 #define DIV_FRAC(dividend, divisor) \ 2480 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2481 2482 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, 2483 enum omap_plane_id plane, 2484 unsigned long pclk, unsigned long lclk, 2485 enum omap_overlay_caps caps, 2486 const struct videomode *vm, 2487 u16 width, u16 height, 2488 u16 out_width, u16 out_height, 2489 u32 fourcc, bool *five_taps, 2490 int *x_predecim, int *y_predecim, u16 pos_x, 2491 enum omap_dss_rotation_type rotation_type, 2492 bool mem_to_mem) 2493 { 2494 int maxhdownscale = dispc->feat->max_downscale; 2495 int maxvdownscale = dispc->feat->max_downscale; 2496 const int max_decim_limit = 16; 2497 unsigned long core_clk = 0; 2498 int decim_x, decim_y, ret; 2499 2500 if (width == out_width && height == out_height) 2501 return 0; 2502 2503 if (dispc->feat->supported_scaler_color_modes) { 2504 const u32 *modes = dispc->feat->supported_scaler_color_modes; 2505 unsigned int i; 2506 2507 for (i = 0; modes[i]; ++i) { 2508 if (modes[i] == fourcc) 2509 break; 2510 } 2511 2512 if (modes[i] == 0) 2513 return -EINVAL; 2514 } 2515 2516 if (plane == OMAP_DSS_WB) { 2517 switch (fourcc) { 2518 case DRM_FORMAT_NV12: 2519 maxhdownscale = maxvdownscale = 2; 2520 break; 2521 case DRM_FORMAT_YUYV: 2522 case DRM_FORMAT_UYVY: 2523 maxhdownscale = 2; 2524 maxvdownscale = 4; 2525 break; 2526 default: 2527 break; 2528 } 2529 } 2530 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { 2531 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2532 return -EINVAL; 2533 } 2534 2535 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2536 return -EINVAL; 2537 2538 if (mem_to_mem) { 2539 *x_predecim = *y_predecim = 1; 2540 } else { 2541 *x_predecim = max_decim_limit; 2542 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2543 dispc_has_feature(dispc, FEAT_BURST_2D)) ? 2544 2 : max_decim_limit; 2545 } 2546 2547 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale); 2548 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxvdownscale); 2549 2550 if (decim_x > *x_predecim || out_width > width * 8) 2551 return -EINVAL; 2552 2553 if (decim_y > *y_predecim || out_height > height * 8) 2554 return -EINVAL; 2555 2556 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, 2557 out_width, out_height, fourcc, 2558 five_taps, x_predecim, y_predecim, 2559 &decim_x, &decim_y, pos_x, &core_clk, 2560 mem_to_mem); 2561 if (ret) 2562 return ret; 2563 2564 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2565 width, height, 2566 out_width, out_height, 2567 out_width / width, DIV_FRAC(out_width, width), 2568 out_height / height, DIV_FRAC(out_height, height), 2569 2570 decim_x, decim_y, 2571 width / decim_x, height / decim_y, 2572 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2573 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2574 2575 *five_taps ? 5 : 3, 2576 core_clk, dispc_core_clk_rate(dispc)); 2577 2578 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { 2579 DSSERR("failed to set up scaling, " 2580 "required core clk rate = %lu Hz, " 2581 "current core clk rate = %lu Hz\n", 2582 core_clk, dispc_core_clk_rate(dispc)); 2583 return -EINVAL; 2584 } 2585 2586 *x_predecim = decim_x; 2587 *y_predecim = decim_y; 2588 return 0; 2589 } 2590 2591 static int dispc_ovl_setup_common(struct dispc_device *dispc, 2592 enum omap_plane_id plane, 2593 enum omap_overlay_caps caps, 2594 u32 paddr, u32 p_uv_addr, 2595 u16 screen_width, int pos_x, int pos_y, 2596 u16 width, u16 height, 2597 u16 out_width, u16 out_height, 2598 u32 fourcc, u8 rotation, u8 zorder, 2599 u8 pre_mult_alpha, u8 global_alpha, 2600 enum omap_dss_rotation_type rotation_type, 2601 bool replication, const struct videomode *vm, 2602 bool mem_to_mem) 2603 { 2604 bool five_taps = true; 2605 bool fieldmode = false; 2606 int r, cconv = 0; 2607 unsigned int offset0, offset1; 2608 s32 row_inc; 2609 s32 pix_inc; 2610 u16 frame_width; 2611 unsigned int field_offset = 0; 2612 u16 in_height = height; 2613 u16 in_width = width; 2614 int x_predecim = 1, y_predecim = 1; 2615 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); 2616 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); 2617 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); 2618 const struct drm_format_info *info; 2619 2620 info = drm_format_info(fourcc); 2621 2622 /* when setting up WB, dispc_plane_pclk_rate() returns 0 */ 2623 if (plane == OMAP_DSS_WB) 2624 pclk = vm->pixelclock; 2625 2626 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2627 return -EINVAL; 2628 2629 if (info->is_yuv && (in_width & 1)) { 2630 DSSERR("input width %d is not even for YUV format\n", in_width); 2631 return -EINVAL; 2632 } 2633 2634 out_width = out_width == 0 ? width : out_width; 2635 out_height = out_height == 0 ? height : out_height; 2636 2637 if (plane != OMAP_DSS_WB) { 2638 if (ilace && height == out_height) 2639 fieldmode = true; 2640 2641 if (ilace) { 2642 if (fieldmode) 2643 in_height /= 2; 2644 pos_y /= 2; 2645 out_height /= 2; 2646 2647 DSSDBG("adjusting for ilace: height %d, pos_y %d, out_height %d\n", 2648 in_height, pos_y, out_height); 2649 } 2650 } 2651 2652 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) 2653 return -EINVAL; 2654 2655 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, 2656 in_height, out_width, out_height, fourcc, 2657 &five_taps, &x_predecim, &y_predecim, pos_x, 2658 rotation_type, mem_to_mem); 2659 if (r) 2660 return r; 2661 2662 in_width = in_width / x_predecim; 2663 in_height = in_height / y_predecim; 2664 2665 if (x_predecim > 1 || y_predecim > 1) 2666 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2667 x_predecim, y_predecim, in_width, in_height); 2668 2669 if (info->is_yuv && (in_width & 1)) { 2670 DSSDBG("predecimated input width is not even for YUV format\n"); 2671 DSSDBG("adjusting input width %d -> %d\n", 2672 in_width, in_width & ~1); 2673 2674 in_width &= ~1; 2675 } 2676 2677 if (info->is_yuv) 2678 cconv = 1; 2679 2680 if (ilace && !fieldmode) { 2681 /* 2682 * when downscaling the bottom field may have to start several 2683 * source lines below the top field. Unfortunately ACCUI 2684 * registers will only hold the fractional part of the offset 2685 * so the integer part must be added to the base address of the 2686 * bottom field. 2687 */ 2688 if (!in_height || in_height == out_height) 2689 field_offset = 0; 2690 else 2691 field_offset = in_height / out_height / 2; 2692 } 2693 2694 /* Fields are independent but interleaved in memory. */ 2695 if (fieldmode) 2696 field_offset = 1; 2697 2698 offset0 = 0; 2699 offset1 = 0; 2700 row_inc = 0; 2701 pix_inc = 0; 2702 2703 if (plane == OMAP_DSS_WB) 2704 frame_width = out_width; 2705 else 2706 frame_width = in_width; 2707 2708 calc_offset(screen_width, frame_width, 2709 fourcc, fieldmode, field_offset, 2710 &offset0, &offset1, &row_inc, &pix_inc, 2711 x_predecim, y_predecim, 2712 rotation_type, rotation); 2713 2714 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2715 offset0, offset1, row_inc, pix_inc); 2716 2717 dispc_ovl_set_color_mode(dispc, plane, fourcc); 2718 2719 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); 2720 2721 if (dispc->feat->reverse_ilace_field_order) 2722 swap(offset0, offset1); 2723 2724 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); 2725 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); 2726 2727 if (fourcc == DRM_FORMAT_NV12) { 2728 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); 2729 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); 2730 } 2731 2732 if (dispc->feat->last_pixel_inc_missing) 2733 row_inc += pix_inc - 1; 2734 2735 dispc_ovl_set_row_inc(dispc, plane, row_inc); 2736 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); 2737 2738 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2739 in_height, out_width, out_height); 2740 2741 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); 2742 2743 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); 2744 2745 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2746 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, 2747 out_width, out_height, ilace, five_taps, 2748 fieldmode, fourcc, rotation); 2749 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); 2750 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); 2751 } 2752 2753 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, 2754 fourcc); 2755 2756 dispc_ovl_set_zorder(dispc, plane, caps, zorder); 2757 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); 2758 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); 2759 2760 dispc_ovl_enable_replication(dispc, plane, caps, replication); 2761 2762 return 0; 2763 } 2764 2765 static int dispc_ovl_setup(struct dispc_device *dispc, 2766 enum omap_plane_id plane, 2767 const struct omap_overlay_info *oi, 2768 const struct videomode *vm, bool mem_to_mem, 2769 enum omap_channel channel) 2770 { 2771 int r; 2772 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; 2773 const bool replication = true; 2774 2775 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2776 " %dx%d, cmode %x, rot %d, chan %d repl %d\n", 2777 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2778 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2779 oi->fourcc, oi->rotation, channel, replication); 2780 2781 dispc_ovl_set_channel_out(dispc, plane, channel); 2782 2783 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, 2784 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2785 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, 2786 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2787 oi->rotation_type, replication, vm, mem_to_mem); 2788 2789 return r; 2790 } 2791 2792 static int dispc_wb_setup(struct dispc_device *dispc, 2793 const struct omap_dss_writeback_info *wi, 2794 bool mem_to_mem, const struct videomode *vm, 2795 enum dss_writeback_channel channel_in) 2796 { 2797 int r; 2798 u32 l; 2799 enum omap_plane_id plane = OMAP_DSS_WB; 2800 const int pos_x = 0, pos_y = 0; 2801 const u8 zorder = 0, global_alpha = 0; 2802 const bool replication = true; 2803 bool truncation; 2804 int in_width = vm->hactive; 2805 int in_height = vm->vactive; 2806 enum omap_overlay_caps caps = 2807 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2808 2809 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2810 in_height /= 2; 2811 2812 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " 2813 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, 2814 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); 2815 2816 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, 2817 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2818 wi->height, wi->fourcc, wi->rotation, zorder, 2819 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2820 replication, vm, mem_to_mem); 2821 if (r) 2822 return r; 2823 2824 switch (wi->fourcc) { 2825 case DRM_FORMAT_RGB565: 2826 case DRM_FORMAT_RGB888: 2827 case DRM_FORMAT_ARGB4444: 2828 case DRM_FORMAT_RGBA4444: 2829 case DRM_FORMAT_RGBX4444: 2830 case DRM_FORMAT_ARGB1555: 2831 case DRM_FORMAT_XRGB1555: 2832 case DRM_FORMAT_XRGB4444: 2833 truncation = true; 2834 break; 2835 default: 2836 truncation = false; 2837 break; 2838 } 2839 2840 /* setup extra DISPC_WB_ATTRIBUTES */ 2841 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 2842 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ 2843 l = FLD_MOD(l, channel_in, 18, 16); /* CHANNELIN */ 2844 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ 2845 if (mem_to_mem) 2846 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ 2847 else 2848 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ 2849 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); 2850 2851 if (mem_to_mem) { 2852 /* WBDELAYCOUNT */ 2853 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); 2854 } else { 2855 u32 wbdelay; 2856 2857 if (channel_in == DSS_WB_TV_MGR) 2858 wbdelay = vm->vsync_len + vm->vback_porch; 2859 else 2860 wbdelay = vm->vfront_porch + vm->vsync_len + 2861 vm->vback_porch; 2862 2863 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2864 wbdelay /= 2; 2865 2866 wbdelay = min(wbdelay, 255u); 2867 2868 /* WBDELAYCOUNT */ 2869 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2870 } 2871 2872 return 0; 2873 } 2874 2875 static bool dispc_has_writeback(struct dispc_device *dispc) 2876 { 2877 return dispc->feat->has_writeback; 2878 } 2879 2880 static int dispc_ovl_enable(struct dispc_device *dispc, 2881 enum omap_plane_id plane, bool enable) 2882 { 2883 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2884 2885 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2886 2887 return 0; 2888 } 2889 2890 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, 2891 bool act_high) 2892 { 2893 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) 2894 return; 2895 2896 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2897 } 2898 2899 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) 2900 { 2901 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) 2902 return; 2903 2904 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2905 } 2906 2907 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) 2908 { 2909 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) 2910 return; 2911 2912 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2913 } 2914 2915 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, 2916 enum omap_channel channel, 2917 bool enable) 2918 { 2919 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2920 } 2921 2922 2923 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, 2924 enum omap_channel channel) 2925 { 2926 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); 2927 } 2928 2929 static void dispc_set_loadmode(struct dispc_device *dispc, 2930 enum omap_dss_load_mode mode) 2931 { 2932 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); 2933 } 2934 2935 2936 static void dispc_mgr_set_default_color(struct dispc_device *dispc, 2937 enum omap_channel channel, u32 color) 2938 { 2939 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); 2940 } 2941 2942 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, 2943 enum omap_channel ch, 2944 enum omap_dss_trans_key_type type, 2945 u32 trans_key) 2946 { 2947 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); 2948 2949 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); 2950 } 2951 2952 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, 2953 enum omap_channel ch, bool enable) 2954 { 2955 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); 2956 } 2957 2958 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, 2959 enum omap_channel ch, 2960 bool enable) 2961 { 2962 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) 2963 return; 2964 2965 if (ch == OMAP_DSS_CHANNEL_LCD) 2966 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); 2967 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2968 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); 2969 } 2970 2971 static void dispc_mgr_setup(struct dispc_device *dispc, 2972 enum omap_channel channel, 2973 const struct omap_overlay_manager_info *info) 2974 { 2975 dispc_mgr_set_default_color(dispc, channel, info->default_color); 2976 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, 2977 info->trans_key); 2978 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); 2979 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, 2980 info->partial_alpha_enabled); 2981 if (dispc_has_feature(dispc, FEAT_CPR)) { 2982 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); 2983 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); 2984 } 2985 } 2986 2987 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, 2988 enum omap_channel channel, 2989 u8 data_lines) 2990 { 2991 int code; 2992 2993 switch (data_lines) { 2994 case 12: 2995 code = 0; 2996 break; 2997 case 16: 2998 code = 1; 2999 break; 3000 case 18: 3001 code = 2; 3002 break; 3003 case 24: 3004 code = 3; 3005 break; 3006 default: 3007 BUG(); 3008 return; 3009 } 3010 3011 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); 3012 } 3013 3014 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, 3015 enum dss_io_pad_mode mode) 3016 { 3017 u32 l; 3018 int gpout0, gpout1; 3019 3020 switch (mode) { 3021 case DSS_IO_PAD_MODE_RESET: 3022 gpout0 = 0; 3023 gpout1 = 0; 3024 break; 3025 case DSS_IO_PAD_MODE_RFBI: 3026 gpout0 = 1; 3027 gpout1 = 0; 3028 break; 3029 case DSS_IO_PAD_MODE_BYPASS: 3030 gpout0 = 1; 3031 gpout1 = 1; 3032 break; 3033 default: 3034 BUG(); 3035 return; 3036 } 3037 3038 l = dispc_read_reg(dispc, DISPC_CONTROL); 3039 l = FLD_MOD(l, gpout0, 15, 15); 3040 l = FLD_MOD(l, gpout1, 16, 16); 3041 dispc_write_reg(dispc, DISPC_CONTROL, l); 3042 } 3043 3044 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, 3045 enum omap_channel channel, bool enable) 3046 { 3047 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); 3048 } 3049 3050 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc, 3051 enum omap_channel channel, 3052 const struct dss_lcd_mgr_config *config) 3053 { 3054 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); 3055 3056 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); 3057 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); 3058 3059 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); 3060 3061 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); 3062 3063 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); 3064 3065 dispc_mgr_set_lcd_type_tft(dispc, channel); 3066 } 3067 3068 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, 3069 u16 width, u16 height) 3070 { 3071 return width <= dispc->feat->mgr_width_max && 3072 height <= dispc->feat->mgr_height_max; 3073 } 3074 3075 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, 3076 int hsync_len, int hfp, int hbp, 3077 int vsw, int vfp, int vbp) 3078 { 3079 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || 3080 hfp < 1 || hfp > dispc->feat->hp_max || 3081 hbp < 1 || hbp > dispc->feat->hp_max || 3082 vsw < 1 || vsw > dispc->feat->sw_max || 3083 vfp < 0 || vfp > dispc->feat->vp_max || 3084 vbp < 0 || vbp > dispc->feat->vp_max) 3085 return false; 3086 return true; 3087 } 3088 3089 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, 3090 enum omap_channel channel, 3091 unsigned long pclk) 3092 { 3093 if (dss_mgr_is_lcd(channel)) 3094 return pclk <= dispc->feat->max_lcd_pclk; 3095 else 3096 return pclk <= dispc->feat->max_tv_pclk; 3097 } 3098 3099 static int dispc_mgr_check_timings(struct dispc_device *dispc, 3100 enum omap_channel channel, 3101 const struct videomode *vm) 3102 { 3103 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) 3104 return MODE_BAD; 3105 3106 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) 3107 return MODE_BAD; 3108 3109 if (dss_mgr_is_lcd(channel)) { 3110 /* TODO: OMAP4+ supports interlace for LCD outputs */ 3111 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 3112 return MODE_BAD; 3113 3114 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, 3115 vm->hfront_porch, vm->hback_porch, 3116 vm->vsync_len, vm->vfront_porch, 3117 vm->vback_porch)) 3118 return MODE_BAD; 3119 } 3120 3121 return MODE_OK; 3122 } 3123 3124 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, 3125 enum omap_channel channel, 3126 const struct videomode *vm) 3127 { 3128 u32 timing_h, timing_v, l; 3129 bool onoff, rf, ipc, vs, hs, de; 3130 3131 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | 3132 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | 3133 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); 3134 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | 3135 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | 3136 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); 3137 3138 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); 3139 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); 3140 3141 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH) 3142 vs = false; 3143 else 3144 vs = true; 3145 3146 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH) 3147 hs = false; 3148 else 3149 hs = true; 3150 3151 if (vm->flags & DISPLAY_FLAGS_DE_HIGH) 3152 de = false; 3153 else 3154 de = true; 3155 3156 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 3157 ipc = false; 3158 else 3159 ipc = true; 3160 3161 /* always use the 'rf' setting */ 3162 onoff = true; 3163 3164 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE) 3165 rf = true; 3166 else 3167 rf = false; 3168 3169 l = FLD_VAL(onoff, 17, 17) | 3170 FLD_VAL(rf, 16, 16) | 3171 FLD_VAL(de, 15, 15) | 3172 FLD_VAL(ipc, 14, 14) | 3173 FLD_VAL(hs, 13, 13) | 3174 FLD_VAL(vs, 12, 12); 3175 3176 /* always set ALIGN bit when available */ 3177 if (dispc->feat->supports_sync_align) 3178 l |= (1 << 18); 3179 3180 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); 3181 3182 if (dispc->syscon_pol) { 3183 const int shifts[] = { 3184 [OMAP_DSS_CHANNEL_LCD] = 0, 3185 [OMAP_DSS_CHANNEL_LCD2] = 1, 3186 [OMAP_DSS_CHANNEL_LCD3] = 2, 3187 }; 3188 3189 u32 mask, val; 3190 3191 mask = (1 << 0) | (1 << 3) | (1 << 6); 3192 val = (rf << 0) | (ipc << 3) | (onoff << 6); 3193 3194 mask <<= 16 + shifts[channel]; 3195 val <<= 16 + shifts[channel]; 3196 3197 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, 3198 mask, val); 3199 } 3200 } 3201 3202 static int vm_flag_to_int(enum display_flags flags, enum display_flags high, 3203 enum display_flags low) 3204 { 3205 if (flags & high) 3206 return 1; 3207 if (flags & low) 3208 return -1; 3209 return 0; 3210 } 3211 3212 /* change name to mode? */ 3213 static void dispc_mgr_set_timings(struct dispc_device *dispc, 3214 enum omap_channel channel, 3215 const struct videomode *vm) 3216 { 3217 unsigned int xtot, ytot; 3218 unsigned long ht, vt; 3219 struct videomode t = *vm; 3220 3221 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 3222 3223 if (dispc_mgr_check_timings(dispc, channel, &t)) { 3224 BUG(); 3225 return; 3226 } 3227 3228 if (dss_mgr_is_lcd(channel)) { 3229 _dispc_mgr_set_lcd_timings(dispc, channel, &t); 3230 3231 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3232 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 3233 3234 ht = vm->pixelclock / xtot; 3235 vt = vm->pixelclock / xtot / ytot; 3236 3237 DSSDBG("pck %lu\n", vm->pixelclock); 3238 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3239 t.hsync_len, t.hfront_porch, t.hback_porch, 3240 t.vsync_len, t.vfront_porch, t.vback_porch); 3241 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3242 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW), 3243 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW), 3244 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE), 3245 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW), 3246 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE)); 3247 3248 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3249 } else { 3250 if (t.flags & DISPLAY_FLAGS_INTERLACED) 3251 t.vactive /= 2; 3252 3253 if (dispc->feat->supports_double_pixel) 3254 REG_FLD_MOD(dispc, DISPC_CONTROL, 3255 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), 3256 19, 17); 3257 } 3258 3259 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); 3260 } 3261 3262 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, 3263 enum omap_channel channel, u16 lck_div, 3264 u16 pck_div) 3265 { 3266 BUG_ON(lck_div < 1); 3267 BUG_ON(pck_div < 1); 3268 3269 dispc_write_reg(dispc, DISPC_DIVISORo(channel), 3270 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3271 3272 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && 3273 channel == OMAP_DSS_CHANNEL_LCD) 3274 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; 3275 } 3276 3277 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, 3278 enum omap_channel channel, int *lck_div, 3279 int *pck_div) 3280 { 3281 u32 l; 3282 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); 3283 *lck_div = FLD_GET(l, 23, 16); 3284 *pck_div = FLD_GET(l, 7, 0); 3285 } 3286 3287 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) 3288 { 3289 unsigned long r; 3290 enum dss_clk_source src; 3291 3292 src = dss_get_dispc_clk_source(dispc->dss); 3293 3294 if (src == DSS_CLK_SRC_FCK) { 3295 r = dss_get_dispc_clk_rate(dispc->dss); 3296 } else { 3297 struct dss_pll *pll; 3298 unsigned int clkout_idx; 3299 3300 pll = dss_pll_find_by_src(dispc->dss, src); 3301 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3302 3303 r = pll->cinfo.clkout[clkout_idx]; 3304 } 3305 3306 return r; 3307 } 3308 3309 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, 3310 enum omap_channel channel) 3311 { 3312 int lcd; 3313 unsigned long r; 3314 enum dss_clk_source src; 3315 3316 /* for TV, LCLK rate is the FCLK rate */ 3317 if (!dss_mgr_is_lcd(channel)) 3318 return dispc_fclk_rate(dispc); 3319 3320 src = dss_get_lcd_clk_source(dispc->dss, channel); 3321 3322 if (src == DSS_CLK_SRC_FCK) { 3323 r = dss_get_dispc_clk_rate(dispc->dss); 3324 } else { 3325 struct dss_pll *pll; 3326 unsigned int clkout_idx; 3327 3328 pll = dss_pll_find_by_src(dispc->dss, src); 3329 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3330 3331 r = pll->cinfo.clkout[clkout_idx]; 3332 } 3333 3334 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); 3335 3336 return r / lcd; 3337 } 3338 3339 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, 3340 enum omap_channel channel) 3341 { 3342 unsigned long r; 3343 3344 if (dss_mgr_is_lcd(channel)) { 3345 int pcd; 3346 u32 l; 3347 3348 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); 3349 3350 pcd = FLD_GET(l, 7, 0); 3351 3352 r = dispc_mgr_lclk_rate(dispc, channel); 3353 3354 return r / pcd; 3355 } else { 3356 return dispc->tv_pclk_rate; 3357 } 3358 } 3359 3360 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) 3361 { 3362 dispc->tv_pclk_rate = pclk; 3363 } 3364 3365 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) 3366 { 3367 return dispc->core_clk_rate; 3368 } 3369 3370 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, 3371 enum omap_plane_id plane) 3372 { 3373 enum omap_channel channel; 3374 3375 if (plane == OMAP_DSS_WB) 3376 return 0; 3377 3378 channel = dispc_ovl_get_channel_out(dispc, plane); 3379 3380 return dispc_mgr_pclk_rate(dispc, channel); 3381 } 3382 3383 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, 3384 enum omap_plane_id plane) 3385 { 3386 enum omap_channel channel; 3387 3388 if (plane == OMAP_DSS_WB) 3389 return 0; 3390 3391 channel = dispc_ovl_get_channel_out(dispc, plane); 3392 3393 return dispc_mgr_lclk_rate(dispc, channel); 3394 } 3395 3396 static void dispc_dump_clocks_channel(struct dispc_device *dispc, 3397 struct seq_file *s, 3398 enum omap_channel channel) 3399 { 3400 int lcd, pcd; 3401 enum dss_clk_source lcd_clk_src; 3402 3403 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3404 3405 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); 3406 3407 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3408 dss_get_clk_source_name(lcd_clk_src)); 3409 3410 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); 3411 3412 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3413 dispc_mgr_lclk_rate(dispc, channel), lcd); 3414 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3415 dispc_mgr_pclk_rate(dispc, channel), pcd); 3416 } 3417 3418 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) 3419 { 3420 enum dss_clk_source dispc_clk_src; 3421 int lcd; 3422 u32 l; 3423 3424 if (dispc_runtime_get(dispc)) 3425 return; 3426 3427 seq_printf(s, "- DISPC -\n"); 3428 3429 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); 3430 seq_printf(s, "dispc fclk source = %s\n", 3431 dss_get_clk_source_name(dispc_clk_src)); 3432 3433 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); 3434 3435 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { 3436 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3437 l = dispc_read_reg(dispc, DISPC_DIVISOR); 3438 lcd = FLD_GET(l, 23, 16); 3439 3440 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3441 (dispc_fclk_rate(dispc)/lcd), lcd); 3442 } 3443 3444 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); 3445 3446 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3447 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); 3448 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3449 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); 3450 3451 dispc_runtime_put(dispc); 3452 } 3453 3454 static int dispc_dump_regs(struct seq_file *s, void *p) 3455 { 3456 struct dispc_device *dispc = s->private; 3457 int i, j; 3458 const char *mgr_names[] = { 3459 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3460 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3461 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3462 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3463 }; 3464 const char *ovl_names[] = { 3465 [OMAP_DSS_GFX] = "GFX", 3466 [OMAP_DSS_VIDEO1] = "VID1", 3467 [OMAP_DSS_VIDEO2] = "VID2", 3468 [OMAP_DSS_VIDEO3] = "VID3", 3469 [OMAP_DSS_WB] = "WB", 3470 }; 3471 const char **p_names; 3472 3473 #define DUMPREG(dispc, r) \ 3474 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) 3475 3476 if (dispc_runtime_get(dispc)) 3477 return 0; 3478 3479 /* DISPC common registers */ 3480 DUMPREG(dispc, DISPC_REVISION); 3481 DUMPREG(dispc, DISPC_SYSCONFIG); 3482 DUMPREG(dispc, DISPC_SYSSTATUS); 3483 DUMPREG(dispc, DISPC_IRQSTATUS); 3484 DUMPREG(dispc, DISPC_IRQENABLE); 3485 DUMPREG(dispc, DISPC_CONTROL); 3486 DUMPREG(dispc, DISPC_CONFIG); 3487 DUMPREG(dispc, DISPC_CAPABLE); 3488 DUMPREG(dispc, DISPC_LINE_STATUS); 3489 DUMPREG(dispc, DISPC_LINE_NUMBER); 3490 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 3491 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 3492 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); 3493 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 3494 DUMPREG(dispc, DISPC_CONTROL2); 3495 DUMPREG(dispc, DISPC_CONFIG2); 3496 } 3497 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 3498 DUMPREG(dispc, DISPC_CONTROL3); 3499 DUMPREG(dispc, DISPC_CONFIG3); 3500 } 3501 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3502 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3503 3504 #undef DUMPREG 3505 3506 #define DISPC_REG(i, name) name(i) 3507 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3508 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3509 dispc_read_reg(dispc, DISPC_REG(i, r))) 3510 3511 p_names = mgr_names; 3512 3513 /* DISPC channel specific registers */ 3514 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 3515 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); 3516 DUMPREG(dispc, i, DISPC_TRANS_COLOR); 3517 DUMPREG(dispc, i, DISPC_SIZE_MGR); 3518 3519 if (i == OMAP_DSS_CHANNEL_DIGIT) 3520 continue; 3521 3522 DUMPREG(dispc, i, DISPC_TIMING_H); 3523 DUMPREG(dispc, i, DISPC_TIMING_V); 3524 DUMPREG(dispc, i, DISPC_POL_FREQ); 3525 DUMPREG(dispc, i, DISPC_DIVISORo); 3526 3527 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); 3528 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); 3529 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); 3530 3531 if (dispc_has_feature(dispc, FEAT_CPR)) { 3532 DUMPREG(dispc, i, DISPC_CPR_COEF_R); 3533 DUMPREG(dispc, i, DISPC_CPR_COEF_G); 3534 DUMPREG(dispc, i, DISPC_CPR_COEF_B); 3535 } 3536 } 3537 3538 p_names = ovl_names; 3539 3540 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 3541 DUMPREG(dispc, i, DISPC_OVL_BA0); 3542 DUMPREG(dispc, i, DISPC_OVL_BA1); 3543 DUMPREG(dispc, i, DISPC_OVL_POSITION); 3544 DUMPREG(dispc, i, DISPC_OVL_SIZE); 3545 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); 3546 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); 3547 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); 3548 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); 3549 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); 3550 3551 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 3552 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); 3553 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3554 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); 3555 3556 if (i == OMAP_DSS_GFX) { 3557 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); 3558 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); 3559 continue; 3560 } 3561 3562 DUMPREG(dispc, i, DISPC_OVL_FIR); 3563 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); 3564 DUMPREG(dispc, i, DISPC_OVL_ACCU0); 3565 DUMPREG(dispc, i, DISPC_OVL_ACCU1); 3566 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3567 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); 3568 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); 3569 DUMPREG(dispc, i, DISPC_OVL_FIR2); 3570 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); 3571 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); 3572 } 3573 if (dispc_has_feature(dispc, FEAT_ATTR2)) 3574 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); 3575 } 3576 3577 if (dispc->feat->has_writeback) { 3578 i = OMAP_DSS_WB; 3579 DUMPREG(dispc, i, DISPC_OVL_BA0); 3580 DUMPREG(dispc, i, DISPC_OVL_BA1); 3581 DUMPREG(dispc, i, DISPC_OVL_SIZE); 3582 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); 3583 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); 3584 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); 3585 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); 3586 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); 3587 3588 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3589 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); 3590 3591 DUMPREG(dispc, i, DISPC_OVL_FIR); 3592 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); 3593 DUMPREG(dispc, i, DISPC_OVL_ACCU0); 3594 DUMPREG(dispc, i, DISPC_OVL_ACCU1); 3595 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3596 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); 3597 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); 3598 DUMPREG(dispc, i, DISPC_OVL_FIR2); 3599 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); 3600 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); 3601 } 3602 if (dispc_has_feature(dispc, FEAT_ATTR2)) 3603 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); 3604 } 3605 3606 #undef DISPC_REG 3607 #undef DUMPREG 3608 3609 #define DISPC_REG(plane, name, i) name(plane, i) 3610 #define DUMPREG(dispc, plane, name, i) \ 3611 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3612 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3613 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) 3614 3615 /* Video pipeline coefficient registers */ 3616 3617 /* start from OMAP_DSS_VIDEO1 */ 3618 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { 3619 for (j = 0; j < 8; j++) 3620 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); 3621 3622 for (j = 0; j < 8; j++) 3623 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); 3624 3625 for (j = 0; j < 5; j++) 3626 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); 3627 3628 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 3629 for (j = 0; j < 8; j++) 3630 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); 3631 } 3632 3633 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3634 for (j = 0; j < 8; j++) 3635 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); 3636 3637 for (j = 0; j < 8; j++) 3638 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); 3639 3640 for (j = 0; j < 8; j++) 3641 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); 3642 } 3643 } 3644 3645 dispc_runtime_put(dispc); 3646 3647 #undef DISPC_REG 3648 #undef DUMPREG 3649 3650 return 0; 3651 } 3652 3653 /* calculate clock rates using dividers in cinfo */ 3654 int dispc_calc_clock_rates(struct dispc_device *dispc, 3655 unsigned long dispc_fclk_rate, 3656 struct dispc_clock_info *cinfo) 3657 { 3658 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3659 return -EINVAL; 3660 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3661 return -EINVAL; 3662 3663 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3664 cinfo->pck = cinfo->lck / cinfo->pck_div; 3665 3666 return 0; 3667 } 3668 3669 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, 3670 unsigned long pck_min, unsigned long pck_max, 3671 dispc_div_calc_func func, void *data) 3672 { 3673 int lckd, lckd_start, lckd_stop; 3674 int pckd, pckd_start, pckd_stop; 3675 unsigned long pck, lck; 3676 unsigned long lck_max; 3677 unsigned long pckd_hw_min, pckd_hw_max; 3678 unsigned int min_fck_per_pck; 3679 unsigned long fck; 3680 3681 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK 3682 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; 3683 #else 3684 min_fck_per_pck = 0; 3685 #endif 3686 3687 pckd_hw_min = dispc->feat->min_pcd; 3688 pckd_hw_max = 255; 3689 3690 lck_max = dss_get_max_fck_rate(dispc->dss); 3691 3692 pck_min = pck_min ? pck_min : 1; 3693 pck_max = pck_max ? pck_max : ULONG_MAX; 3694 3695 lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul); 3696 lckd_stop = min(dispc_freq / pck_min, 255ul); 3697 3698 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3699 lck = dispc_freq / lckd; 3700 3701 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3702 pckd_stop = min(lck / pck_min, pckd_hw_max); 3703 3704 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3705 pck = lck / pckd; 3706 3707 /* 3708 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3709 * clock, which means we're configuring DISPC fclk here 3710 * also. Thus we need to use the calculated lck. For 3711 * OMAP4+ the DISPC fclk is a separate clock. 3712 */ 3713 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 3714 fck = dispc_core_clk_rate(dispc); 3715 else 3716 fck = lck; 3717 3718 if (fck < pck * min_fck_per_pck) 3719 continue; 3720 3721 if (func(lckd, pckd, lck, pck, data)) 3722 return true; 3723 } 3724 } 3725 3726 return false; 3727 } 3728 3729 void dispc_mgr_set_clock_div(struct dispc_device *dispc, 3730 enum omap_channel channel, 3731 const struct dispc_clock_info *cinfo) 3732 { 3733 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3734 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3735 3736 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, 3737 cinfo->pck_div); 3738 } 3739 3740 int dispc_mgr_get_clock_div(struct dispc_device *dispc, 3741 enum omap_channel channel, 3742 struct dispc_clock_info *cinfo) 3743 { 3744 unsigned long fck; 3745 3746 fck = dispc_fclk_rate(dispc); 3747 3748 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); 3749 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); 3750 3751 cinfo->lck = fck / cinfo->lck_div; 3752 cinfo->pck = cinfo->lck / cinfo->pck_div; 3753 3754 return 0; 3755 } 3756 3757 static u32 dispc_read_irqstatus(struct dispc_device *dispc) 3758 { 3759 return dispc_read_reg(dispc, DISPC_IRQSTATUS); 3760 } 3761 3762 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) 3763 { 3764 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); 3765 } 3766 3767 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) 3768 { 3769 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); 3770 3771 /* clear the irqstatus for newly enabled irqs */ 3772 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); 3773 3774 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); 3775 3776 /* flush posted write */ 3777 dispc_read_reg(dispc, DISPC_IRQENABLE); 3778 } 3779 3780 void dispc_enable_sidle(struct dispc_device *dispc) 3781 { 3782 /* SIDLEMODE: smart idle */ 3783 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); 3784 } 3785 3786 void dispc_disable_sidle(struct dispc_device *dispc) 3787 { 3788 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3789 } 3790 3791 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc, 3792 enum omap_channel channel) 3793 { 3794 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3795 3796 if (!dispc->feat->has_gamma_table) 3797 return 0; 3798 3799 return gdesc->len; 3800 } 3801 3802 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, 3803 enum omap_channel channel) 3804 { 3805 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3806 u32 *table = dispc->gamma_table[channel]; 3807 unsigned int i; 3808 3809 DSSDBG("%s: channel %d\n", __func__, channel); 3810 3811 for (i = 0; i < gdesc->len; ++i) { 3812 u32 v = table[i]; 3813 3814 if (gdesc->has_index) 3815 v |= i << 24; 3816 else if (i == 0) 3817 v |= 1 << 31; 3818 3819 dispc_write_reg(dispc, gdesc->reg, v); 3820 } 3821 } 3822 3823 static void dispc_restore_gamma_tables(struct dispc_device *dispc) 3824 { 3825 DSSDBG("%s()\n", __func__); 3826 3827 if (!dispc->feat->has_gamma_table) 3828 return; 3829 3830 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); 3831 3832 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); 3833 3834 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3835 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); 3836 3837 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3838 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); 3839 } 3840 3841 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 3842 { .red = 0, .green = 0, .blue = 0, }, 3843 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 3844 }; 3845 3846 static void dispc_mgr_set_gamma(struct dispc_device *dispc, 3847 enum omap_channel channel, 3848 const struct drm_color_lut *lut, 3849 unsigned int length) 3850 { 3851 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3852 u32 *table = dispc->gamma_table[channel]; 3853 uint i; 3854 3855 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__, 3856 channel, length, gdesc->len); 3857 3858 if (!dispc->feat->has_gamma_table) 3859 return; 3860 3861 if (lut == NULL || length < 2) { 3862 lut = dispc_mgr_gamma_default_lut; 3863 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut); 3864 } 3865 3866 for (i = 0; i < length - 1; ++i) { 3867 uint first = i * (gdesc->len - 1) / (length - 1); 3868 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); 3869 uint w = last - first; 3870 u16 r, g, b; 3871 uint j; 3872 3873 if (w == 0) 3874 continue; 3875 3876 for (j = 0; j <= w; j++) { 3877 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; 3878 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; 3879 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; 3880 3881 r >>= 16 - gdesc->bits; 3882 g >>= 16 - gdesc->bits; 3883 b >>= 16 - gdesc->bits; 3884 3885 table[first + j] = (r << (gdesc->bits * 2)) | 3886 (g << gdesc->bits) | b; 3887 } 3888 } 3889 3890 if (dispc->is_enabled) 3891 dispc_mgr_write_gamma_table(dispc, channel); 3892 } 3893 3894 static int dispc_init_gamma_tables(struct dispc_device *dispc) 3895 { 3896 int channel; 3897 3898 if (!dispc->feat->has_gamma_table) 3899 return 0; 3900 3901 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { 3902 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3903 u32 *gt; 3904 3905 if (channel == OMAP_DSS_CHANNEL_LCD2 && 3906 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3907 continue; 3908 3909 if (channel == OMAP_DSS_CHANNEL_LCD3 && 3910 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3911 continue; 3912 3913 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, 3914 sizeof(u32), GFP_KERNEL); 3915 if (!gt) 3916 return -ENOMEM; 3917 3918 dispc->gamma_table[channel] = gt; 3919 3920 dispc_mgr_set_gamma(dispc, channel, NULL, 0); 3921 } 3922 return 0; 3923 } 3924 3925 static void _omap_dispc_initial_config(struct dispc_device *dispc) 3926 { 3927 u32 l; 3928 3929 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3930 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { 3931 l = dispc_read_reg(dispc, DISPC_DIVISOR); 3932 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3933 l = FLD_MOD(l, 1, 0, 0); 3934 l = FLD_MOD(l, 1, 23, 16); 3935 dispc_write_reg(dispc, DISPC_DIVISOR, l); 3936 3937 dispc->core_clk_rate = dispc_fclk_rate(dispc); 3938 } 3939 3940 /* Use gamma table mode, instead of palette mode */ 3941 if (dispc->feat->has_gamma_table) 3942 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); 3943 3944 /* For older DSS versions (FEAT_FUNCGATED) this enables 3945 * func-clock auto-gating. For newer versions 3946 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. 3947 */ 3948 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || 3949 dispc->feat->has_gamma_table) 3950 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); 3951 3952 dispc_setup_color_conv_coef(dispc); 3953 3954 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); 3955 3956 dispc_init_fifos(dispc); 3957 3958 dispc_configure_burst_sizes(dispc); 3959 3960 dispc_ovl_enable_zorder_planes(dispc); 3961 3962 if (dispc->feat->mstandby_workaround) 3963 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); 3964 3965 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3966 dispc_init_mflag(dispc); 3967 } 3968 3969 static const enum dispc_feature_id omap2_dispc_features_list[] = { 3970 FEAT_LCDENABLEPOL, 3971 FEAT_LCDENABLESIGNAL, 3972 FEAT_PCKFREEENABLE, 3973 FEAT_FUNCGATED, 3974 FEAT_ROWREPEATENABLE, 3975 FEAT_RESIZECONF, 3976 }; 3977 3978 static const enum dispc_feature_id omap3_dispc_features_list[] = { 3979 FEAT_LCDENABLEPOL, 3980 FEAT_LCDENABLESIGNAL, 3981 FEAT_PCKFREEENABLE, 3982 FEAT_FUNCGATED, 3983 FEAT_LINEBUFFERSPLIT, 3984 FEAT_ROWREPEATENABLE, 3985 FEAT_RESIZECONF, 3986 FEAT_CPR, 3987 FEAT_PRELOAD, 3988 FEAT_FIR_COEF_V, 3989 FEAT_ALPHA_FIXED_ZORDER, 3990 FEAT_FIFO_MERGE, 3991 FEAT_OMAP3_DSI_FIFO_BUG, 3992 }; 3993 3994 static const enum dispc_feature_id am43xx_dispc_features_list[] = { 3995 FEAT_LCDENABLEPOL, 3996 FEAT_LCDENABLESIGNAL, 3997 FEAT_PCKFREEENABLE, 3998 FEAT_FUNCGATED, 3999 FEAT_LINEBUFFERSPLIT, 4000 FEAT_ROWREPEATENABLE, 4001 FEAT_RESIZECONF, 4002 FEAT_CPR, 4003 FEAT_PRELOAD, 4004 FEAT_FIR_COEF_V, 4005 FEAT_ALPHA_FIXED_ZORDER, 4006 FEAT_FIFO_MERGE, 4007 }; 4008 4009 static const enum dispc_feature_id omap4_dispc_features_list[] = { 4010 FEAT_MGR_LCD2, 4011 FEAT_CORE_CLK_DIV, 4012 FEAT_HANDLE_UV_SEPARATE, 4013 FEAT_ATTR2, 4014 FEAT_CPR, 4015 FEAT_PRELOAD, 4016 FEAT_FIR_COEF_V, 4017 FEAT_ALPHA_FREE_ZORDER, 4018 FEAT_FIFO_MERGE, 4019 FEAT_BURST_2D, 4020 }; 4021 4022 static const enum dispc_feature_id omap5_dispc_features_list[] = { 4023 FEAT_MGR_LCD2, 4024 FEAT_MGR_LCD3, 4025 FEAT_CORE_CLK_DIV, 4026 FEAT_HANDLE_UV_SEPARATE, 4027 FEAT_ATTR2, 4028 FEAT_CPR, 4029 FEAT_PRELOAD, 4030 FEAT_FIR_COEF_V, 4031 FEAT_ALPHA_FREE_ZORDER, 4032 FEAT_FIFO_MERGE, 4033 FEAT_BURST_2D, 4034 FEAT_MFLAG, 4035 }; 4036 4037 static const struct dss_reg_field omap2_dispc_reg_fields[] = { 4038 [FEAT_REG_FIRHINC] = { 11, 0 }, 4039 [FEAT_REG_FIRVINC] = { 27, 16 }, 4040 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, 4041 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, 4042 [FEAT_REG_FIFOSIZE] = { 8, 0 }, 4043 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 4044 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 4045 }; 4046 4047 static const struct dss_reg_field omap3_dispc_reg_fields[] = { 4048 [FEAT_REG_FIRHINC] = { 12, 0 }, 4049 [FEAT_REG_FIRVINC] = { 28, 16 }, 4050 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, 4051 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, 4052 [FEAT_REG_FIFOSIZE] = { 10, 0 }, 4053 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 4054 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 4055 }; 4056 4057 static const struct dss_reg_field omap4_dispc_reg_fields[] = { 4058 [FEAT_REG_FIRHINC] = { 12, 0 }, 4059 [FEAT_REG_FIRVINC] = { 28, 16 }, 4060 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, 4061 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, 4062 [FEAT_REG_FIFOSIZE] = { 15, 0 }, 4063 [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, 4064 [FEAT_REG_VERTICALACCU] = { 26, 16 }, 4065 }; 4066 4067 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { 4068 /* OMAP_DSS_GFX */ 4069 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4070 4071 /* OMAP_DSS_VIDEO1 */ 4072 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4073 OMAP_DSS_OVL_CAP_REPLICATION, 4074 4075 /* OMAP_DSS_VIDEO2 */ 4076 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4077 OMAP_DSS_OVL_CAP_REPLICATION, 4078 }; 4079 4080 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = { 4081 /* OMAP_DSS_GFX */ 4082 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | 4083 OMAP_DSS_OVL_CAP_REPLICATION, 4084 4085 /* OMAP_DSS_VIDEO1 */ 4086 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4087 OMAP_DSS_OVL_CAP_REPLICATION, 4088 4089 /* OMAP_DSS_VIDEO2 */ 4090 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4091 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4092 }; 4093 4094 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = { 4095 /* OMAP_DSS_GFX */ 4096 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 4097 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4098 4099 /* OMAP_DSS_VIDEO1 */ 4100 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4101 OMAP_DSS_OVL_CAP_REPLICATION, 4102 4103 /* OMAP_DSS_VIDEO2 */ 4104 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4105 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | 4106 OMAP_DSS_OVL_CAP_REPLICATION, 4107 }; 4108 4109 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = { 4110 /* OMAP_DSS_GFX */ 4111 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 4112 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | 4113 OMAP_DSS_OVL_CAP_REPLICATION, 4114 4115 /* OMAP_DSS_VIDEO1 */ 4116 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4117 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4118 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4119 4120 /* OMAP_DSS_VIDEO2 */ 4121 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4122 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4123 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4124 4125 /* OMAP_DSS_VIDEO3 */ 4126 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4127 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4128 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4129 }; 4130 4131 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } 4132 4133 static const u32 *omap2_dispc_supported_color_modes[] = { 4134 4135 /* OMAP_DSS_GFX */ 4136 COLOR_ARRAY( 4137 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 4138 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), 4139 4140 /* OMAP_DSS_VIDEO1 */ 4141 COLOR_ARRAY( 4142 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4143 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4144 DRM_FORMAT_UYVY), 4145 4146 /* OMAP_DSS_VIDEO2 */ 4147 COLOR_ARRAY( 4148 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4149 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4150 DRM_FORMAT_UYVY), 4151 }; 4152 4153 static const u32 *omap3_dispc_supported_color_modes[] = { 4154 /* OMAP_DSS_GFX */ 4155 COLOR_ARRAY( 4156 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4157 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4158 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 4159 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 4160 4161 /* OMAP_DSS_VIDEO1 */ 4162 COLOR_ARRAY( 4163 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, 4164 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 4165 DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), 4166 4167 /* OMAP_DSS_VIDEO2 */ 4168 COLOR_ARRAY( 4169 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4170 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4171 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4172 DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, 4173 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 4174 }; 4175 4176 static const u32 *omap4_dispc_supported_color_modes[] = { 4177 /* OMAP_DSS_GFX */ 4178 COLOR_ARRAY( 4179 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4180 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4181 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 4182 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, 4183 DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, 4184 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), 4185 4186 /* OMAP_DSS_VIDEO1 */ 4187 COLOR_ARRAY( 4188 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4189 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4190 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4191 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4192 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4193 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4194 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4195 DRM_FORMAT_RGBX8888), 4196 4197 /* OMAP_DSS_VIDEO2 */ 4198 COLOR_ARRAY( 4199 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4200 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4201 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4202 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4203 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4204 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4205 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4206 DRM_FORMAT_RGBX8888), 4207 4208 /* OMAP_DSS_VIDEO3 */ 4209 COLOR_ARRAY( 4210 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4211 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4212 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4213 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4214 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4215 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4216 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4217 DRM_FORMAT_RGBX8888), 4218 4219 /* OMAP_DSS_WB */ 4220 COLOR_ARRAY( 4221 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4222 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4223 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4224 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4225 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4226 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4227 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4228 DRM_FORMAT_RGBX8888), 4229 }; 4230 4231 static const u32 omap3_dispc_supported_scaler_color_modes[] = { 4232 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_YUYV, 4233 DRM_FORMAT_UYVY, 4234 0, 4235 }; 4236 4237 static const struct dispc_features omap24xx_dispc_feats = { 4238 .sw_start = 5, 4239 .fp_start = 15, 4240 .bp_start = 27, 4241 .sw_max = 64, 4242 .vp_max = 255, 4243 .hp_max = 256, 4244 .mgr_width_start = 10, 4245 .mgr_height_start = 26, 4246 .mgr_width_max = 2048, 4247 .mgr_height_max = 2048, 4248 .max_lcd_pclk = 66500000, 4249 .max_downscale = 2, 4250 /* 4251 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler 4252 * cannot scale an image width larger than 768. 4253 */ 4254 .max_line_width = 768, 4255 .min_pcd = 2, 4256 .calc_scaling = dispc_ovl_calc_scaling_24xx, 4257 .calc_core_clk = calc_core_clk_24xx, 4258 .num_fifos = 3, 4259 .features = omap2_dispc_features_list, 4260 .num_features = ARRAY_SIZE(omap2_dispc_features_list), 4261 .reg_fields = omap2_dispc_reg_fields, 4262 .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields), 4263 .overlay_caps = omap2_dispc_overlay_caps, 4264 .supported_color_modes = omap2_dispc_supported_color_modes, 4265 .supported_scaler_color_modes = COLOR_ARRAY(DRM_FORMAT_XRGB8888), 4266 .num_mgrs = 2, 4267 .num_ovls = 3, 4268 .buffer_size_unit = 1, 4269 .burst_size_unit = 8, 4270 .no_framedone_tv = true, 4271 .set_max_preload = false, 4272 .last_pixel_inc_missing = true, 4273 }; 4274 4275 static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 4276 .sw_start = 5, 4277 .fp_start = 15, 4278 .bp_start = 27, 4279 .sw_max = 64, 4280 .vp_max = 255, 4281 .hp_max = 256, 4282 .mgr_width_start = 10, 4283 .mgr_height_start = 26, 4284 .mgr_width_max = 2048, 4285 .mgr_height_max = 2048, 4286 .max_lcd_pclk = 173000000, 4287 .max_tv_pclk = 59000000, 4288 .max_downscale = 4, 4289 .max_line_width = 1024, 4290 .min_pcd = 1, 4291 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4292 .calc_core_clk = calc_core_clk_34xx, 4293 .num_fifos = 3, 4294 .features = omap3_dispc_features_list, 4295 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4296 .reg_fields = omap3_dispc_reg_fields, 4297 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4298 .overlay_caps = omap3430_dispc_overlay_caps, 4299 .supported_color_modes = omap3_dispc_supported_color_modes, 4300 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4301 .num_mgrs = 2, 4302 .num_ovls = 3, 4303 .buffer_size_unit = 1, 4304 .burst_size_unit = 8, 4305 .no_framedone_tv = true, 4306 .set_max_preload = false, 4307 .last_pixel_inc_missing = true, 4308 }; 4309 4310 static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 4311 .sw_start = 7, 4312 .fp_start = 19, 4313 .bp_start = 31, 4314 .sw_max = 256, 4315 .vp_max = 4095, 4316 .hp_max = 4096, 4317 .mgr_width_start = 10, 4318 .mgr_height_start = 26, 4319 .mgr_width_max = 2048, 4320 .mgr_height_max = 2048, 4321 .max_lcd_pclk = 173000000, 4322 .max_tv_pclk = 59000000, 4323 .max_downscale = 4, 4324 .max_line_width = 1024, 4325 .min_pcd = 1, 4326 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4327 .calc_core_clk = calc_core_clk_34xx, 4328 .num_fifos = 3, 4329 .features = omap3_dispc_features_list, 4330 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4331 .reg_fields = omap3_dispc_reg_fields, 4332 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4333 .overlay_caps = omap3430_dispc_overlay_caps, 4334 .supported_color_modes = omap3_dispc_supported_color_modes, 4335 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4336 .num_mgrs = 2, 4337 .num_ovls = 3, 4338 .buffer_size_unit = 1, 4339 .burst_size_unit = 8, 4340 .no_framedone_tv = true, 4341 .set_max_preload = false, 4342 .last_pixel_inc_missing = true, 4343 }; 4344 4345 static const struct dispc_features omap36xx_dispc_feats = { 4346 .sw_start = 7, 4347 .fp_start = 19, 4348 .bp_start = 31, 4349 .sw_max = 256, 4350 .vp_max = 4095, 4351 .hp_max = 4096, 4352 .mgr_width_start = 10, 4353 .mgr_height_start = 26, 4354 .mgr_width_max = 2048, 4355 .mgr_height_max = 2048, 4356 .max_lcd_pclk = 173000000, 4357 .max_tv_pclk = 59000000, 4358 .max_downscale = 4, 4359 .max_line_width = 1024, 4360 .min_pcd = 1, 4361 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4362 .calc_core_clk = calc_core_clk_34xx, 4363 .num_fifos = 3, 4364 .features = omap3_dispc_features_list, 4365 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4366 .reg_fields = omap3_dispc_reg_fields, 4367 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4368 .overlay_caps = omap3630_dispc_overlay_caps, 4369 .supported_color_modes = omap3_dispc_supported_color_modes, 4370 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4371 .num_mgrs = 2, 4372 .num_ovls = 3, 4373 .buffer_size_unit = 1, 4374 .burst_size_unit = 8, 4375 .no_framedone_tv = true, 4376 .set_max_preload = false, 4377 .last_pixel_inc_missing = true, 4378 }; 4379 4380 static const struct dispc_features am43xx_dispc_feats = { 4381 .sw_start = 7, 4382 .fp_start = 19, 4383 .bp_start = 31, 4384 .sw_max = 256, 4385 .vp_max = 4095, 4386 .hp_max = 4096, 4387 .mgr_width_start = 10, 4388 .mgr_height_start = 26, 4389 .mgr_width_max = 2048, 4390 .mgr_height_max = 2048, 4391 .max_lcd_pclk = 173000000, 4392 .max_tv_pclk = 59000000, 4393 .max_downscale = 4, 4394 .max_line_width = 1024, 4395 .min_pcd = 1, 4396 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4397 .calc_core_clk = calc_core_clk_34xx, 4398 .num_fifos = 3, 4399 .features = am43xx_dispc_features_list, 4400 .num_features = ARRAY_SIZE(am43xx_dispc_features_list), 4401 .reg_fields = omap3_dispc_reg_fields, 4402 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4403 .overlay_caps = omap3430_dispc_overlay_caps, 4404 .supported_color_modes = omap3_dispc_supported_color_modes, 4405 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4406 .num_mgrs = 1, 4407 .num_ovls = 3, 4408 .buffer_size_unit = 1, 4409 .burst_size_unit = 8, 4410 .no_framedone_tv = true, 4411 .set_max_preload = false, 4412 .last_pixel_inc_missing = true, 4413 }; 4414 4415 static const struct dispc_features omap44xx_dispc_feats = { 4416 .sw_start = 7, 4417 .fp_start = 19, 4418 .bp_start = 31, 4419 .sw_max = 256, 4420 .vp_max = 4095, 4421 .hp_max = 4096, 4422 .mgr_width_start = 10, 4423 .mgr_height_start = 26, 4424 .mgr_width_max = 2048, 4425 .mgr_height_max = 2048, 4426 .max_lcd_pclk = 170000000, 4427 .max_tv_pclk = 185625000, 4428 .max_downscale = 4, 4429 .max_line_width = 2048, 4430 .min_pcd = 1, 4431 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4432 .calc_core_clk = calc_core_clk_44xx, 4433 .num_fifos = 5, 4434 .features = omap4_dispc_features_list, 4435 .num_features = ARRAY_SIZE(omap4_dispc_features_list), 4436 .reg_fields = omap4_dispc_reg_fields, 4437 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4438 .overlay_caps = omap4_dispc_overlay_caps, 4439 .supported_color_modes = omap4_dispc_supported_color_modes, 4440 .num_mgrs = 3, 4441 .num_ovls = 4, 4442 .buffer_size_unit = 16, 4443 .burst_size_unit = 16, 4444 .gfx_fifo_workaround = true, 4445 .set_max_preload = true, 4446 .supports_sync_align = true, 4447 .has_writeback = true, 4448 .supports_double_pixel = true, 4449 .reverse_ilace_field_order = true, 4450 .has_gamma_table = true, 4451 .has_gamma_i734_bug = true, 4452 }; 4453 4454 static const struct dispc_features omap54xx_dispc_feats = { 4455 .sw_start = 7, 4456 .fp_start = 19, 4457 .bp_start = 31, 4458 .sw_max = 256, 4459 .vp_max = 4095, 4460 .hp_max = 4096, 4461 .mgr_width_start = 11, 4462 .mgr_height_start = 27, 4463 .mgr_width_max = 4096, 4464 .mgr_height_max = 4096, 4465 .max_lcd_pclk = 170000000, 4466 .max_tv_pclk = 186000000, 4467 .max_downscale = 4, 4468 .max_line_width = 2048, 4469 .min_pcd = 1, 4470 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4471 .calc_core_clk = calc_core_clk_44xx, 4472 .num_fifos = 5, 4473 .features = omap5_dispc_features_list, 4474 .num_features = ARRAY_SIZE(omap5_dispc_features_list), 4475 .reg_fields = omap4_dispc_reg_fields, 4476 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4477 .overlay_caps = omap4_dispc_overlay_caps, 4478 .supported_color_modes = omap4_dispc_supported_color_modes, 4479 .num_mgrs = 4, 4480 .num_ovls = 4, 4481 .buffer_size_unit = 16, 4482 .burst_size_unit = 16, 4483 .gfx_fifo_workaround = true, 4484 .mstandby_workaround = true, 4485 .set_max_preload = true, 4486 .supports_sync_align = true, 4487 .has_writeback = true, 4488 .supports_double_pixel = true, 4489 .reverse_ilace_field_order = true, 4490 .has_gamma_table = true, 4491 .has_gamma_i734_bug = true, 4492 }; 4493 4494 static irqreturn_t dispc_irq_handler(int irq, void *arg) 4495 { 4496 struct dispc_device *dispc = arg; 4497 4498 if (!dispc->is_enabled) 4499 return IRQ_NONE; 4500 4501 return dispc->user_handler(irq, dispc->user_data); 4502 } 4503 4504 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, 4505 void *dev_id) 4506 { 4507 int r; 4508 4509 if (dispc->user_handler != NULL) 4510 return -EBUSY; 4511 4512 dispc->user_handler = handler; 4513 dispc->user_data = dev_id; 4514 4515 /* ensure the dispc_irq_handler sees the values above */ 4516 smp_wmb(); 4517 4518 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, 4519 IRQF_SHARED, "OMAP DISPC", dispc); 4520 if (r) { 4521 dispc->user_handler = NULL; 4522 dispc->user_data = NULL; 4523 } 4524 4525 return r; 4526 } 4527 4528 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) 4529 { 4530 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); 4531 4532 dispc->user_handler = NULL; 4533 dispc->user_data = NULL; 4534 } 4535 4536 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) 4537 { 4538 u32 limit = 0; 4539 4540 /* Optional maximum memory bandwidth */ 4541 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", 4542 &limit); 4543 4544 return limit; 4545 } 4546 4547 /* 4548 * Workaround for errata i734 in DSS dispc 4549 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled 4550 * 4551 * For gamma tables to work on LCD1 the GFX plane has to be used at 4552 * least once after DSS HW has come out of reset. The workaround 4553 * sets up a minimal LCD setup with GFX plane and waits for one 4554 * vertical sync irq before disabling the setup and continuing with 4555 * the context restore. The physical outputs are gated during the 4556 * operation. This workaround requires that gamma table's LOADMODE 4557 * is set to 0x2 in DISPC_CONTROL1 register. 4558 * 4559 * For details see: 4560 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata 4561 * Literature Number: SWPZ037E 4562 * Or some other relevant errata document for the DSS IP version. 4563 */ 4564 4565 static const struct dispc_errata_i734_data { 4566 struct videomode vm; 4567 struct omap_overlay_info ovli; 4568 struct omap_overlay_manager_info mgri; 4569 struct dss_lcd_mgr_config lcd_conf; 4570 } i734 = { 4571 .vm = { 4572 .hactive = 8, .vactive = 1, 4573 .pixelclock = 16000000, 4574 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 4575 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, 4576 4577 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4578 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE | 4579 DISPLAY_FLAGS_PIXDATA_POSEDGE, 4580 }, 4581 .ovli = { 4582 .screen_width = 1, 4583 .width = 1, .height = 1, 4584 .fourcc = DRM_FORMAT_XRGB8888, 4585 .rotation = DRM_MODE_ROTATE_0, 4586 .rotation_type = OMAP_DSS_ROT_NONE, 4587 .pos_x = 0, .pos_y = 0, 4588 .out_width = 0, .out_height = 0, 4589 .global_alpha = 0xff, 4590 .pre_mult_alpha = 0, 4591 .zorder = 0, 4592 }, 4593 .mgri = { 4594 .default_color = 0, 4595 .trans_enabled = false, 4596 .partial_alpha_enabled = false, 4597 .cpr_enable = false, 4598 }, 4599 .lcd_conf = { 4600 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS, 4601 .stallmode = false, 4602 .fifohandcheck = false, 4603 .clock_info = { 4604 .lck_div = 1, 4605 .pck_div = 2, 4606 }, 4607 .video_port_width = 24, 4608 .lcden_sig_polarity = 0, 4609 }, 4610 }; 4611 4612 static struct i734_buf { 4613 size_t size; 4614 dma_addr_t paddr; 4615 void *vaddr; 4616 } i734_buf; 4617 4618 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) 4619 { 4620 if (!dispc->feat->has_gamma_i734_bug) 4621 return 0; 4622 4623 i734_buf.size = i734.ovli.width * i734.ovli.height * 4624 color_mode_to_bpp(i734.ovli.fourcc) / 8; 4625 4626 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, 4627 &i734_buf.paddr, GFP_KERNEL); 4628 if (!i734_buf.vaddr) { 4629 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", 4630 __func__); 4631 return -ENOMEM; 4632 } 4633 4634 return 0; 4635 } 4636 4637 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) 4638 { 4639 if (!dispc->feat->has_gamma_i734_bug) 4640 return; 4641 4642 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, 4643 i734_buf.paddr); 4644 } 4645 4646 static void dispc_errata_i734_wa(struct dispc_device *dispc) 4647 { 4648 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, 4649 OMAP_DSS_CHANNEL_LCD); 4650 struct omap_overlay_info ovli; 4651 struct dss_lcd_mgr_config lcd_conf; 4652 u32 gatestate; 4653 unsigned int count; 4654 4655 if (!dispc->feat->has_gamma_i734_bug) 4656 return; 4657 4658 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); 4659 4660 ovli = i734.ovli; 4661 ovli.paddr = i734_buf.paddr; 4662 lcd_conf = i734.lcd_conf; 4663 4664 /* Gate all LCD1 outputs */ 4665 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); 4666 4667 /* Setup and enable GFX plane */ 4668 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, 4669 OMAP_DSS_CHANNEL_LCD); 4670 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); 4671 4672 /* Set up and enable display manager for LCD1 */ 4673 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); 4674 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), 4675 &lcd_conf.clock_info); 4676 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4677 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); 4678 4679 dispc_clear_irqstatus(dispc, framedone_irq); 4680 4681 /* Enable and shut the channel to produce just one frame */ 4682 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); 4683 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); 4684 4685 /* Busy wait for framedone. We can't fiddle with irq handlers 4686 * in PM resume. Typically the loop runs less than 5 times and 4687 * waits less than a micro second. 4688 */ 4689 count = 0; 4690 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { 4691 if (count++ > 10000) { 4692 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", 4693 __func__); 4694 break; 4695 } 4696 } 4697 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); 4698 4699 /* Clear all irq bits before continuing */ 4700 dispc_clear_irqstatus(dispc, 0xffffffff); 4701 4702 /* Restore the original state to LCD1 output gates */ 4703 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); 4704 } 4705 4706 static const struct dispc_ops dispc_ops = { 4707 .read_irqstatus = dispc_read_irqstatus, 4708 .clear_irqstatus = dispc_clear_irqstatus, 4709 .write_irqenable = dispc_write_irqenable, 4710 4711 .request_irq = dispc_request_irq, 4712 .free_irq = dispc_free_irq, 4713 4714 .runtime_get = dispc_runtime_get, 4715 .runtime_put = dispc_runtime_put, 4716 4717 .get_num_ovls = dispc_get_num_ovls, 4718 .get_num_mgrs = dispc_get_num_mgrs, 4719 4720 .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit, 4721 4722 .mgr_enable = dispc_mgr_enable, 4723 .mgr_is_enabled = dispc_mgr_is_enabled, 4724 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, 4725 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq, 4726 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq, 4727 .mgr_go_busy = dispc_mgr_go_busy, 4728 .mgr_go = dispc_mgr_go, 4729 .mgr_set_lcd_config = dispc_mgr_set_lcd_config, 4730 .mgr_check_timings = dispc_mgr_check_timings, 4731 .mgr_set_timings = dispc_mgr_set_timings, 4732 .mgr_setup = dispc_mgr_setup, 4733 .mgr_gamma_size = dispc_mgr_gamma_size, 4734 .mgr_set_gamma = dispc_mgr_set_gamma, 4735 4736 .ovl_enable = dispc_ovl_enable, 4737 .ovl_setup = dispc_ovl_setup, 4738 .ovl_get_color_modes = dispc_ovl_get_color_modes, 4739 4740 .wb_get_framedone_irq = dispc_wb_get_framedone_irq, 4741 .wb_setup = dispc_wb_setup, 4742 .has_writeback = dispc_has_writeback, 4743 .wb_go_busy = dispc_wb_go_busy, 4744 .wb_go = dispc_wb_go, 4745 }; 4746 4747 /* DISPC HW IP initialisation */ 4748 static const struct of_device_id dispc_of_match[] = { 4749 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats }, 4750 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats }, 4751 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats }, 4752 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats }, 4753 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats }, 4754 {}, 4755 }; 4756 4757 static const struct soc_device_attribute dispc_soc_devices[] = { 4758 { .machine = "OMAP3[45]*", 4759 .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, 4760 { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, 4761 { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, 4762 { .machine = "AM43*", .data = &am43xx_dispc_feats }, 4763 { /* sentinel */ } 4764 }; 4765 4766 static int dispc_bind(struct device *dev, struct device *master, void *data) 4767 { 4768 struct platform_device *pdev = to_platform_device(dev); 4769 const struct soc_device_attribute *soc; 4770 struct dss_device *dss = dss_get_device(master); 4771 struct dispc_device *dispc; 4772 u32 rev; 4773 int r = 0; 4774 struct resource *dispc_mem; 4775 struct device_node *np = pdev->dev.of_node; 4776 4777 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); 4778 if (!dispc) 4779 return -ENOMEM; 4780 4781 dispc->pdev = pdev; 4782 platform_set_drvdata(pdev, dispc); 4783 dispc->dss = dss; 4784 4785 /* 4786 * The OMAP3-based models can't be told apart using the compatible 4787 * string, use SoC device matching. 4788 */ 4789 soc = soc_device_match(dispc_soc_devices); 4790 if (soc) 4791 dispc->feat = soc->data; 4792 else 4793 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; 4794 4795 r = dispc_errata_i734_wa_init(dispc); 4796 if (r) 4797 goto err_free; 4798 4799 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); 4800 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); 4801 if (IS_ERR(dispc->base)) { 4802 r = PTR_ERR(dispc->base); 4803 goto err_free; 4804 } 4805 4806 dispc->irq = platform_get_irq(dispc->pdev, 0); 4807 if (dispc->irq < 0) { 4808 DSSERR("platform_get_irq failed\n"); 4809 r = -ENODEV; 4810 goto err_free; 4811 } 4812 4813 if (np && of_property_read_bool(np, "syscon-pol")) { 4814 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 4815 if (IS_ERR(dispc->syscon_pol)) { 4816 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 4817 r = PTR_ERR(dispc->syscon_pol); 4818 goto err_free; 4819 } 4820 4821 if (of_property_read_u32_index(np, "syscon-pol", 1, 4822 &dispc->syscon_pol_offset)) { 4823 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 4824 r = -EINVAL; 4825 goto err_free; 4826 } 4827 } 4828 4829 r = dispc_init_gamma_tables(dispc); 4830 if (r) 4831 goto err_free; 4832 4833 pm_runtime_enable(&pdev->dev); 4834 4835 r = dispc_runtime_get(dispc); 4836 if (r) 4837 goto err_runtime_get; 4838 4839 _omap_dispc_initial_config(dispc); 4840 4841 rev = dispc_read_reg(dispc, DISPC_REVISION); 4842 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 4843 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4844 4845 dispc_runtime_put(dispc); 4846 4847 dss->dispc = dispc; 4848 dss->dispc_ops = &dispc_ops; 4849 4850 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, 4851 dispc); 4852 4853 return 0; 4854 4855 err_runtime_get: 4856 pm_runtime_disable(&pdev->dev); 4857 err_free: 4858 kfree(dispc); 4859 return r; 4860 } 4861 4862 static void dispc_unbind(struct device *dev, struct device *master, void *data) 4863 { 4864 struct dispc_device *dispc = dev_get_drvdata(dev); 4865 struct dss_device *dss = dispc->dss; 4866 4867 dss_debugfs_remove_file(dispc->debugfs); 4868 4869 dss->dispc = NULL; 4870 dss->dispc_ops = NULL; 4871 4872 pm_runtime_disable(dev); 4873 4874 dispc_errata_i734_wa_fini(dispc); 4875 4876 kfree(dispc); 4877 } 4878 4879 static const struct component_ops dispc_component_ops = { 4880 .bind = dispc_bind, 4881 .unbind = dispc_unbind, 4882 }; 4883 4884 static int dispc_probe(struct platform_device *pdev) 4885 { 4886 return component_add(&pdev->dev, &dispc_component_ops); 4887 } 4888 4889 static int dispc_remove(struct platform_device *pdev) 4890 { 4891 component_del(&pdev->dev, &dispc_component_ops); 4892 return 0; 4893 } 4894 4895 static int dispc_runtime_suspend(struct device *dev) 4896 { 4897 struct dispc_device *dispc = dev_get_drvdata(dev); 4898 4899 dispc->is_enabled = false; 4900 /* ensure the dispc_irq_handler sees the is_enabled value */ 4901 smp_wmb(); 4902 /* wait for current handler to finish before turning the DISPC off */ 4903 synchronize_irq(dispc->irq); 4904 4905 dispc_save_context(dispc); 4906 4907 return 0; 4908 } 4909 4910 static int dispc_runtime_resume(struct device *dev) 4911 { 4912 struct dispc_device *dispc = dev_get_drvdata(dev); 4913 4914 /* 4915 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4916 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4917 * _omap_dispc_initial_config(). We can thus use it to detect if 4918 * we have lost register context. 4919 */ 4920 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4921 _omap_dispc_initial_config(dispc); 4922 4923 dispc_errata_i734_wa(dispc); 4924 4925 dispc_restore_context(dispc); 4926 4927 dispc_restore_gamma_tables(dispc); 4928 } 4929 4930 dispc->is_enabled = true; 4931 /* ensure the dispc_irq_handler sees the is_enabled value */ 4932 smp_wmb(); 4933 4934 return 0; 4935 } 4936 4937 static const struct dev_pm_ops dispc_pm_ops = { 4938 .runtime_suspend = dispc_runtime_suspend, 4939 .runtime_resume = dispc_runtime_resume, 4940 }; 4941 4942 struct platform_driver omap_dispchw_driver = { 4943 .probe = dispc_probe, 4944 .remove = dispc_remove, 4945 .driver = { 4946 .name = "omapdss_dispc", 4947 .pm = &dispc_pm_ops, 4948 .of_match_table = dispc_of_match, 4949 .suppress_bind_attrs = true, 4950 }, 4951 }; 4952