1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 * 6 * Some code and ideas taken from drivers/video/omap/ driver 7 * by Imre Deak. 8 */ 9 10 #define DSS_SUBSYS_NAME "DISPC" 11 12 #include <linux/kernel.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/vmalloc.h> 15 #include <linux/export.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/jiffies.h> 19 #include <linux/seq_file.h> 20 #include <linux/delay.h> 21 #include <linux/workqueue.h> 22 #include <linux/hardirq.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/sizes.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/regmap.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/component.h> 31 #include <linux/sys_soc.h> 32 #include <drm/drm_fourcc.h> 33 #include <drm/drm_blend.h> 34 35 #include "omapdss.h" 36 #include "dss.h" 37 #include "dispc.h" 38 39 struct dispc_device; 40 41 /* DISPC */ 42 #define DISPC_SZ_REGS SZ_4K 43 44 enum omap_burst_size { 45 BURST_SIZE_X2 = 0, 46 BURST_SIZE_X4 = 1, 47 BURST_SIZE_X8 = 2, 48 }; 49 50 #define REG_GET(dispc, idx, start, end) \ 51 FLD_GET(dispc_read_reg(dispc, idx), start, end) 52 53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ 54 dispc_write_reg(dispc, idx, \ 55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end)) 56 57 /* DISPC has feature id */ 58 enum dispc_feature_id { 59 FEAT_LCDENABLEPOL, 60 FEAT_LCDENABLESIGNAL, 61 FEAT_PCKFREEENABLE, 62 FEAT_FUNCGATED, 63 FEAT_MGR_LCD2, 64 FEAT_MGR_LCD3, 65 FEAT_LINEBUFFERSPLIT, 66 FEAT_ROWREPEATENABLE, 67 FEAT_RESIZECONF, 68 /* Independent core clk divider */ 69 FEAT_CORE_CLK_DIV, 70 FEAT_HANDLE_UV_SEPARATE, 71 FEAT_ATTR2, 72 FEAT_CPR, 73 FEAT_PRELOAD, 74 FEAT_FIR_COEF_V, 75 FEAT_ALPHA_FIXED_ZORDER, 76 FEAT_ALPHA_FREE_ZORDER, 77 FEAT_FIFO_MERGE, 78 /* An unknown HW bug causing the normal FIFO thresholds not to work */ 79 FEAT_OMAP3_DSI_FIFO_BUG, 80 FEAT_BURST_2D, 81 FEAT_MFLAG, 82 }; 83 84 struct dispc_features { 85 u8 sw_start; 86 u8 fp_start; 87 u8 bp_start; 88 u16 sw_max; 89 u16 vp_max; 90 u16 hp_max; 91 u8 mgr_width_start; 92 u8 mgr_height_start; 93 u16 mgr_width_max; 94 u16 mgr_height_max; 95 u16 ovl_width_max; 96 u16 ovl_height_max; 97 unsigned long max_lcd_pclk; 98 unsigned long max_tv_pclk; 99 unsigned int max_downscale; 100 unsigned int max_line_width; 101 unsigned int min_pcd; 102 int (*calc_scaling)(struct dispc_device *dispc, 103 unsigned long pclk, unsigned long lclk, 104 const struct videomode *vm, 105 u16 width, u16 height, u16 out_width, u16 out_height, 106 u32 fourcc, bool *five_taps, 107 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 108 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 109 unsigned long (*calc_core_clk) (unsigned long pclk, 110 u16 width, u16 height, u16 out_width, u16 out_height, 111 bool mem_to_mem); 112 u8 num_fifos; 113 const enum dispc_feature_id *features; 114 unsigned int num_features; 115 const struct dss_reg_field *reg_fields; 116 const unsigned int num_reg_fields; 117 const enum omap_overlay_caps *overlay_caps; 118 const u32 **supported_color_modes; 119 const u32 *supported_scaler_color_modes; 120 unsigned int num_mgrs; 121 unsigned int num_ovls; 122 unsigned int buffer_size_unit; 123 unsigned int burst_size_unit; 124 125 /* swap GFX & WB fifos */ 126 bool gfx_fifo_workaround:1; 127 128 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 129 bool no_framedone_tv:1; 130 131 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 132 bool mstandby_workaround:1; 133 134 bool set_max_preload:1; 135 136 /* PIXEL_INC is not added to the last pixel of a line */ 137 bool last_pixel_inc_missing:1; 138 139 /* POL_FREQ has ALIGN bit */ 140 bool supports_sync_align:1; 141 142 bool has_writeback:1; 143 144 bool supports_double_pixel:1; 145 146 /* 147 * Field order for VENC is different than HDMI. We should handle this in 148 * some intelligent manner, but as the SoCs have either HDMI or VENC, 149 * never both, we can just use this flag for now. 150 */ 151 bool reverse_ilace_field_order:1; 152 153 bool has_gamma_table:1; 154 155 bool has_gamma_i734_bug:1; 156 }; 157 158 #define DISPC_MAX_NR_FIFOS 5 159 #define DISPC_MAX_CHANNEL_GAMMA 4 160 161 struct dispc_device { 162 struct platform_device *pdev; 163 void __iomem *base; 164 struct dss_device *dss; 165 166 struct dss_debugfs_entry *debugfs; 167 168 int irq; 169 irq_handler_t user_handler; 170 void *user_data; 171 172 unsigned long core_clk_rate; 173 unsigned long tv_pclk_rate; 174 175 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 176 /* maps which plane is using a fifo. fifo-id -> plane-id */ 177 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 178 179 bool ctx_valid; 180 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 181 182 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA]; 183 184 const struct dispc_features *feat; 185 186 bool is_enabled; 187 188 struct regmap *syscon_pol; 189 u32 syscon_pol_offset; 190 }; 191 192 enum omap_color_component { 193 /* used for all color formats for OMAP3 and earlier 194 * and for RGB and Y color component on OMAP4 195 */ 196 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 197 /* used for UV component for 198 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12 199 * color formats on OMAP4 200 */ 201 DISPC_COLOR_COMPONENT_UV = 1 << 1, 202 }; 203 204 enum mgr_reg_fields { 205 DISPC_MGR_FLD_ENABLE, 206 DISPC_MGR_FLD_STNTFT, 207 DISPC_MGR_FLD_GO, 208 DISPC_MGR_FLD_TFTDATALINES, 209 DISPC_MGR_FLD_STALLMODE, 210 DISPC_MGR_FLD_TCKENABLE, 211 DISPC_MGR_FLD_TCKSELECTION, 212 DISPC_MGR_FLD_CPR, 213 DISPC_MGR_FLD_FIFOHANDCHECK, 214 /* used to maintain a count of the above fields */ 215 DISPC_MGR_FLD_NUM, 216 }; 217 218 /* DISPC register field id */ 219 enum dispc_feat_reg_field { 220 FEAT_REG_FIRHINC, 221 FEAT_REG_FIRVINC, 222 FEAT_REG_FIFOHIGHTHRESHOLD, 223 FEAT_REG_FIFOLOWTHRESHOLD, 224 FEAT_REG_FIFOSIZE, 225 FEAT_REG_HORIZONTALACCU, 226 FEAT_REG_VERTICALACCU, 227 }; 228 229 struct dispc_reg_field { 230 u16 reg; 231 u8 high; 232 u8 low; 233 }; 234 235 struct dispc_gamma_desc { 236 u32 len; 237 u32 bits; 238 u16 reg; 239 bool has_index; 240 }; 241 242 static const struct { 243 const char *name; 244 u32 vsync_irq; 245 u32 framedone_irq; 246 u32 sync_lost_irq; 247 struct dispc_gamma_desc gamma; 248 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 249 } mgr_desc[] = { 250 [OMAP_DSS_CHANNEL_LCD] = { 251 .name = "LCD", 252 .vsync_irq = DISPC_IRQ_VSYNC, 253 .framedone_irq = DISPC_IRQ_FRAMEDONE, 254 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 255 .gamma = { 256 .len = 256, 257 .bits = 8, 258 .reg = DISPC_GAMMA_TABLE0, 259 .has_index = true, 260 }, 261 .reg_desc = { 262 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 263 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 264 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 265 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 266 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 267 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 268 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 269 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 270 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 271 }, 272 }, 273 [OMAP_DSS_CHANNEL_DIGIT] = { 274 .name = "DIGIT", 275 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 276 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 277 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 278 .gamma = { 279 .len = 1024, 280 .bits = 10, 281 .reg = DISPC_GAMMA_TABLE2, 282 .has_index = false, 283 }, 284 .reg_desc = { 285 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 286 [DISPC_MGR_FLD_STNTFT] = { }, 287 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 288 [DISPC_MGR_FLD_TFTDATALINES] = { }, 289 [DISPC_MGR_FLD_STALLMODE] = { }, 290 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 291 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 292 [DISPC_MGR_FLD_CPR] = { }, 293 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 294 }, 295 }, 296 [OMAP_DSS_CHANNEL_LCD2] = { 297 .name = "LCD2", 298 .vsync_irq = DISPC_IRQ_VSYNC2, 299 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 300 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 301 .gamma = { 302 .len = 256, 303 .bits = 8, 304 .reg = DISPC_GAMMA_TABLE1, 305 .has_index = true, 306 }, 307 .reg_desc = { 308 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 309 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 310 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 311 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 312 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 313 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 314 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 315 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 316 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 317 }, 318 }, 319 [OMAP_DSS_CHANNEL_LCD3] = { 320 .name = "LCD3", 321 .vsync_irq = DISPC_IRQ_VSYNC3, 322 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 323 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 324 .gamma = { 325 .len = 256, 326 .bits = 8, 327 .reg = DISPC_GAMMA_TABLE3, 328 .has_index = true, 329 }, 330 .reg_desc = { 331 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 332 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 333 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 334 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 335 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 336 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 337 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 338 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 339 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 340 }, 341 }, 342 }; 343 344 static unsigned long dispc_fclk_rate(struct dispc_device *dispc); 345 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc); 346 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, 347 enum omap_channel channel); 348 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, 349 enum omap_channel channel); 350 351 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, 352 enum omap_plane_id plane); 353 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, 354 enum omap_plane_id plane); 355 356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) 357 { 358 __raw_writel(val, dispc->base + idx); 359 } 360 361 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) 362 { 363 return __raw_readl(dispc->base + idx); 364 } 365 366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, 367 enum mgr_reg_fields regfld) 368 { 369 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld]; 370 371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); 372 } 373 374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, 375 enum mgr_reg_fields regfld, int val) 376 { 377 const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld]; 378 379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); 380 } 381 382 int dispc_get_num_ovls(struct dispc_device *dispc) 383 { 384 return dispc->feat->num_ovls; 385 } 386 387 int dispc_get_num_mgrs(struct dispc_device *dispc) 388 { 389 return dispc->feat->num_mgrs; 390 } 391 392 static void dispc_get_reg_field(struct dispc_device *dispc, 393 enum dispc_feat_reg_field id, 394 u8 *start, u8 *end) 395 { 396 BUG_ON(id >= dispc->feat->num_reg_fields); 397 398 *start = dispc->feat->reg_fields[id].start; 399 *end = dispc->feat->reg_fields[id].end; 400 } 401 402 static bool dispc_has_feature(struct dispc_device *dispc, 403 enum dispc_feature_id id) 404 { 405 unsigned int i; 406 407 for (i = 0; i < dispc->feat->num_features; i++) { 408 if (dispc->feat->features[i] == id) 409 return true; 410 } 411 412 return false; 413 } 414 415 #define SR(dispc, reg) \ 416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg) 417 #define RR(dispc, reg) \ 418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)]) 419 420 static void dispc_save_context(struct dispc_device *dispc) 421 { 422 int i, j; 423 424 DSSDBG("dispc_save_context\n"); 425 426 SR(dispc, IRQENABLE); 427 SR(dispc, CONTROL); 428 SR(dispc, CONFIG); 429 SR(dispc, LINE_NUMBER); 430 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 431 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 432 SR(dispc, GLOBAL_ALPHA); 433 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 434 SR(dispc, CONTROL2); 435 SR(dispc, CONFIG2); 436 } 437 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 438 SR(dispc, CONTROL3); 439 SR(dispc, CONFIG3); 440 } 441 442 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 443 SR(dispc, DEFAULT_COLOR(i)); 444 SR(dispc, TRANS_COLOR(i)); 445 SR(dispc, SIZE_MGR(i)); 446 if (i == OMAP_DSS_CHANNEL_DIGIT) 447 continue; 448 SR(dispc, TIMING_H(i)); 449 SR(dispc, TIMING_V(i)); 450 SR(dispc, POL_FREQ(i)); 451 SR(dispc, DIVISORo(i)); 452 453 SR(dispc, DATA_CYCLE1(i)); 454 SR(dispc, DATA_CYCLE2(i)); 455 SR(dispc, DATA_CYCLE3(i)); 456 457 if (dispc_has_feature(dispc, FEAT_CPR)) { 458 SR(dispc, CPR_COEF_R(i)); 459 SR(dispc, CPR_COEF_G(i)); 460 SR(dispc, CPR_COEF_B(i)); 461 } 462 } 463 464 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 465 SR(dispc, OVL_BA0(i)); 466 SR(dispc, OVL_BA1(i)); 467 SR(dispc, OVL_POSITION(i)); 468 SR(dispc, OVL_SIZE(i)); 469 SR(dispc, OVL_ATTRIBUTES(i)); 470 SR(dispc, OVL_FIFO_THRESHOLD(i)); 471 SR(dispc, OVL_ROW_INC(i)); 472 SR(dispc, OVL_PIXEL_INC(i)); 473 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 474 SR(dispc, OVL_PRELOAD(i)); 475 if (i == OMAP_DSS_GFX) { 476 SR(dispc, OVL_WINDOW_SKIP(i)); 477 SR(dispc, OVL_TABLE_BA(i)); 478 continue; 479 } 480 SR(dispc, OVL_FIR(i)); 481 SR(dispc, OVL_PICTURE_SIZE(i)); 482 SR(dispc, OVL_ACCU0(i)); 483 SR(dispc, OVL_ACCU1(i)); 484 485 for (j = 0; j < 8; j++) 486 SR(dispc, OVL_FIR_COEF_H(i, j)); 487 488 for (j = 0; j < 8; j++) 489 SR(dispc, OVL_FIR_COEF_HV(i, j)); 490 491 for (j = 0; j < 5; j++) 492 SR(dispc, OVL_CONV_COEF(i, j)); 493 494 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 495 for (j = 0; j < 8; j++) 496 SR(dispc, OVL_FIR_COEF_V(i, j)); 497 } 498 499 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 500 SR(dispc, OVL_BA0_UV(i)); 501 SR(dispc, OVL_BA1_UV(i)); 502 SR(dispc, OVL_FIR2(i)); 503 SR(dispc, OVL_ACCU2_0(i)); 504 SR(dispc, OVL_ACCU2_1(i)); 505 506 for (j = 0; j < 8; j++) 507 SR(dispc, OVL_FIR_COEF_H2(i, j)); 508 509 for (j = 0; j < 8; j++) 510 SR(dispc, OVL_FIR_COEF_HV2(i, j)); 511 512 for (j = 0; j < 8; j++) 513 SR(dispc, OVL_FIR_COEF_V2(i, j)); 514 } 515 if (dispc_has_feature(dispc, FEAT_ATTR2)) 516 SR(dispc, OVL_ATTRIBUTES2(i)); 517 } 518 519 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 520 SR(dispc, DIVISOR); 521 522 dispc->ctx_valid = true; 523 524 DSSDBG("context saved\n"); 525 } 526 527 static void dispc_restore_context(struct dispc_device *dispc) 528 { 529 int i, j; 530 531 DSSDBG("dispc_restore_context\n"); 532 533 if (!dispc->ctx_valid) 534 return; 535 536 /*RR(dispc, IRQENABLE);*/ 537 /*RR(dispc, CONTROL);*/ 538 RR(dispc, CONFIG); 539 RR(dispc, LINE_NUMBER); 540 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 541 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 542 RR(dispc, GLOBAL_ALPHA); 543 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 544 RR(dispc, CONFIG2); 545 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 546 RR(dispc, CONFIG3); 547 548 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 549 RR(dispc, DEFAULT_COLOR(i)); 550 RR(dispc, TRANS_COLOR(i)); 551 RR(dispc, SIZE_MGR(i)); 552 if (i == OMAP_DSS_CHANNEL_DIGIT) 553 continue; 554 RR(dispc, TIMING_H(i)); 555 RR(dispc, TIMING_V(i)); 556 RR(dispc, POL_FREQ(i)); 557 RR(dispc, DIVISORo(i)); 558 559 RR(dispc, DATA_CYCLE1(i)); 560 RR(dispc, DATA_CYCLE2(i)); 561 RR(dispc, DATA_CYCLE3(i)); 562 563 if (dispc_has_feature(dispc, FEAT_CPR)) { 564 RR(dispc, CPR_COEF_R(i)); 565 RR(dispc, CPR_COEF_G(i)); 566 RR(dispc, CPR_COEF_B(i)); 567 } 568 } 569 570 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 571 RR(dispc, OVL_BA0(i)); 572 RR(dispc, OVL_BA1(i)); 573 RR(dispc, OVL_POSITION(i)); 574 RR(dispc, OVL_SIZE(i)); 575 RR(dispc, OVL_ATTRIBUTES(i)); 576 RR(dispc, OVL_FIFO_THRESHOLD(i)); 577 RR(dispc, OVL_ROW_INC(i)); 578 RR(dispc, OVL_PIXEL_INC(i)); 579 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 580 RR(dispc, OVL_PRELOAD(i)); 581 if (i == OMAP_DSS_GFX) { 582 RR(dispc, OVL_WINDOW_SKIP(i)); 583 RR(dispc, OVL_TABLE_BA(i)); 584 continue; 585 } 586 RR(dispc, OVL_FIR(i)); 587 RR(dispc, OVL_PICTURE_SIZE(i)); 588 RR(dispc, OVL_ACCU0(i)); 589 RR(dispc, OVL_ACCU1(i)); 590 591 for (j = 0; j < 8; j++) 592 RR(dispc, OVL_FIR_COEF_H(i, j)); 593 594 for (j = 0; j < 8; j++) 595 RR(dispc, OVL_FIR_COEF_HV(i, j)); 596 597 for (j = 0; j < 5; j++) 598 RR(dispc, OVL_CONV_COEF(i, j)); 599 600 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 601 for (j = 0; j < 8; j++) 602 RR(dispc, OVL_FIR_COEF_V(i, j)); 603 } 604 605 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 606 RR(dispc, OVL_BA0_UV(i)); 607 RR(dispc, OVL_BA1_UV(i)); 608 RR(dispc, OVL_FIR2(i)); 609 RR(dispc, OVL_ACCU2_0(i)); 610 RR(dispc, OVL_ACCU2_1(i)); 611 612 for (j = 0; j < 8; j++) 613 RR(dispc, OVL_FIR_COEF_H2(i, j)); 614 615 for (j = 0; j < 8; j++) 616 RR(dispc, OVL_FIR_COEF_HV2(i, j)); 617 618 for (j = 0; j < 8; j++) 619 RR(dispc, OVL_FIR_COEF_V2(i, j)); 620 } 621 if (dispc_has_feature(dispc, FEAT_ATTR2)) 622 RR(dispc, OVL_ATTRIBUTES2(i)); 623 } 624 625 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 626 RR(dispc, DIVISOR); 627 628 /* enable last, because LCD & DIGIT enable are here */ 629 RR(dispc, CONTROL); 630 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 631 RR(dispc, CONTROL2); 632 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 633 RR(dispc, CONTROL3); 634 /* clear spurious SYNC_LOST_DIGIT interrupts */ 635 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); 636 637 /* 638 * enable last so IRQs won't trigger before 639 * the context is fully restored 640 */ 641 RR(dispc, IRQENABLE); 642 643 DSSDBG("context restored\n"); 644 } 645 646 #undef SR 647 #undef RR 648 649 int dispc_runtime_get(struct dispc_device *dispc) 650 { 651 int r; 652 653 DSSDBG("dispc_runtime_get\n"); 654 655 r = pm_runtime_get_sync(&dispc->pdev->dev); 656 if (WARN_ON(r < 0)) { 657 pm_runtime_put_noidle(&dispc->pdev->dev); 658 return r; 659 } 660 return 0; 661 } 662 663 void dispc_runtime_put(struct dispc_device *dispc) 664 { 665 int r; 666 667 DSSDBG("dispc_runtime_put\n"); 668 669 r = pm_runtime_put_sync(&dispc->pdev->dev); 670 WARN_ON(r < 0 && r != -ENOSYS); 671 } 672 673 u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, 674 enum omap_channel channel) 675 { 676 return mgr_desc[channel].vsync_irq; 677 } 678 679 u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, 680 enum omap_channel channel) 681 { 682 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) 683 return 0; 684 685 return mgr_desc[channel].framedone_irq; 686 } 687 688 u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, 689 enum omap_channel channel) 690 { 691 return mgr_desc[channel].sync_lost_irq; 692 } 693 694 u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) 695 { 696 return DISPC_IRQ_FRAMEDONEWB; 697 } 698 699 void dispc_mgr_enable(struct dispc_device *dispc, 700 enum omap_channel channel, bool enable) 701 { 702 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); 703 /* flush posted write */ 704 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); 705 } 706 707 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, 708 enum omap_channel channel) 709 { 710 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); 711 } 712 713 bool dispc_mgr_go_busy(struct dispc_device *dispc, 714 enum omap_channel channel) 715 { 716 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; 717 } 718 719 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) 720 { 721 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); 722 WARN_ON(dispc_mgr_go_busy(dispc, channel)); 723 724 DSSDBG("GO %s\n", mgr_desc[channel].name); 725 726 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); 727 } 728 729 bool dispc_wb_go_busy(struct dispc_device *dispc) 730 { 731 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; 732 } 733 734 void dispc_wb_go(struct dispc_device *dispc) 735 { 736 enum omap_plane_id plane = OMAP_DSS_WB; 737 bool enable, go; 738 739 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 740 741 if (!enable) 742 return; 743 744 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; 745 if (go) { 746 DSSERR("GO bit not down for WB\n"); 747 return; 748 } 749 750 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); 751 } 752 753 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, 754 enum omap_plane_id plane, int reg, 755 u32 value) 756 { 757 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); 758 } 759 760 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, 761 enum omap_plane_id plane, int reg, 762 u32 value) 763 { 764 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); 765 } 766 767 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, 768 enum omap_plane_id plane, int reg, 769 u32 value) 770 { 771 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); 772 } 773 774 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, 775 enum omap_plane_id plane, int reg, 776 u32 value) 777 { 778 BUG_ON(plane == OMAP_DSS_GFX); 779 780 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); 781 } 782 783 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, 784 enum omap_plane_id plane, int reg, 785 u32 value) 786 { 787 BUG_ON(plane == OMAP_DSS_GFX); 788 789 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 790 } 791 792 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, 793 enum omap_plane_id plane, int reg, 794 u32 value) 795 { 796 BUG_ON(plane == OMAP_DSS_GFX); 797 798 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); 799 } 800 801 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, 802 enum omap_plane_id plane, int fir_hinc, 803 int fir_vinc, int five_taps, 804 enum omap_color_component color_comp) 805 { 806 const struct dispc_coef *h_coef, *v_coef; 807 int i; 808 809 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 810 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 811 812 if (!h_coef || !v_coef) { 813 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", 814 __func__); 815 return; 816 } 817 818 for (i = 0; i < 8; i++) { 819 u32 h, hv; 820 821 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 822 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 823 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 824 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 825 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 826 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 827 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 828 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 829 830 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 831 dispc_ovl_write_firh_reg(dispc, plane, i, h); 832 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); 833 } else { 834 dispc_ovl_write_firh2_reg(dispc, plane, i, h); 835 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); 836 } 837 838 } 839 840 if (five_taps) { 841 for (i = 0; i < 8; i++) { 842 u32 v; 843 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 844 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 845 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 846 dispc_ovl_write_firv_reg(dispc, plane, i, v); 847 else 848 dispc_ovl_write_firv2_reg(dispc, plane, i, v); 849 } 850 } 851 } 852 853 struct csc_coef_yuv2rgb { 854 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr; 855 bool full_range; 856 }; 857 858 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, 859 enum omap_plane_id plane, 860 const struct csc_coef_yuv2rgb *ct) 861 { 862 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 863 864 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 865 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 869 870 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 871 872 #undef CVAL 873 } 874 875 /* YUV -> RGB, ITU-R BT.601, full range */ 876 static const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_full = { 877 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/ 878 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/ 879 256, 452, 0, /* by, bcb, bcr |1.000 1.772 0.000|*/ 880 true, /* full range */ 881 }; 882 883 /* YUV -> RGB, ITU-R BT.601, limited range */ 884 static const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = { 885 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/ 886 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/ 887 298, 516, 0, /* by, bcb, bcr |1.164 2.017 0.000|*/ 888 false, /* limited range */ 889 }; 890 891 /* YUV -> RGB, ITU-R BT.709, full range */ 892 static const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt709_full = { 893 256, 0, 402, /* ry, rcb, rcr |1.000 0.000 1.570|*/ 894 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/ 895 256, 475, 0, /* by, bcb, bcr |1.000 1.856 0.000|*/ 896 true, /* full range */ 897 }; 898 899 /* YUV -> RGB, ITU-R BT.709, limited range */ 900 static const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt709_lim = { 901 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/ 902 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/ 903 298, 541, 0, /* by, bcb, bcr |1.164 2.112 0.000|*/ 904 false, /* limited range */ 905 }; 906 907 static void dispc_ovl_set_csc(struct dispc_device *dispc, 908 enum omap_plane_id plane, 909 enum drm_color_encoding color_encoding, 910 enum drm_color_range color_range) 911 { 912 const struct csc_coef_yuv2rgb *csc; 913 914 switch (color_encoding) { 915 default: 916 case DRM_COLOR_YCBCR_BT601: 917 if (color_range == DRM_COLOR_YCBCR_FULL_RANGE) 918 csc = &coefs_yuv2rgb_bt601_full; 919 else 920 csc = &coefs_yuv2rgb_bt601_lim; 921 break; 922 case DRM_COLOR_YCBCR_BT709: 923 if (color_range == DRM_COLOR_YCBCR_FULL_RANGE) 924 csc = &coefs_yuv2rgb_bt709_full; 925 else 926 csc = &coefs_yuv2rgb_bt709_lim; 927 break; 928 } 929 930 dispc_ovl_write_color_conv_coef(dispc, plane, csc); 931 } 932 933 static void dispc_ovl_set_ba0(struct dispc_device *dispc, 934 enum omap_plane_id plane, u32 paddr) 935 { 936 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); 937 } 938 939 static void dispc_ovl_set_ba1(struct dispc_device *dispc, 940 enum omap_plane_id plane, u32 paddr) 941 { 942 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); 943 } 944 945 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, 946 enum omap_plane_id plane, u32 paddr) 947 { 948 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); 949 } 950 951 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, 952 enum omap_plane_id plane, u32 paddr) 953 { 954 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); 955 } 956 957 static void dispc_ovl_set_pos(struct dispc_device *dispc, 958 enum omap_plane_id plane, 959 enum omap_overlay_caps caps, int x, int y) 960 { 961 u32 val; 962 963 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 964 return; 965 966 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 967 968 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); 969 } 970 971 static void dispc_ovl_set_input_size(struct dispc_device *dispc, 972 enum omap_plane_id plane, int width, 973 int height) 974 { 975 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 976 977 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 978 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); 979 else 980 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); 981 } 982 983 static void dispc_ovl_set_output_size(struct dispc_device *dispc, 984 enum omap_plane_id plane, int width, 985 int height) 986 { 987 u32 val; 988 989 BUG_ON(plane == OMAP_DSS_GFX); 990 991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 992 993 if (plane == OMAP_DSS_WB) 994 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); 995 else 996 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); 997 } 998 999 static void dispc_ovl_set_zorder(struct dispc_device *dispc, 1000 enum omap_plane_id plane, 1001 enum omap_overlay_caps caps, u8 zorder) 1002 { 1003 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 1004 return; 1005 1006 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 1007 } 1008 1009 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) 1010 { 1011 int i; 1012 1013 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 1014 return; 1015 1016 for (i = 0; i < dispc_get_num_ovls(dispc); i++) 1017 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 1018 } 1019 1020 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, 1021 enum omap_plane_id plane, 1022 enum omap_overlay_caps caps, 1023 bool enable) 1024 { 1025 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 1026 return; 1027 1028 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 1029 } 1030 1031 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, 1032 enum omap_plane_id plane, 1033 enum omap_overlay_caps caps, 1034 u8 global_alpha) 1035 { 1036 static const unsigned int shifts[] = { 0, 8, 16, 24, }; 1037 int shift; 1038 1039 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 1040 return; 1041 1042 shift = shifts[plane]; 1043 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 1044 } 1045 1046 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, 1047 enum omap_plane_id plane, s32 inc) 1048 { 1049 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); 1050 } 1051 1052 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, 1053 enum omap_plane_id plane, s32 inc) 1054 { 1055 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); 1056 } 1057 1058 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, 1059 enum omap_plane_id plane, u32 fourcc) 1060 { 1061 u32 m = 0; 1062 if (plane != OMAP_DSS_GFX) { 1063 switch (fourcc) { 1064 case DRM_FORMAT_NV12: 1065 m = 0x0; break; 1066 case DRM_FORMAT_XRGB4444: 1067 m = 0x1; break; 1068 case DRM_FORMAT_RGBA4444: 1069 m = 0x2; break; 1070 case DRM_FORMAT_RGBX4444: 1071 m = 0x4; break; 1072 case DRM_FORMAT_ARGB4444: 1073 m = 0x5; break; 1074 case DRM_FORMAT_RGB565: 1075 m = 0x6; break; 1076 case DRM_FORMAT_ARGB1555: 1077 m = 0x7; break; 1078 case DRM_FORMAT_XRGB8888: 1079 m = 0x8; break; 1080 case DRM_FORMAT_RGB888: 1081 m = 0x9; break; 1082 case DRM_FORMAT_YUYV: 1083 m = 0xa; break; 1084 case DRM_FORMAT_UYVY: 1085 m = 0xb; break; 1086 case DRM_FORMAT_ARGB8888: 1087 m = 0xc; break; 1088 case DRM_FORMAT_RGBA8888: 1089 m = 0xd; break; 1090 case DRM_FORMAT_RGBX8888: 1091 m = 0xe; break; 1092 case DRM_FORMAT_XRGB1555: 1093 m = 0xf; break; 1094 default: 1095 BUG(); return; 1096 } 1097 } else { 1098 switch (fourcc) { 1099 case DRM_FORMAT_RGBX4444: 1100 m = 0x4; break; 1101 case DRM_FORMAT_ARGB4444: 1102 m = 0x5; break; 1103 case DRM_FORMAT_RGB565: 1104 m = 0x6; break; 1105 case DRM_FORMAT_ARGB1555: 1106 m = 0x7; break; 1107 case DRM_FORMAT_XRGB8888: 1108 m = 0x8; break; 1109 case DRM_FORMAT_RGB888: 1110 m = 0x9; break; 1111 case DRM_FORMAT_XRGB4444: 1112 m = 0xa; break; 1113 case DRM_FORMAT_RGBA4444: 1114 m = 0xb; break; 1115 case DRM_FORMAT_ARGB8888: 1116 m = 0xc; break; 1117 case DRM_FORMAT_RGBA8888: 1118 m = 0xd; break; 1119 case DRM_FORMAT_RGBX8888: 1120 m = 0xe; break; 1121 case DRM_FORMAT_XRGB1555: 1122 m = 0xf; break; 1123 default: 1124 BUG(); return; 1125 } 1126 } 1127 1128 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 1129 } 1130 1131 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, 1132 enum omap_plane_id plane, 1133 enum omap_dss_rotation_type rotation) 1134 { 1135 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) 1136 return; 1137 1138 if (rotation == OMAP_DSS_ROT_TILER) 1139 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 1140 else 1141 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 1142 } 1143 1144 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, 1145 enum omap_plane_id plane, 1146 enum omap_channel channel) 1147 { 1148 int shift; 1149 u32 val; 1150 int chan = 0, chan2 = 0; 1151 1152 switch (plane) { 1153 case OMAP_DSS_GFX: 1154 shift = 8; 1155 break; 1156 case OMAP_DSS_VIDEO1: 1157 case OMAP_DSS_VIDEO2: 1158 case OMAP_DSS_VIDEO3: 1159 shift = 16; 1160 break; 1161 default: 1162 BUG(); 1163 return; 1164 } 1165 1166 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1167 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 1168 switch (channel) { 1169 case OMAP_DSS_CHANNEL_LCD: 1170 chan = 0; 1171 chan2 = 0; 1172 break; 1173 case OMAP_DSS_CHANNEL_DIGIT: 1174 chan = 1; 1175 chan2 = 0; 1176 break; 1177 case OMAP_DSS_CHANNEL_LCD2: 1178 chan = 0; 1179 chan2 = 1; 1180 break; 1181 case OMAP_DSS_CHANNEL_LCD3: 1182 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 1183 chan = 0; 1184 chan2 = 2; 1185 } else { 1186 BUG(); 1187 return; 1188 } 1189 break; 1190 case OMAP_DSS_CHANNEL_WB: 1191 chan = 0; 1192 chan2 = 3; 1193 break; 1194 default: 1195 BUG(); 1196 return; 1197 } 1198 1199 val = FLD_MOD(val, chan, shift, shift); 1200 val = FLD_MOD(val, chan2, 31, 30); 1201 } else { 1202 val = FLD_MOD(val, channel, shift, shift); 1203 } 1204 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); 1205 } 1206 1207 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, 1208 enum omap_plane_id plane) 1209 { 1210 int shift; 1211 u32 val; 1212 1213 switch (plane) { 1214 case OMAP_DSS_GFX: 1215 shift = 8; 1216 break; 1217 case OMAP_DSS_VIDEO1: 1218 case OMAP_DSS_VIDEO2: 1219 case OMAP_DSS_VIDEO3: 1220 shift = 16; 1221 break; 1222 default: 1223 BUG(); 1224 return 0; 1225 } 1226 1227 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1228 1229 if (FLD_GET(val, shift, shift) == 1) 1230 return OMAP_DSS_CHANNEL_DIGIT; 1231 1232 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) 1233 return OMAP_DSS_CHANNEL_LCD; 1234 1235 switch (FLD_GET(val, 31, 30)) { 1236 case 0: 1237 default: 1238 return OMAP_DSS_CHANNEL_LCD; 1239 case 1: 1240 return OMAP_DSS_CHANNEL_LCD2; 1241 case 2: 1242 return OMAP_DSS_CHANNEL_LCD3; 1243 case 3: 1244 return OMAP_DSS_CHANNEL_WB; 1245 } 1246 } 1247 1248 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, 1249 enum omap_plane_id plane, 1250 enum omap_burst_size burst_size) 1251 { 1252 static const unsigned int shifts[] = { 6, 14, 14, 14, 14, }; 1253 int shift; 1254 1255 shift = shifts[plane]; 1256 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, 1257 shift + 1, shift); 1258 } 1259 1260 static void dispc_configure_burst_sizes(struct dispc_device *dispc) 1261 { 1262 int i; 1263 const int burst_size = BURST_SIZE_X8; 1264 1265 /* Configure burst size always to maximum size */ 1266 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) 1267 dispc_ovl_set_burst_size(dispc, i, burst_size); 1268 if (dispc->feat->has_writeback) 1269 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); 1270 } 1271 1272 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, 1273 enum omap_plane_id plane) 1274 { 1275 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1276 return dispc->feat->burst_size_unit * 8; 1277 } 1278 1279 bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, 1280 enum omap_plane_id plane, u32 fourcc) 1281 { 1282 const u32 *modes; 1283 unsigned int i; 1284 1285 modes = dispc->feat->supported_color_modes[plane]; 1286 1287 for (i = 0; modes[i]; ++i) { 1288 if (modes[i] == fourcc) 1289 return true; 1290 } 1291 1292 return false; 1293 } 1294 1295 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, 1296 enum omap_plane_id plane) 1297 { 1298 return dispc->feat->supported_color_modes[plane]; 1299 } 1300 1301 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, 1302 enum omap_channel channel, bool enable) 1303 { 1304 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1305 return; 1306 1307 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); 1308 } 1309 1310 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, 1311 enum omap_channel channel, 1312 const struct omap_dss_cpr_coefs *coefs) 1313 { 1314 u32 coef_r, coef_g, coef_b; 1315 1316 if (!dss_mgr_is_lcd(channel)) 1317 return; 1318 1319 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1320 FLD_VAL(coefs->rb, 9, 0); 1321 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1322 FLD_VAL(coefs->gb, 9, 0); 1323 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1324 FLD_VAL(coefs->bb, 9, 0); 1325 1326 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); 1327 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); 1328 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); 1329 } 1330 1331 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, 1332 enum omap_plane_id plane, bool enable) 1333 { 1334 u32 val; 1335 1336 BUG_ON(plane == OMAP_DSS_GFX); 1337 1338 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1339 val = FLD_MOD(val, enable, 9, 9); 1340 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); 1341 } 1342 1343 static void dispc_ovl_enable_replication(struct dispc_device *dispc, 1344 enum omap_plane_id plane, 1345 enum omap_overlay_caps caps, 1346 bool enable) 1347 { 1348 static const unsigned int shifts[] = { 5, 10, 10, 10 }; 1349 int shift; 1350 1351 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1352 return; 1353 1354 shift = shifts[plane]; 1355 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1356 } 1357 1358 static void dispc_mgr_set_size(struct dispc_device *dispc, 1359 enum omap_channel channel, u16 width, u16 height) 1360 { 1361 u32 val; 1362 1363 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | 1364 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); 1365 1366 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); 1367 } 1368 1369 static void dispc_init_fifos(struct dispc_device *dispc) 1370 { 1371 u32 size; 1372 int fifo; 1373 u8 start, end; 1374 u32 unit; 1375 int i; 1376 1377 unit = dispc->feat->buffer_size_unit; 1378 1379 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); 1380 1381 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { 1382 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), 1383 start, end); 1384 size *= unit; 1385 dispc->fifo_size[fifo] = size; 1386 1387 /* 1388 * By default fifos are mapped directly to overlays, fifo 0 to 1389 * ovl 0, fifo 1 to ovl 1, etc. 1390 */ 1391 dispc->fifo_assignment[fifo] = fifo; 1392 } 1393 1394 /* 1395 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1396 * causes problems with certain use cases, like using the tiler in 2D 1397 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1398 * giving GFX plane a larger fifo. WB but should work fine with a 1399 * smaller fifo. 1400 */ 1401 if (dispc->feat->gfx_fifo_workaround) { 1402 u32 v; 1403 1404 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); 1405 1406 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1407 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1408 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1409 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1410 1411 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); 1412 1413 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1414 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1415 } 1416 1417 /* 1418 * Setup default fifo thresholds. 1419 */ 1420 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { 1421 u32 low, high; 1422 const bool use_fifomerge = false; 1423 const bool manual_update = false; 1424 1425 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, 1426 use_fifomerge, manual_update); 1427 1428 dispc_ovl_set_fifo_threshold(dispc, i, low, high); 1429 } 1430 1431 if (dispc->feat->has_writeback) { 1432 u32 low, high; 1433 const bool use_fifomerge = false; 1434 const bool manual_update = false; 1435 1436 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, 1437 &low, &high, use_fifomerge, 1438 manual_update); 1439 1440 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); 1441 } 1442 } 1443 1444 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, 1445 enum omap_plane_id plane) 1446 { 1447 int fifo; 1448 u32 size = 0; 1449 1450 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { 1451 if (dispc->fifo_assignment[fifo] == plane) 1452 size += dispc->fifo_size[fifo]; 1453 } 1454 1455 return size; 1456 } 1457 1458 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, 1459 enum omap_plane_id plane, 1460 u32 low, u32 high) 1461 { 1462 u8 hi_start, hi_end, lo_start, lo_end; 1463 u32 unit; 1464 1465 unit = dispc->feat->buffer_size_unit; 1466 1467 WARN_ON(low % unit != 0); 1468 WARN_ON(high % unit != 0); 1469 1470 low /= unit; 1471 high /= unit; 1472 1473 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, 1474 &hi_start, &hi_end); 1475 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, 1476 &lo_start, &lo_end); 1477 1478 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1479 plane, 1480 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1481 lo_start, lo_end) * unit, 1482 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1483 hi_start, hi_end) * unit, 1484 low * unit, high * unit); 1485 1486 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), 1487 FLD_VAL(high, hi_start, hi_end) | 1488 FLD_VAL(low, lo_start, lo_end)); 1489 1490 /* 1491 * configure the preload to the pipeline's high threhold, if HT it's too 1492 * large for the preload field, set the threshold to the maximum value 1493 * that can be held by the preload register 1494 */ 1495 if (dispc_has_feature(dispc, FEAT_PRELOAD) && 1496 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) 1497 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), 1498 min(high, 0xfffu)); 1499 } 1500 1501 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) 1502 { 1503 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { 1504 WARN_ON(enable); 1505 return; 1506 } 1507 1508 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1509 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1510 } 1511 1512 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, 1513 enum omap_plane_id plane, 1514 u32 *fifo_low, u32 *fifo_high, 1515 bool use_fifomerge, bool manual_update) 1516 { 1517 /* 1518 * All sizes are in bytes. Both the buffer and burst are made of 1519 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1520 */ 1521 unsigned int buf_unit = dispc->feat->buffer_size_unit; 1522 unsigned int ovl_fifo_size, total_fifo_size, burst_size; 1523 int i; 1524 1525 burst_size = dispc_ovl_get_burst_size(dispc, plane); 1526 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); 1527 1528 if (use_fifomerge) { 1529 total_fifo_size = 0; 1530 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) 1531 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); 1532 } else { 1533 total_fifo_size = ovl_fifo_size; 1534 } 1535 1536 /* 1537 * We use the same low threshold for both fifomerge and non-fifomerge 1538 * cases, but for fifomerge we calculate the high threshold using the 1539 * combined fifo size 1540 */ 1541 1542 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { 1543 *fifo_low = ovl_fifo_size - burst_size * 2; 1544 *fifo_high = total_fifo_size - burst_size; 1545 } else if (plane == OMAP_DSS_WB) { 1546 /* 1547 * Most optimal configuration for writeback is to push out data 1548 * to the interconnect the moment writeback pushes enough pixels 1549 * in the FIFO to form a burst 1550 */ 1551 *fifo_low = 0; 1552 *fifo_high = burst_size; 1553 } else { 1554 *fifo_low = ovl_fifo_size - burst_size; 1555 *fifo_high = total_fifo_size - buf_unit; 1556 } 1557 } 1558 1559 static void dispc_ovl_set_mflag(struct dispc_device *dispc, 1560 enum omap_plane_id plane, bool enable) 1561 { 1562 int bit; 1563 1564 if (plane == OMAP_DSS_GFX) 1565 bit = 14; 1566 else 1567 bit = 23; 1568 1569 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1570 } 1571 1572 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, 1573 enum omap_plane_id plane, 1574 int low, int high) 1575 { 1576 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), 1577 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1578 } 1579 1580 static void dispc_init_mflag(struct dispc_device *dispc) 1581 { 1582 int i; 1583 1584 /* 1585 * HACK: NV12 color format and MFLAG seem to have problems working 1586 * together: using two displays, and having an NV12 overlay on one of 1587 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1588 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1589 * remove the errors, but there doesn't seem to be a clear logic on 1590 * which values work and which not. 1591 * 1592 * As a work-around, set force MFLAG to always on. 1593 */ 1594 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1595 (1 << 0) | /* MFLAG_CTRL = force always on */ 1596 (0 << 2)); /* MFLAG_START = disable */ 1597 1598 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { 1599 u32 size = dispc_ovl_get_fifo_size(dispc, i); 1600 u32 unit = dispc->feat->buffer_size_unit; 1601 u32 low, high; 1602 1603 dispc_ovl_set_mflag(dispc, i, true); 1604 1605 /* 1606 * Simulation team suggests below thesholds: 1607 * HT = fifosize * 5 / 8; 1608 * LT = fifosize * 4 / 8; 1609 */ 1610 1611 low = size * 4 / 8 / unit; 1612 high = size * 5 / 8 / unit; 1613 1614 dispc_ovl_set_mflag_threshold(dispc, i, low, high); 1615 } 1616 1617 if (dispc->feat->has_writeback) { 1618 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); 1619 u32 unit = dispc->feat->buffer_size_unit; 1620 u32 low, high; 1621 1622 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); 1623 1624 /* 1625 * Simulation team suggests below thesholds: 1626 * HT = fifosize * 5 / 8; 1627 * LT = fifosize * 4 / 8; 1628 */ 1629 1630 low = size * 4 / 8 / unit; 1631 high = size * 5 / 8 / unit; 1632 1633 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); 1634 } 1635 } 1636 1637 static void dispc_ovl_set_fir(struct dispc_device *dispc, 1638 enum omap_plane_id plane, 1639 int hinc, int vinc, 1640 enum omap_color_component color_comp) 1641 { 1642 u32 val; 1643 1644 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1645 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1646 1647 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, 1648 &hinc_start, &hinc_end); 1649 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, 1650 &vinc_start, &vinc_end); 1651 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1652 FLD_VAL(hinc, hinc_start, hinc_end); 1653 1654 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); 1655 } else { 1656 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1657 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); 1658 } 1659 } 1660 1661 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, 1662 enum omap_plane_id plane, int haccu, 1663 int vaccu) 1664 { 1665 u32 val; 1666 u8 hor_start, hor_end, vert_start, vert_end; 1667 1668 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, 1669 &hor_start, &hor_end); 1670 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, 1671 &vert_start, &vert_end); 1672 1673 val = FLD_VAL(vaccu, vert_start, vert_end) | 1674 FLD_VAL(haccu, hor_start, hor_end); 1675 1676 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); 1677 } 1678 1679 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, 1680 enum omap_plane_id plane, int haccu, 1681 int vaccu) 1682 { 1683 u32 val; 1684 u8 hor_start, hor_end, vert_start, vert_end; 1685 1686 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, 1687 &hor_start, &hor_end); 1688 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, 1689 &vert_start, &vert_end); 1690 1691 val = FLD_VAL(vaccu, vert_start, vert_end) | 1692 FLD_VAL(haccu, hor_start, hor_end); 1693 1694 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); 1695 } 1696 1697 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, 1698 enum omap_plane_id plane, int haccu, 1699 int vaccu) 1700 { 1701 u32 val; 1702 1703 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); 1705 } 1706 1707 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, 1708 enum omap_plane_id plane, int haccu, 1709 int vaccu) 1710 { 1711 u32 val; 1712 1713 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1714 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); 1715 } 1716 1717 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, 1718 enum omap_plane_id plane, 1719 u16 orig_width, u16 orig_height, 1720 u16 out_width, u16 out_height, 1721 bool five_taps, u8 rotation, 1722 enum omap_color_component color_comp) 1723 { 1724 int fir_hinc, fir_vinc; 1725 1726 fir_hinc = 1024 * orig_width / out_width; 1727 fir_vinc = 1024 * orig_height / out_height; 1728 1729 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, 1730 color_comp); 1731 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); 1732 } 1733 1734 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, 1735 enum omap_plane_id plane, 1736 u16 orig_width, u16 orig_height, 1737 u16 out_width, u16 out_height, 1738 bool ilace, u32 fourcc, u8 rotation) 1739 { 1740 int h_accu2_0, h_accu2_1; 1741 int v_accu2_0, v_accu2_1; 1742 int chroma_hinc, chroma_vinc; 1743 int idx; 1744 1745 struct accu { 1746 s8 h0_m, h0_n; 1747 s8 h1_m, h1_n; 1748 s8 v0_m, v0_n; 1749 s8 v1_m, v1_n; 1750 }; 1751 1752 const struct accu *accu_table; 1753 const struct accu *accu_val; 1754 1755 static const struct accu accu_nv12[4] = { 1756 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1757 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1758 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1759 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1760 }; 1761 1762 static const struct accu accu_nv12_ilace[4] = { 1763 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1764 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1765 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1766 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1767 }; 1768 1769 static const struct accu accu_yuv[4] = { 1770 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1771 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1772 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1773 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1774 }; 1775 1776 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1777 switch (rotation & DRM_MODE_ROTATE_MASK) { 1778 default: 1779 case DRM_MODE_ROTATE_0: 1780 idx = 0; 1781 break; 1782 case DRM_MODE_ROTATE_90: 1783 idx = 3; 1784 break; 1785 case DRM_MODE_ROTATE_180: 1786 idx = 2; 1787 break; 1788 case DRM_MODE_ROTATE_270: 1789 idx = 1; 1790 break; 1791 } 1792 1793 switch (fourcc) { 1794 case DRM_FORMAT_NV12: 1795 if (ilace) 1796 accu_table = accu_nv12_ilace; 1797 else 1798 accu_table = accu_nv12; 1799 break; 1800 case DRM_FORMAT_YUYV: 1801 case DRM_FORMAT_UYVY: 1802 accu_table = accu_yuv; 1803 break; 1804 default: 1805 BUG(); 1806 return; 1807 } 1808 1809 accu_val = &accu_table[idx]; 1810 1811 chroma_hinc = 1024 * orig_width / out_width; 1812 chroma_vinc = 1024 * orig_height / out_height; 1813 1814 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1815 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1816 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1817 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1818 1819 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); 1820 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); 1821 } 1822 1823 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, 1824 enum omap_plane_id plane, 1825 u16 orig_width, u16 orig_height, 1826 u16 out_width, u16 out_height, 1827 bool ilace, bool five_taps, 1828 bool fieldmode, u32 fourcc, 1829 u8 rotation) 1830 { 1831 int accu0 = 0; 1832 int accu1 = 0; 1833 u32 l; 1834 1835 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, 1836 out_width, out_height, five_taps, 1837 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1838 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 1839 1840 /* RESIZEENABLE and VERTICALTAPS */ 1841 l &= ~((0x3 << 5) | (0x1 << 21)); 1842 l |= (orig_width != out_width) ? (1 << 5) : 0; 1843 l |= (orig_height != out_height) ? (1 << 6) : 0; 1844 l |= five_taps ? (1 << 21) : 0; 1845 1846 /* VRESIZECONF and HRESIZECONF */ 1847 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { 1848 l &= ~(0x3 << 7); 1849 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1850 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1851 } 1852 1853 /* LINEBUFFERSPLIT */ 1854 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { 1855 l &= ~(0x1 << 22); 1856 l |= five_taps ? (1 << 22) : 0; 1857 } 1858 1859 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); 1860 1861 /* 1862 * field 0 = even field = bottom field 1863 * field 1 = odd field = top field 1864 */ 1865 if (ilace && !fieldmode) { 1866 accu1 = 0; 1867 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1868 if (accu0 >= 1024/2) { 1869 accu1 = 1024/2; 1870 accu0 -= accu1; 1871 } 1872 } 1873 1874 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); 1875 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); 1876 } 1877 1878 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, 1879 enum omap_plane_id plane, 1880 u16 orig_width, u16 orig_height, 1881 u16 out_width, u16 out_height, 1882 bool ilace, bool five_taps, 1883 bool fieldmode, u32 fourcc, 1884 u8 rotation) 1885 { 1886 int scale_x = out_width != orig_width; 1887 int scale_y = out_height != orig_height; 1888 bool chroma_upscale = plane != OMAP_DSS_WB; 1889 const struct drm_format_info *info; 1890 1891 info = drm_format_info(fourcc); 1892 1893 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) 1894 return; 1895 1896 if (!info->is_yuv) { 1897 /* reset chroma resampling for RGB formats */ 1898 if (plane != OMAP_DSS_WB) 1899 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 1900 0, 8, 8); 1901 return; 1902 } 1903 1904 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, 1905 out_height, ilace, fourcc, rotation); 1906 1907 switch (fourcc) { 1908 case DRM_FORMAT_NV12: 1909 if (chroma_upscale) { 1910 /* UV is subsampled by 2 horizontally and vertically */ 1911 orig_height >>= 1; 1912 orig_width >>= 1; 1913 } else { 1914 /* UV is downsampled by 2 horizontally and vertically */ 1915 orig_height <<= 1; 1916 orig_width <<= 1; 1917 } 1918 1919 break; 1920 case DRM_FORMAT_YUYV: 1921 case DRM_FORMAT_UYVY: 1922 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1923 if (!drm_rotation_90_or_270(rotation)) { 1924 if (chroma_upscale) 1925 /* UV is subsampled by 2 horizontally */ 1926 orig_width >>= 1; 1927 else 1928 /* UV is downsampled by 2 horizontally */ 1929 orig_width <<= 1; 1930 } 1931 1932 /* must use FIR for YUV422 if rotated */ 1933 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0) 1934 scale_x = scale_y = true; 1935 1936 break; 1937 default: 1938 BUG(); 1939 return; 1940 } 1941 1942 if (out_width != orig_width) 1943 scale_x = true; 1944 if (out_height != orig_height) 1945 scale_y = true; 1946 1947 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, 1948 out_width, out_height, five_taps, 1949 rotation, DISPC_COLOR_COMPONENT_UV); 1950 1951 if (plane != OMAP_DSS_WB) 1952 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 1953 (scale_x || scale_y) ? 1 : 0, 8, 8); 1954 1955 /* set H scaling */ 1956 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1957 /* set V scaling */ 1958 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1959 } 1960 1961 static void dispc_ovl_set_scaling(struct dispc_device *dispc, 1962 enum omap_plane_id plane, 1963 u16 orig_width, u16 orig_height, 1964 u16 out_width, u16 out_height, 1965 bool ilace, bool five_taps, 1966 bool fieldmode, u32 fourcc, 1967 u8 rotation) 1968 { 1969 BUG_ON(plane == OMAP_DSS_GFX); 1970 1971 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, 1972 out_width, out_height, ilace, five_taps, 1973 fieldmode, fourcc, rotation); 1974 1975 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, 1976 out_width, out_height, ilace, five_taps, 1977 fieldmode, fourcc, rotation); 1978 } 1979 1980 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, 1981 enum omap_plane_id plane, u8 rotation, 1982 enum omap_dss_rotation_type rotation_type, 1983 u32 fourcc) 1984 { 1985 bool row_repeat = false; 1986 int vidrot = 0; 1987 1988 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1989 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) { 1990 1991 if (rotation & DRM_MODE_REFLECT_X) { 1992 switch (rotation & DRM_MODE_ROTATE_MASK) { 1993 case DRM_MODE_ROTATE_0: 1994 vidrot = 2; 1995 break; 1996 case DRM_MODE_ROTATE_90: 1997 vidrot = 1; 1998 break; 1999 case DRM_MODE_ROTATE_180: 2000 vidrot = 0; 2001 break; 2002 case DRM_MODE_ROTATE_270: 2003 vidrot = 3; 2004 break; 2005 } 2006 } else { 2007 switch (rotation & DRM_MODE_ROTATE_MASK) { 2008 case DRM_MODE_ROTATE_0: 2009 vidrot = 0; 2010 break; 2011 case DRM_MODE_ROTATE_90: 2012 vidrot = 3; 2013 break; 2014 case DRM_MODE_ROTATE_180: 2015 vidrot = 2; 2016 break; 2017 case DRM_MODE_ROTATE_270: 2018 vidrot = 1; 2019 break; 2020 } 2021 } 2022 2023 if (drm_rotation_90_or_270(rotation)) 2024 row_repeat = true; 2025 else 2026 row_repeat = false; 2027 } 2028 2029 /* 2030 * OMAP4/5 Errata i631: 2031 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 2032 * rows beyond the framebuffer, which may cause OCP error. 2033 */ 2034 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) 2035 vidrot = 1; 2036 2037 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 2038 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) 2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 2040 row_repeat ? 1 : 0, 18, 18); 2041 2042 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { 2043 bool doublestride = 2044 fourcc == DRM_FORMAT_NV12 && 2045 rotation_type == OMAP_DSS_ROT_TILER && 2046 !drm_rotation_90_or_270(rotation); 2047 2048 /* DOUBLESTRIDE */ 2049 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 2050 doublestride, 22, 22); 2051 } 2052 } 2053 2054 static int color_mode_to_bpp(u32 fourcc) 2055 { 2056 switch (fourcc) { 2057 case DRM_FORMAT_NV12: 2058 return 8; 2059 case DRM_FORMAT_RGBX4444: 2060 case DRM_FORMAT_RGB565: 2061 case DRM_FORMAT_ARGB4444: 2062 case DRM_FORMAT_YUYV: 2063 case DRM_FORMAT_UYVY: 2064 case DRM_FORMAT_RGBA4444: 2065 case DRM_FORMAT_XRGB4444: 2066 case DRM_FORMAT_ARGB1555: 2067 case DRM_FORMAT_XRGB1555: 2068 return 16; 2069 case DRM_FORMAT_RGB888: 2070 return 24; 2071 case DRM_FORMAT_XRGB8888: 2072 case DRM_FORMAT_ARGB8888: 2073 case DRM_FORMAT_RGBA8888: 2074 case DRM_FORMAT_RGBX8888: 2075 return 32; 2076 default: 2077 BUG(); 2078 return 0; 2079 } 2080 } 2081 2082 static s32 pixinc(int pixels, u8 ps) 2083 { 2084 if (pixels == 1) 2085 return 1; 2086 else if (pixels > 1) 2087 return 1 + (pixels - 1) * ps; 2088 else if (pixels < 0) 2089 return 1 - (-pixels + 1) * ps; 2090 2091 BUG(); 2092 } 2093 2094 static void calc_offset(u16 screen_width, u16 width, 2095 u32 fourcc, bool fieldmode, unsigned int field_offset, 2096 unsigned int *offset0, unsigned int *offset1, 2097 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, 2098 enum omap_dss_rotation_type rotation_type, u8 rotation) 2099 { 2100 u8 ps; 2101 2102 ps = color_mode_to_bpp(fourcc) / 8; 2103 2104 DSSDBG("scrw %d, width %d\n", screen_width, width); 2105 2106 if (rotation_type == OMAP_DSS_ROT_TILER && 2107 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && 2108 drm_rotation_90_or_270(rotation)) { 2109 /* 2110 * HACK: ROW_INC needs to be calculated with TILER units. 2111 * We get such 'screen_width' that multiplying it with the 2112 * YUV422 pixel size gives the correct TILER container width. 2113 * However, 'width' is in pixels and multiplying it with YUV422 2114 * pixel size gives incorrect result. We thus multiply it here 2115 * with 2 to match the 32 bit TILER unit size. 2116 */ 2117 width *= 2; 2118 } 2119 2120 /* 2121 * field 0 = even field = bottom field 2122 * field 1 = odd field = top field 2123 */ 2124 *offset0 = field_offset * screen_width * ps; 2125 *offset1 = 0; 2126 2127 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 2128 (fieldmode ? screen_width : 0), ps); 2129 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) 2130 *pix_inc = pixinc(x_predecim, 2 * ps); 2131 else 2132 *pix_inc = pixinc(x_predecim, ps); 2133 } 2134 2135 /* 2136 * This function is used to avoid synclosts in OMAP3, because of some 2137 * undocumented horizontal position and timing related limitations. 2138 */ 2139 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2140 const struct videomode *vm, u16 pos_x, 2141 u16 width, u16 height, u16 out_width, u16 out_height, 2142 bool five_taps) 2143 { 2144 const int ds = DIV_ROUND_UP(height, out_height); 2145 unsigned long nonactive; 2146 static const u8 limits[3] = { 8, 10, 20 }; 2147 u64 val, blank; 2148 int i; 2149 2150 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + 2151 vm->hback_porch - out_width; 2152 2153 i = 0; 2154 if (out_height < height) 2155 i++; 2156 if (out_width < width) 2157 i++; 2158 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * 2159 lclk, pclk); 2160 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2161 if (blank <= limits[i]) 2162 return -EINVAL; 2163 2164 /* FIXME add checks for 3-tap filter once the limitations are known */ 2165 if (!five_taps) 2166 return 0; 2167 2168 /* 2169 * Pixel data should be prepared before visible display point starts. 2170 * So, atleast DS-2 lines must have already been fetched by DISPC 2171 * during nonactive - pos_x period. 2172 */ 2173 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 2174 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2175 val, max(0, ds - 2) * width); 2176 if (val < max(0, ds - 2) * width) 2177 return -EINVAL; 2178 2179 /* 2180 * All lines need to be refilled during the nonactive period of which 2181 * only one line can be loaded during the active period. So, atleast 2182 * DS - 1 lines should be loaded during nonactive period. 2183 */ 2184 val = div_u64((u64)nonactive * lclk, pclk); 2185 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2186 val, max(0, ds - 1) * width); 2187 if (val < max(0, ds - 1) * width) 2188 return -EINVAL; 2189 2190 return 0; 2191 } 2192 2193 static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2194 const struct videomode *vm, u16 width, 2195 u16 height, u16 out_width, u16 out_height, 2196 u32 fourcc) 2197 { 2198 u32 core_clk = 0; 2199 u64 tmp; 2200 2201 if (height <= out_height && width <= out_width) 2202 return (unsigned long) pclk; 2203 2204 if (height > out_height) { 2205 unsigned int ppl = vm->hactive; 2206 2207 tmp = (u64)pclk * height * out_width; 2208 do_div(tmp, 2 * out_height * ppl); 2209 core_clk = tmp; 2210 2211 if (height > 2 * out_height) { 2212 if (ppl == out_width) 2213 return 0; 2214 2215 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2216 do_div(tmp, 2 * out_height * (ppl - out_width)); 2217 core_clk = max_t(u32, core_clk, tmp); 2218 } 2219 } 2220 2221 if (width > out_width) { 2222 tmp = (u64)pclk * width; 2223 do_div(tmp, out_width); 2224 core_clk = max_t(u32, core_clk, tmp); 2225 2226 if (fourcc == DRM_FORMAT_XRGB8888) 2227 core_clk <<= 1; 2228 } 2229 2230 return core_clk; 2231 } 2232 2233 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2234 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2235 { 2236 if (height > out_height && width > out_width) 2237 return pclk * 4; 2238 else 2239 return pclk * 2; 2240 } 2241 2242 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2243 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2244 { 2245 unsigned int hf, vf; 2246 2247 /* 2248 * FIXME how to determine the 'A' factor 2249 * for the no downscaling case ? 2250 */ 2251 2252 if (width > 3 * out_width) 2253 hf = 4; 2254 else if (width > 2 * out_width) 2255 hf = 3; 2256 else if (width > out_width) 2257 hf = 2; 2258 else 2259 hf = 1; 2260 if (height > out_height) 2261 vf = 2; 2262 else 2263 vf = 1; 2264 2265 return pclk * vf * hf; 2266 } 2267 2268 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2269 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2270 { 2271 /* 2272 * If the overlay/writeback is in mem to mem mode, there are no 2273 * downscaling limitations with respect to pixel clock, return 1 as 2274 * required core clock to represent that we have sufficient enough 2275 * core clock to do maximum downscaling 2276 */ 2277 if (mem_to_mem) 2278 return 1; 2279 2280 if (width > out_width) 2281 return DIV_ROUND_UP(pclk, out_width) * width; 2282 else 2283 return pclk; 2284 } 2285 2286 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, 2287 unsigned long pclk, unsigned long lclk, 2288 const struct videomode *vm, 2289 u16 width, u16 height, 2290 u16 out_width, u16 out_height, 2291 u32 fourcc, bool *five_taps, 2292 int *x_predecim, int *y_predecim, 2293 int *decim_x, int *decim_y, 2294 u16 pos_x, unsigned long *core_clk, 2295 bool mem_to_mem) 2296 { 2297 int error; 2298 u16 in_width, in_height; 2299 int min_factor = min(*decim_x, *decim_y); 2300 const int maxsinglelinewidth = dispc->feat->max_line_width; 2301 2302 *five_taps = false; 2303 2304 do { 2305 in_height = height / *decim_y; 2306 in_width = width / *decim_x; 2307 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, 2308 in_height, out_width, out_height, mem_to_mem); 2309 error = (in_width > maxsinglelinewidth || !*core_clk || 2310 *core_clk > dispc_core_clk_rate(dispc)); 2311 if (error) { 2312 if (*decim_x == *decim_y) { 2313 *decim_x = min_factor; 2314 ++*decim_y; 2315 } else { 2316 swap(*decim_x, *decim_y); 2317 if (*decim_x < *decim_y) 2318 ++*decim_x; 2319 } 2320 } 2321 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2322 2323 if (error) { 2324 DSSERR("failed to find scaling settings\n"); 2325 return -EINVAL; 2326 } 2327 2328 if (in_width > maxsinglelinewidth) { 2329 DSSERR("Cannot scale max input width exceeded\n"); 2330 return -EINVAL; 2331 } 2332 return 0; 2333 } 2334 2335 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, 2336 unsigned long pclk, unsigned long lclk, 2337 const struct videomode *vm, 2338 u16 width, u16 height, 2339 u16 out_width, u16 out_height, 2340 u32 fourcc, bool *five_taps, 2341 int *x_predecim, int *y_predecim, 2342 int *decim_x, int *decim_y, 2343 u16 pos_x, unsigned long *core_clk, 2344 bool mem_to_mem) 2345 { 2346 int error; 2347 u16 in_width, in_height; 2348 const int maxsinglelinewidth = dispc->feat->max_line_width; 2349 2350 do { 2351 in_height = height / *decim_y; 2352 in_width = width / *decim_x; 2353 *five_taps = in_height > out_height; 2354 2355 if (in_width > maxsinglelinewidth) 2356 if (in_height > out_height && 2357 in_height < out_height * 2) 2358 *five_taps = false; 2359 again: 2360 if (*five_taps) 2361 *core_clk = calc_core_clk_five_taps(pclk, vm, 2362 in_width, in_height, out_width, 2363 out_height, fourcc); 2364 else 2365 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, 2366 in_height, out_width, out_height, 2367 mem_to_mem); 2368 2369 error = check_horiz_timing_omap3(pclk, lclk, vm, 2370 pos_x, in_width, in_height, out_width, 2371 out_height, *five_taps); 2372 if (error && *five_taps) { 2373 *five_taps = false; 2374 goto again; 2375 } 2376 2377 error = (error || in_width > maxsinglelinewidth * 2 || 2378 (in_width > maxsinglelinewidth && *five_taps) || 2379 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); 2380 2381 if (!error) { 2382 /* verify that we're inside the limits of scaler */ 2383 if (in_width / 4 > out_width) 2384 error = 1; 2385 2386 if (*five_taps) { 2387 if (in_height / 4 > out_height) 2388 error = 1; 2389 } else { 2390 if (in_height / 2 > out_height) 2391 error = 1; 2392 } 2393 } 2394 2395 if (error) 2396 ++*decim_y; 2397 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2398 2399 if (error) { 2400 DSSERR("failed to find scaling settings\n"); 2401 return -EINVAL; 2402 } 2403 2404 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width, 2405 in_height, out_width, out_height, *five_taps)) { 2406 DSSERR("horizontal timing too tight\n"); 2407 return -EINVAL; 2408 } 2409 2410 if (in_width > (maxsinglelinewidth * 2)) { 2411 DSSERR("Cannot setup scaling\n"); 2412 DSSERR("width exceeds maximum width possible\n"); 2413 return -EINVAL; 2414 } 2415 2416 if (in_width > maxsinglelinewidth && *five_taps) { 2417 DSSERR("cannot setup scaling with five taps\n"); 2418 return -EINVAL; 2419 } 2420 return 0; 2421 } 2422 2423 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, 2424 unsigned long pclk, unsigned long lclk, 2425 const struct videomode *vm, 2426 u16 width, u16 height, 2427 u16 out_width, u16 out_height, 2428 u32 fourcc, bool *five_taps, 2429 int *x_predecim, int *y_predecim, 2430 int *decim_x, int *decim_y, 2431 u16 pos_x, unsigned long *core_clk, 2432 bool mem_to_mem) 2433 { 2434 u16 in_width, in_width_max; 2435 int decim_x_min = *decim_x; 2436 u16 in_height = height / *decim_y; 2437 const int maxsinglelinewidth = dispc->feat->max_line_width; 2438 const int maxdownscale = dispc->feat->max_downscale; 2439 2440 if (mem_to_mem) { 2441 in_width_max = out_width * maxdownscale; 2442 } else { 2443 in_width_max = dispc_core_clk_rate(dispc) 2444 / DIV_ROUND_UP(pclk, out_width); 2445 } 2446 2447 *decim_x = DIV_ROUND_UP(width, in_width_max); 2448 2449 *decim_x = max(*decim_x, decim_x_min); 2450 if (*decim_x > *x_predecim) 2451 return -EINVAL; 2452 2453 do { 2454 in_width = width / *decim_x; 2455 } while (*decim_x <= *x_predecim && 2456 in_width > maxsinglelinewidth && ++*decim_x); 2457 2458 if (in_width > maxsinglelinewidth) { 2459 DSSERR("Cannot scale width exceeds max line width\n"); 2460 return -EINVAL; 2461 } 2462 2463 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) { 2464 /* 2465 * Let's disable all scaling that requires horizontal 2466 * decimation with higher factor than 4, until we have 2467 * better estimates of what we can and can not 2468 * do. However, NV12 color format appears to work Ok 2469 * with all decimation factors. 2470 * 2471 * When decimating horizontally by more that 4 the dss 2472 * is not able to fetch the data in burst mode. When 2473 * this happens it is hard to tell if there enough 2474 * bandwidth. Despite what theory says this appears to 2475 * be true also for 16-bit color formats. 2476 */ 2477 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x); 2478 2479 return -EINVAL; 2480 } 2481 2482 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, 2483 out_width, out_height, mem_to_mem); 2484 return 0; 2485 } 2486 2487 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane) 2488 { 2489 return dispc->feat->overlay_caps[plane]; 2490 } 2491 2492 #define DIV_FRAC(dividend, divisor) \ 2493 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2494 2495 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, 2496 enum omap_plane_id plane, 2497 unsigned long pclk, unsigned long lclk, 2498 enum omap_overlay_caps caps, 2499 const struct videomode *vm, 2500 u16 width, u16 height, 2501 u16 out_width, u16 out_height, 2502 u32 fourcc, bool *five_taps, 2503 int *x_predecim, int *y_predecim, u16 pos_x, 2504 enum omap_dss_rotation_type rotation_type, 2505 bool mem_to_mem) 2506 { 2507 int maxhdownscale = dispc->feat->max_downscale; 2508 int maxvdownscale = dispc->feat->max_downscale; 2509 const int max_decim_limit = 16; 2510 unsigned long core_clk = 0; 2511 int decim_x, decim_y, ret; 2512 2513 if (width == out_width && height == out_height) 2514 return 0; 2515 2516 if (dispc->feat->supported_scaler_color_modes) { 2517 const u32 *modes = dispc->feat->supported_scaler_color_modes; 2518 unsigned int i; 2519 2520 for (i = 0; modes[i]; ++i) { 2521 if (modes[i] == fourcc) 2522 break; 2523 } 2524 2525 if (modes[i] == 0) 2526 return -EINVAL; 2527 } 2528 2529 if (plane == OMAP_DSS_WB) { 2530 switch (fourcc) { 2531 case DRM_FORMAT_NV12: 2532 maxhdownscale = maxvdownscale = 2; 2533 break; 2534 case DRM_FORMAT_YUYV: 2535 case DRM_FORMAT_UYVY: 2536 maxhdownscale = 2; 2537 maxvdownscale = 4; 2538 break; 2539 default: 2540 break; 2541 } 2542 } 2543 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { 2544 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2545 return -EINVAL; 2546 } 2547 2548 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2549 return -EINVAL; 2550 2551 if (mem_to_mem) { 2552 *x_predecim = *y_predecim = 1; 2553 } else { 2554 *x_predecim = max_decim_limit; 2555 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2556 dispc_has_feature(dispc, FEAT_BURST_2D)) ? 2557 2 : max_decim_limit; 2558 } 2559 2560 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale); 2561 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxvdownscale); 2562 2563 if (decim_x > *x_predecim || out_width > width * 8) 2564 return -EINVAL; 2565 2566 if (decim_y > *y_predecim || out_height > height * 8) 2567 return -EINVAL; 2568 2569 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, 2570 out_width, out_height, fourcc, 2571 five_taps, x_predecim, y_predecim, 2572 &decim_x, &decim_y, pos_x, &core_clk, 2573 mem_to_mem); 2574 if (ret) 2575 return ret; 2576 2577 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2578 width, height, 2579 out_width, out_height, 2580 out_width / width, DIV_FRAC(out_width, width), 2581 out_height / height, DIV_FRAC(out_height, height), 2582 2583 decim_x, decim_y, 2584 width / decim_x, height / decim_y, 2585 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2586 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2587 2588 *five_taps ? 5 : 3, 2589 core_clk, dispc_core_clk_rate(dispc)); 2590 2591 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { 2592 DSSERR("failed to set up scaling, " 2593 "required core clk rate = %lu Hz, " 2594 "current core clk rate = %lu Hz\n", 2595 core_clk, dispc_core_clk_rate(dispc)); 2596 return -EINVAL; 2597 } 2598 2599 *x_predecim = decim_x; 2600 *y_predecim = decim_y; 2601 return 0; 2602 } 2603 2604 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height) 2605 { 2606 *width = dispc->feat->ovl_width_max; 2607 *height = dispc->feat->ovl_height_max; 2608 } 2609 2610 static int dispc_ovl_setup_common(struct dispc_device *dispc, 2611 enum omap_plane_id plane, 2612 enum omap_overlay_caps caps, 2613 u32 paddr, u32 p_uv_addr, 2614 u16 screen_width, int pos_x, int pos_y, 2615 u16 width, u16 height, 2616 u16 out_width, u16 out_height, 2617 u32 fourcc, u8 rotation, u8 zorder, 2618 u8 pre_mult_alpha, u8 global_alpha, 2619 enum omap_dss_rotation_type rotation_type, 2620 bool replication, const struct videomode *vm, 2621 bool mem_to_mem, 2622 enum drm_color_encoding color_encoding, 2623 enum drm_color_range color_range) 2624 { 2625 bool five_taps = true; 2626 bool fieldmode = false; 2627 int r, cconv = 0; 2628 unsigned int offset0, offset1; 2629 s32 row_inc; 2630 s32 pix_inc; 2631 u16 frame_width; 2632 unsigned int field_offset = 0; 2633 u16 in_height = height; 2634 u16 in_width = width; 2635 int x_predecim = 1, y_predecim = 1; 2636 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); 2637 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); 2638 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); 2639 const struct drm_format_info *info; 2640 2641 info = drm_format_info(fourcc); 2642 2643 /* when setting up WB, dispc_plane_pclk_rate() returns 0 */ 2644 if (plane == OMAP_DSS_WB) 2645 pclk = vm->pixelclock; 2646 2647 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2648 return -EINVAL; 2649 2650 if (info->is_yuv && (in_width & 1)) { 2651 DSSERR("input width %d is not even for YUV format\n", in_width); 2652 return -EINVAL; 2653 } 2654 2655 out_width = out_width == 0 ? width : out_width; 2656 out_height = out_height == 0 ? height : out_height; 2657 2658 if (plane != OMAP_DSS_WB) { 2659 if (ilace && height == out_height) 2660 fieldmode = true; 2661 2662 if (ilace) { 2663 if (fieldmode) 2664 in_height /= 2; 2665 pos_y /= 2; 2666 out_height /= 2; 2667 2668 DSSDBG("adjusting for ilace: height %d, pos_y %d, out_height %d\n", 2669 in_height, pos_y, out_height); 2670 } 2671 } 2672 2673 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) 2674 return -EINVAL; 2675 2676 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, 2677 in_height, out_width, out_height, fourcc, 2678 &five_taps, &x_predecim, &y_predecim, pos_x, 2679 rotation_type, mem_to_mem); 2680 if (r) 2681 return r; 2682 2683 in_width = in_width / x_predecim; 2684 in_height = in_height / y_predecim; 2685 2686 if (x_predecim > 1 || y_predecim > 1) 2687 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2688 x_predecim, y_predecim, in_width, in_height); 2689 2690 if (info->is_yuv && (in_width & 1)) { 2691 DSSDBG("predecimated input width is not even for YUV format\n"); 2692 DSSDBG("adjusting input width %d -> %d\n", 2693 in_width, in_width & ~1); 2694 2695 in_width &= ~1; 2696 } 2697 2698 if (info->is_yuv) 2699 cconv = 1; 2700 2701 if (ilace && !fieldmode) { 2702 /* 2703 * when downscaling the bottom field may have to start several 2704 * source lines below the top field. Unfortunately ACCUI 2705 * registers will only hold the fractional part of the offset 2706 * so the integer part must be added to the base address of the 2707 * bottom field. 2708 */ 2709 if (!in_height || in_height == out_height) 2710 field_offset = 0; 2711 else 2712 field_offset = in_height / out_height / 2; 2713 } 2714 2715 /* Fields are independent but interleaved in memory. */ 2716 if (fieldmode) 2717 field_offset = 1; 2718 2719 offset0 = 0; 2720 offset1 = 0; 2721 row_inc = 0; 2722 pix_inc = 0; 2723 2724 if (plane == OMAP_DSS_WB) 2725 frame_width = out_width; 2726 else 2727 frame_width = in_width; 2728 2729 calc_offset(screen_width, frame_width, 2730 fourcc, fieldmode, field_offset, 2731 &offset0, &offset1, &row_inc, &pix_inc, 2732 x_predecim, y_predecim, 2733 rotation_type, rotation); 2734 2735 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2736 offset0, offset1, row_inc, pix_inc); 2737 2738 dispc_ovl_set_color_mode(dispc, plane, fourcc); 2739 2740 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); 2741 2742 if (dispc->feat->reverse_ilace_field_order) 2743 swap(offset0, offset1); 2744 2745 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); 2746 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); 2747 2748 if (fourcc == DRM_FORMAT_NV12) { 2749 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); 2750 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); 2751 } 2752 2753 if (dispc->feat->last_pixel_inc_missing) 2754 row_inc += pix_inc - 1; 2755 2756 dispc_ovl_set_row_inc(dispc, plane, row_inc); 2757 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); 2758 2759 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2760 in_height, out_width, out_height); 2761 2762 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); 2763 2764 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); 2765 2766 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2767 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, 2768 out_width, out_height, ilace, five_taps, 2769 fieldmode, fourcc, rotation); 2770 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); 2771 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); 2772 2773 if (plane != OMAP_DSS_WB) 2774 dispc_ovl_set_csc(dispc, plane, color_encoding, color_range); 2775 } 2776 2777 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, 2778 fourcc); 2779 2780 dispc_ovl_set_zorder(dispc, plane, caps, zorder); 2781 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); 2782 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); 2783 2784 dispc_ovl_enable_replication(dispc, plane, caps, replication); 2785 2786 return 0; 2787 } 2788 2789 int dispc_ovl_setup(struct dispc_device *dispc, 2790 enum omap_plane_id plane, 2791 const struct omap_overlay_info *oi, 2792 const struct videomode *vm, bool mem_to_mem, 2793 enum omap_channel channel) 2794 { 2795 int r; 2796 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; 2797 const bool replication = true; 2798 2799 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2800 " %dx%d, cmode %x, rot %d, chan %d repl %d\n", 2801 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2802 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2803 oi->fourcc, oi->rotation, channel, replication); 2804 2805 dispc_ovl_set_channel_out(dispc, plane, channel); 2806 2807 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, 2808 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2809 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, 2810 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2811 oi->rotation_type, replication, vm, mem_to_mem, 2812 oi->color_encoding, oi->color_range); 2813 2814 return r; 2815 } 2816 2817 int dispc_wb_setup(struct dispc_device *dispc, 2818 const struct omap_dss_writeback_info *wi, 2819 bool mem_to_mem, const struct videomode *vm, 2820 enum dss_writeback_channel channel_in) 2821 { 2822 int r; 2823 u32 l; 2824 enum omap_plane_id plane = OMAP_DSS_WB; 2825 const int pos_x = 0, pos_y = 0; 2826 const u8 zorder = 0, global_alpha = 0; 2827 const bool replication = true; 2828 bool truncation; 2829 int in_width = vm->hactive; 2830 int in_height = vm->vactive; 2831 enum omap_overlay_caps caps = 2832 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2833 2834 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2835 in_height /= 2; 2836 2837 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " 2838 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, 2839 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); 2840 2841 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, 2842 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2843 wi->height, wi->fourcc, wi->rotation, zorder, 2844 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2845 replication, vm, mem_to_mem, DRM_COLOR_YCBCR_BT601, 2846 DRM_COLOR_YCBCR_LIMITED_RANGE); 2847 if (r) 2848 return r; 2849 2850 switch (wi->fourcc) { 2851 case DRM_FORMAT_RGB565: 2852 case DRM_FORMAT_RGB888: 2853 case DRM_FORMAT_ARGB4444: 2854 case DRM_FORMAT_RGBA4444: 2855 case DRM_FORMAT_RGBX4444: 2856 case DRM_FORMAT_ARGB1555: 2857 case DRM_FORMAT_XRGB1555: 2858 case DRM_FORMAT_XRGB4444: 2859 truncation = true; 2860 break; 2861 default: 2862 truncation = false; 2863 break; 2864 } 2865 2866 /* setup extra DISPC_WB_ATTRIBUTES */ 2867 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); 2868 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ 2869 l = FLD_MOD(l, channel_in, 18, 16); /* CHANNELIN */ 2870 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ 2871 if (mem_to_mem) 2872 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ 2873 else 2874 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ 2875 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); 2876 2877 if (mem_to_mem) { 2878 /* WBDELAYCOUNT */ 2879 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); 2880 } else { 2881 u32 wbdelay; 2882 2883 if (channel_in == DSS_WB_TV_MGR) 2884 wbdelay = vm->vsync_len + vm->vback_porch; 2885 else 2886 wbdelay = vm->vfront_porch + vm->vsync_len + 2887 vm->vback_porch; 2888 2889 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2890 wbdelay /= 2; 2891 2892 wbdelay = min(wbdelay, 255u); 2893 2894 /* WBDELAYCOUNT */ 2895 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2896 } 2897 2898 return 0; 2899 } 2900 2901 bool dispc_has_writeback(struct dispc_device *dispc) 2902 { 2903 return dispc->feat->has_writeback; 2904 } 2905 2906 int dispc_ovl_enable(struct dispc_device *dispc, 2907 enum omap_plane_id plane, bool enable) 2908 { 2909 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2910 2911 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2912 2913 return 0; 2914 } 2915 2916 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, 2917 bool act_high) 2918 { 2919 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) 2920 return; 2921 2922 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2923 } 2924 2925 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) 2926 { 2927 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) 2928 return; 2929 2930 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2931 } 2932 2933 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) 2934 { 2935 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) 2936 return; 2937 2938 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2939 } 2940 2941 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, 2942 enum omap_channel channel, 2943 bool enable) 2944 { 2945 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2946 } 2947 2948 2949 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, 2950 enum omap_channel channel) 2951 { 2952 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); 2953 } 2954 2955 static void dispc_set_loadmode(struct dispc_device *dispc, 2956 enum omap_dss_load_mode mode) 2957 { 2958 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); 2959 } 2960 2961 2962 static void dispc_mgr_set_default_color(struct dispc_device *dispc, 2963 enum omap_channel channel, u32 color) 2964 { 2965 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); 2966 } 2967 2968 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, 2969 enum omap_channel ch, 2970 enum omap_dss_trans_key_type type, 2971 u32 trans_key) 2972 { 2973 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); 2974 2975 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); 2976 } 2977 2978 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, 2979 enum omap_channel ch, bool enable) 2980 { 2981 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); 2982 } 2983 2984 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, 2985 enum omap_channel ch, 2986 bool enable) 2987 { 2988 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) 2989 return; 2990 2991 if (ch == OMAP_DSS_CHANNEL_LCD) 2992 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); 2993 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2994 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); 2995 } 2996 2997 void dispc_mgr_setup(struct dispc_device *dispc, 2998 enum omap_channel channel, 2999 const struct omap_overlay_manager_info *info) 3000 { 3001 dispc_mgr_set_default_color(dispc, channel, info->default_color); 3002 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, 3003 info->trans_key); 3004 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); 3005 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, 3006 info->partial_alpha_enabled); 3007 if (dispc_has_feature(dispc, FEAT_CPR)) { 3008 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); 3009 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); 3010 } 3011 } 3012 3013 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, 3014 enum omap_channel channel, 3015 u8 data_lines) 3016 { 3017 int code; 3018 3019 switch (data_lines) { 3020 case 12: 3021 code = 0; 3022 break; 3023 case 16: 3024 code = 1; 3025 break; 3026 case 18: 3027 code = 2; 3028 break; 3029 case 24: 3030 code = 3; 3031 break; 3032 default: 3033 BUG(); 3034 return; 3035 } 3036 3037 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); 3038 } 3039 3040 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, 3041 enum dss_io_pad_mode mode) 3042 { 3043 u32 l; 3044 int gpout0, gpout1; 3045 3046 switch (mode) { 3047 case DSS_IO_PAD_MODE_RESET: 3048 gpout0 = 0; 3049 gpout1 = 0; 3050 break; 3051 case DSS_IO_PAD_MODE_RFBI: 3052 gpout0 = 1; 3053 gpout1 = 0; 3054 break; 3055 case DSS_IO_PAD_MODE_BYPASS: 3056 gpout0 = 1; 3057 gpout1 = 1; 3058 break; 3059 default: 3060 BUG(); 3061 return; 3062 } 3063 3064 l = dispc_read_reg(dispc, DISPC_CONTROL); 3065 l = FLD_MOD(l, gpout0, 15, 15); 3066 l = FLD_MOD(l, gpout1, 16, 16); 3067 dispc_write_reg(dispc, DISPC_CONTROL, l); 3068 } 3069 3070 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, 3071 enum omap_channel channel, bool enable) 3072 { 3073 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); 3074 } 3075 3076 void dispc_mgr_set_lcd_config(struct dispc_device *dispc, 3077 enum omap_channel channel, 3078 const struct dss_lcd_mgr_config *config) 3079 { 3080 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); 3081 3082 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); 3083 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); 3084 3085 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); 3086 3087 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); 3088 3089 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); 3090 3091 dispc_mgr_set_lcd_type_tft(dispc, channel); 3092 } 3093 3094 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, 3095 u16 width, u16 height) 3096 { 3097 return width <= dispc->feat->mgr_width_max && 3098 height <= dispc->feat->mgr_height_max; 3099 } 3100 3101 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, 3102 int hsync_len, int hfp, int hbp, 3103 int vsw, int vfp, int vbp) 3104 { 3105 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || 3106 hfp < 1 || hfp > dispc->feat->hp_max || 3107 hbp < 1 || hbp > dispc->feat->hp_max || 3108 vsw < 1 || vsw > dispc->feat->sw_max || 3109 vfp < 0 || vfp > dispc->feat->vp_max || 3110 vbp < 0 || vbp > dispc->feat->vp_max) 3111 return false; 3112 return true; 3113 } 3114 3115 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, 3116 enum omap_channel channel, 3117 unsigned long pclk) 3118 { 3119 if (dss_mgr_is_lcd(channel)) 3120 return pclk <= dispc->feat->max_lcd_pclk; 3121 else 3122 return pclk <= dispc->feat->max_tv_pclk; 3123 } 3124 3125 int dispc_mgr_check_timings(struct dispc_device *dispc, 3126 enum omap_channel channel, 3127 const struct videomode *vm) 3128 { 3129 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) 3130 return MODE_BAD; 3131 3132 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) 3133 return MODE_BAD; 3134 3135 if (dss_mgr_is_lcd(channel)) { 3136 /* TODO: OMAP4+ supports interlace for LCD outputs */ 3137 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 3138 return MODE_BAD; 3139 3140 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, 3141 vm->hfront_porch, vm->hback_porch, 3142 vm->vsync_len, vm->vfront_porch, 3143 vm->vback_porch)) 3144 return MODE_BAD; 3145 } 3146 3147 return MODE_OK; 3148 } 3149 3150 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, 3151 enum omap_channel channel, 3152 const struct videomode *vm) 3153 { 3154 u32 timing_h, timing_v, l; 3155 bool onoff, rf, ipc, vs, hs, de; 3156 3157 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | 3158 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | 3159 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); 3160 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | 3161 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | 3162 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); 3163 3164 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); 3165 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); 3166 3167 vs = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW); 3168 hs = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW); 3169 de = !!(vm->flags & DISPLAY_FLAGS_DE_LOW); 3170 ipc = !!(vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE); 3171 onoff = true; /* always use the 'rf' setting */ 3172 rf = !!(vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE); 3173 3174 l = FLD_VAL(onoff, 17, 17) | 3175 FLD_VAL(rf, 16, 16) | 3176 FLD_VAL(de, 15, 15) | 3177 FLD_VAL(ipc, 14, 14) | 3178 FLD_VAL(hs, 13, 13) | 3179 FLD_VAL(vs, 12, 12); 3180 3181 /* always set ALIGN bit when available */ 3182 if (dispc->feat->supports_sync_align) 3183 l |= (1 << 18); 3184 3185 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); 3186 3187 if (dispc->syscon_pol) { 3188 const int shifts[] = { 3189 [OMAP_DSS_CHANNEL_LCD] = 0, 3190 [OMAP_DSS_CHANNEL_LCD2] = 1, 3191 [OMAP_DSS_CHANNEL_LCD3] = 2, 3192 }; 3193 3194 u32 mask, val; 3195 3196 mask = (1 << 0) | (1 << 3) | (1 << 6); 3197 val = (rf << 0) | (ipc << 3) | (onoff << 6); 3198 3199 mask <<= 16 + shifts[channel]; 3200 val <<= 16 + shifts[channel]; 3201 3202 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, 3203 mask, val); 3204 } 3205 } 3206 3207 static int vm_flag_to_int(enum display_flags flags, enum display_flags high, 3208 enum display_flags low) 3209 { 3210 if (flags & high) 3211 return 1; 3212 if (flags & low) 3213 return -1; 3214 return 0; 3215 } 3216 3217 /* change name to mode? */ 3218 void dispc_mgr_set_timings(struct dispc_device *dispc, 3219 enum omap_channel channel, 3220 const struct videomode *vm) 3221 { 3222 unsigned int xtot, ytot; 3223 unsigned long ht, vt; 3224 struct videomode t = *vm; 3225 3226 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 3227 3228 if (dispc_mgr_check_timings(dispc, channel, &t)) { 3229 BUG(); 3230 return; 3231 } 3232 3233 if (dss_mgr_is_lcd(channel)) { 3234 _dispc_mgr_set_lcd_timings(dispc, channel, &t); 3235 3236 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3237 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 3238 3239 ht = vm->pixelclock / xtot; 3240 vt = vm->pixelclock / xtot / ytot; 3241 3242 DSSDBG("pck %lu\n", vm->pixelclock); 3243 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3244 t.hsync_len, t.hfront_porch, t.hback_porch, 3245 t.vsync_len, t.vfront_porch, t.vback_porch); 3246 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3247 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW), 3248 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW), 3249 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE), 3250 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW), 3251 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE)); 3252 3253 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3254 } else { 3255 if (t.flags & DISPLAY_FLAGS_INTERLACED) 3256 t.vactive /= 2; 3257 3258 if (dispc->feat->supports_double_pixel) 3259 REG_FLD_MOD(dispc, DISPC_CONTROL, 3260 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), 3261 19, 17); 3262 } 3263 3264 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); 3265 } 3266 3267 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, 3268 enum omap_channel channel, u16 lck_div, 3269 u16 pck_div) 3270 { 3271 BUG_ON(lck_div < 1); 3272 BUG_ON(pck_div < 1); 3273 3274 dispc_write_reg(dispc, DISPC_DIVISORo(channel), 3275 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3276 3277 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && 3278 channel == OMAP_DSS_CHANNEL_LCD) 3279 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; 3280 } 3281 3282 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, 3283 enum omap_channel channel, int *lck_div, 3284 int *pck_div) 3285 { 3286 u32 l; 3287 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); 3288 *lck_div = FLD_GET(l, 23, 16); 3289 *pck_div = FLD_GET(l, 7, 0); 3290 } 3291 3292 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) 3293 { 3294 unsigned long r; 3295 enum dss_clk_source src; 3296 3297 src = dss_get_dispc_clk_source(dispc->dss); 3298 3299 if (src == DSS_CLK_SRC_FCK) { 3300 r = dss_get_dispc_clk_rate(dispc->dss); 3301 } else { 3302 struct dss_pll *pll; 3303 unsigned int clkout_idx; 3304 3305 pll = dss_pll_find_by_src(dispc->dss, src); 3306 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3307 3308 r = pll->cinfo.clkout[clkout_idx]; 3309 } 3310 3311 return r; 3312 } 3313 3314 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, 3315 enum omap_channel channel) 3316 { 3317 int lcd; 3318 unsigned long r; 3319 enum dss_clk_source src; 3320 3321 /* for TV, LCLK rate is the FCLK rate */ 3322 if (!dss_mgr_is_lcd(channel)) 3323 return dispc_fclk_rate(dispc); 3324 3325 src = dss_get_lcd_clk_source(dispc->dss, channel); 3326 3327 if (src == DSS_CLK_SRC_FCK) { 3328 r = dss_get_dispc_clk_rate(dispc->dss); 3329 } else { 3330 struct dss_pll *pll; 3331 unsigned int clkout_idx; 3332 3333 pll = dss_pll_find_by_src(dispc->dss, src); 3334 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3335 3336 r = pll->cinfo.clkout[clkout_idx]; 3337 } 3338 3339 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); 3340 3341 return r / lcd; 3342 } 3343 3344 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, 3345 enum omap_channel channel) 3346 { 3347 unsigned long r; 3348 3349 if (dss_mgr_is_lcd(channel)) { 3350 int pcd; 3351 u32 l; 3352 3353 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); 3354 3355 pcd = FLD_GET(l, 7, 0); 3356 3357 r = dispc_mgr_lclk_rate(dispc, channel); 3358 3359 return r / pcd; 3360 } else { 3361 return dispc->tv_pclk_rate; 3362 } 3363 } 3364 3365 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) 3366 { 3367 dispc->tv_pclk_rate = pclk; 3368 } 3369 3370 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) 3371 { 3372 return dispc->core_clk_rate; 3373 } 3374 3375 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, 3376 enum omap_plane_id plane) 3377 { 3378 enum omap_channel channel; 3379 3380 if (plane == OMAP_DSS_WB) 3381 return 0; 3382 3383 channel = dispc_ovl_get_channel_out(dispc, plane); 3384 3385 return dispc_mgr_pclk_rate(dispc, channel); 3386 } 3387 3388 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, 3389 enum omap_plane_id plane) 3390 { 3391 enum omap_channel channel; 3392 3393 if (plane == OMAP_DSS_WB) 3394 return 0; 3395 3396 channel = dispc_ovl_get_channel_out(dispc, plane); 3397 3398 return dispc_mgr_lclk_rate(dispc, channel); 3399 } 3400 3401 static void dispc_dump_clocks_channel(struct dispc_device *dispc, 3402 struct seq_file *s, 3403 enum omap_channel channel) 3404 { 3405 int lcd, pcd; 3406 enum dss_clk_source lcd_clk_src; 3407 3408 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3409 3410 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); 3411 3412 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3413 dss_get_clk_source_name(lcd_clk_src)); 3414 3415 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); 3416 3417 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3418 dispc_mgr_lclk_rate(dispc, channel), lcd); 3419 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3420 dispc_mgr_pclk_rate(dispc, channel), pcd); 3421 } 3422 3423 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) 3424 { 3425 enum dss_clk_source dispc_clk_src; 3426 int lcd; 3427 u32 l; 3428 3429 if (dispc_runtime_get(dispc)) 3430 return; 3431 3432 seq_printf(s, "- DISPC -\n"); 3433 3434 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); 3435 seq_printf(s, "dispc fclk source = %s\n", 3436 dss_get_clk_source_name(dispc_clk_src)); 3437 3438 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); 3439 3440 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { 3441 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3442 l = dispc_read_reg(dispc, DISPC_DIVISOR); 3443 lcd = FLD_GET(l, 23, 16); 3444 3445 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3446 (dispc_fclk_rate(dispc)/lcd), lcd); 3447 } 3448 3449 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); 3450 3451 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3452 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); 3453 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3454 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); 3455 3456 dispc_runtime_put(dispc); 3457 } 3458 3459 static int dispc_dump_regs(struct seq_file *s, void *p) 3460 { 3461 struct dispc_device *dispc = s->private; 3462 int i, j; 3463 const char *mgr_names[] = { 3464 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3465 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3466 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3467 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3468 }; 3469 const char *ovl_names[] = { 3470 [OMAP_DSS_GFX] = "GFX", 3471 [OMAP_DSS_VIDEO1] = "VID1", 3472 [OMAP_DSS_VIDEO2] = "VID2", 3473 [OMAP_DSS_VIDEO3] = "VID3", 3474 [OMAP_DSS_WB] = "WB", 3475 }; 3476 const char **p_names; 3477 3478 #define DUMPREG(dispc, r) \ 3479 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) 3480 3481 if (dispc_runtime_get(dispc)) 3482 return 0; 3483 3484 /* DISPC common registers */ 3485 DUMPREG(dispc, DISPC_REVISION); 3486 DUMPREG(dispc, DISPC_SYSCONFIG); 3487 DUMPREG(dispc, DISPC_SYSSTATUS); 3488 DUMPREG(dispc, DISPC_IRQSTATUS); 3489 DUMPREG(dispc, DISPC_IRQENABLE); 3490 DUMPREG(dispc, DISPC_CONTROL); 3491 DUMPREG(dispc, DISPC_CONFIG); 3492 DUMPREG(dispc, DISPC_CAPABLE); 3493 DUMPREG(dispc, DISPC_LINE_STATUS); 3494 DUMPREG(dispc, DISPC_LINE_NUMBER); 3495 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || 3496 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) 3497 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); 3498 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { 3499 DUMPREG(dispc, DISPC_CONTROL2); 3500 DUMPREG(dispc, DISPC_CONFIG2); 3501 } 3502 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { 3503 DUMPREG(dispc, DISPC_CONTROL3); 3504 DUMPREG(dispc, DISPC_CONFIG3); 3505 } 3506 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3507 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3508 3509 #undef DUMPREG 3510 3511 #define DISPC_REG(i, name) name(i) 3512 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3513 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3514 dispc_read_reg(dispc, DISPC_REG(i, r))) 3515 3516 p_names = mgr_names; 3517 3518 /* DISPC channel specific registers */ 3519 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { 3520 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); 3521 DUMPREG(dispc, i, DISPC_TRANS_COLOR); 3522 DUMPREG(dispc, i, DISPC_SIZE_MGR); 3523 3524 if (i == OMAP_DSS_CHANNEL_DIGIT) 3525 continue; 3526 3527 DUMPREG(dispc, i, DISPC_TIMING_H); 3528 DUMPREG(dispc, i, DISPC_TIMING_V); 3529 DUMPREG(dispc, i, DISPC_POL_FREQ); 3530 DUMPREG(dispc, i, DISPC_DIVISORo); 3531 3532 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); 3533 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); 3534 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); 3535 3536 if (dispc_has_feature(dispc, FEAT_CPR)) { 3537 DUMPREG(dispc, i, DISPC_CPR_COEF_R); 3538 DUMPREG(dispc, i, DISPC_CPR_COEF_G); 3539 DUMPREG(dispc, i, DISPC_CPR_COEF_B); 3540 } 3541 } 3542 3543 p_names = ovl_names; 3544 3545 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { 3546 DUMPREG(dispc, i, DISPC_OVL_BA0); 3547 DUMPREG(dispc, i, DISPC_OVL_BA1); 3548 DUMPREG(dispc, i, DISPC_OVL_POSITION); 3549 DUMPREG(dispc, i, DISPC_OVL_SIZE); 3550 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); 3551 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); 3552 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); 3553 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); 3554 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); 3555 3556 if (dispc_has_feature(dispc, FEAT_PRELOAD)) 3557 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); 3558 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3559 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); 3560 3561 if (i == OMAP_DSS_GFX) { 3562 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); 3563 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); 3564 continue; 3565 } 3566 3567 DUMPREG(dispc, i, DISPC_OVL_FIR); 3568 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); 3569 DUMPREG(dispc, i, DISPC_OVL_ACCU0); 3570 DUMPREG(dispc, i, DISPC_OVL_ACCU1); 3571 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3572 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); 3573 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); 3574 DUMPREG(dispc, i, DISPC_OVL_FIR2); 3575 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); 3576 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); 3577 } 3578 if (dispc_has_feature(dispc, FEAT_ATTR2)) 3579 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); 3580 } 3581 3582 if (dispc->feat->has_writeback) { 3583 i = OMAP_DSS_WB; 3584 DUMPREG(dispc, i, DISPC_OVL_BA0); 3585 DUMPREG(dispc, i, DISPC_OVL_BA1); 3586 DUMPREG(dispc, i, DISPC_OVL_SIZE); 3587 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); 3588 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); 3589 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); 3590 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); 3591 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); 3592 3593 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3594 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); 3595 3596 DUMPREG(dispc, i, DISPC_OVL_FIR); 3597 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); 3598 DUMPREG(dispc, i, DISPC_OVL_ACCU0); 3599 DUMPREG(dispc, i, DISPC_OVL_ACCU1); 3600 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3601 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); 3602 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); 3603 DUMPREG(dispc, i, DISPC_OVL_FIR2); 3604 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); 3605 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); 3606 } 3607 if (dispc_has_feature(dispc, FEAT_ATTR2)) 3608 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); 3609 } 3610 3611 #undef DISPC_REG 3612 #undef DUMPREG 3613 3614 #define DISPC_REG(plane, name, i) name(plane, i) 3615 #define DUMPREG(dispc, plane, name, i) \ 3616 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3617 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3618 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) 3619 3620 /* Video pipeline coefficient registers */ 3621 3622 /* start from OMAP_DSS_VIDEO1 */ 3623 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { 3624 for (j = 0; j < 8; j++) 3625 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); 3626 3627 for (j = 0; j < 8; j++) 3628 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); 3629 3630 for (j = 0; j < 5; j++) 3631 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); 3632 3633 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { 3634 for (j = 0; j < 8; j++) 3635 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); 3636 } 3637 3638 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { 3639 for (j = 0; j < 8; j++) 3640 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); 3641 3642 for (j = 0; j < 8; j++) 3643 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); 3644 3645 for (j = 0; j < 8; j++) 3646 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); 3647 } 3648 } 3649 3650 dispc_runtime_put(dispc); 3651 3652 #undef DISPC_REG 3653 #undef DUMPREG 3654 3655 return 0; 3656 } 3657 3658 /* calculate clock rates using dividers in cinfo */ 3659 int dispc_calc_clock_rates(struct dispc_device *dispc, 3660 unsigned long dispc_fclk_rate, 3661 struct dispc_clock_info *cinfo) 3662 { 3663 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3664 return -EINVAL; 3665 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3666 return -EINVAL; 3667 3668 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3669 cinfo->pck = cinfo->lck / cinfo->pck_div; 3670 3671 return 0; 3672 } 3673 3674 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, 3675 unsigned long pck_min, unsigned long pck_max, 3676 dispc_div_calc_func func, void *data) 3677 { 3678 int lckd, lckd_start, lckd_stop; 3679 int pckd, pckd_start, pckd_stop; 3680 unsigned long pck, lck; 3681 unsigned long lck_max; 3682 unsigned long pckd_hw_min, pckd_hw_max; 3683 unsigned int min_fck_per_pck; 3684 unsigned long fck; 3685 3686 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK 3687 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; 3688 #else 3689 min_fck_per_pck = 0; 3690 #endif 3691 3692 pckd_hw_min = dispc->feat->min_pcd; 3693 pckd_hw_max = 255; 3694 3695 lck_max = dss_get_max_fck_rate(dispc->dss); 3696 3697 pck_min = pck_min ? pck_min : 1; 3698 pck_max = pck_max ? pck_max : ULONG_MAX; 3699 3700 lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul); 3701 lckd_stop = min(dispc_freq / pck_min, 255ul); 3702 3703 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3704 lck = dispc_freq / lckd; 3705 3706 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3707 pckd_stop = min(lck / pck_min, pckd_hw_max); 3708 3709 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3710 pck = lck / pckd; 3711 3712 /* 3713 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3714 * clock, which means we're configuring DISPC fclk here 3715 * also. Thus we need to use the calculated lck. For 3716 * OMAP4+ the DISPC fclk is a separate clock. 3717 */ 3718 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) 3719 fck = dispc_core_clk_rate(dispc); 3720 else 3721 fck = lck; 3722 3723 if (fck < pck * min_fck_per_pck) 3724 continue; 3725 3726 if (func(lckd, pckd, lck, pck, data)) 3727 return true; 3728 } 3729 } 3730 3731 return false; 3732 } 3733 3734 void dispc_mgr_set_clock_div(struct dispc_device *dispc, 3735 enum omap_channel channel, 3736 const struct dispc_clock_info *cinfo) 3737 { 3738 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3739 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3740 3741 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, 3742 cinfo->pck_div); 3743 } 3744 3745 int dispc_mgr_get_clock_div(struct dispc_device *dispc, 3746 enum omap_channel channel, 3747 struct dispc_clock_info *cinfo) 3748 { 3749 unsigned long fck; 3750 3751 fck = dispc_fclk_rate(dispc); 3752 3753 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); 3754 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); 3755 3756 cinfo->lck = fck / cinfo->lck_div; 3757 cinfo->pck = cinfo->lck / cinfo->pck_div; 3758 3759 return 0; 3760 } 3761 3762 u32 dispc_read_irqstatus(struct dispc_device *dispc) 3763 { 3764 return dispc_read_reg(dispc, DISPC_IRQSTATUS); 3765 } 3766 3767 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) 3768 { 3769 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); 3770 } 3771 3772 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) 3773 { 3774 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); 3775 3776 /* clear the irqstatus for newly enabled irqs */ 3777 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); 3778 3779 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); 3780 3781 /* flush posted write */ 3782 dispc_read_reg(dispc, DISPC_IRQENABLE); 3783 } 3784 3785 void dispc_enable_sidle(struct dispc_device *dispc) 3786 { 3787 /* SIDLEMODE: smart idle */ 3788 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); 3789 } 3790 3791 void dispc_disable_sidle(struct dispc_device *dispc) 3792 { 3793 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3794 } 3795 3796 u32 dispc_mgr_gamma_size(struct dispc_device *dispc, 3797 enum omap_channel channel) 3798 { 3799 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3800 3801 if (!dispc->feat->has_gamma_table) 3802 return 0; 3803 3804 return gdesc->len; 3805 } 3806 3807 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, 3808 enum omap_channel channel) 3809 { 3810 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3811 u32 *table = dispc->gamma_table[channel]; 3812 unsigned int i; 3813 3814 DSSDBG("%s: channel %d\n", __func__, channel); 3815 3816 for (i = 0; i < gdesc->len; ++i) { 3817 u32 v = table[i]; 3818 3819 if (gdesc->has_index) 3820 v |= i << 24; 3821 else if (i == 0) 3822 v |= 1 << 31; 3823 3824 dispc_write_reg(dispc, gdesc->reg, v); 3825 } 3826 } 3827 3828 static void dispc_restore_gamma_tables(struct dispc_device *dispc) 3829 { 3830 DSSDBG("%s()\n", __func__); 3831 3832 if (!dispc->feat->has_gamma_table) 3833 return; 3834 3835 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); 3836 3837 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); 3838 3839 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3840 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); 3841 3842 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3843 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); 3844 } 3845 3846 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 3847 { .red = 0, .green = 0, .blue = 0, }, 3848 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 3849 }; 3850 3851 void dispc_mgr_set_gamma(struct dispc_device *dispc, 3852 enum omap_channel channel, 3853 const struct drm_color_lut *lut, 3854 unsigned int length) 3855 { 3856 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3857 u32 *table = dispc->gamma_table[channel]; 3858 uint i; 3859 3860 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__, 3861 channel, length, gdesc->len); 3862 3863 if (!dispc->feat->has_gamma_table) 3864 return; 3865 3866 if (lut == NULL || length < 2) { 3867 lut = dispc_mgr_gamma_default_lut; 3868 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut); 3869 } 3870 3871 for (i = 0; i < length - 1; ++i) { 3872 uint first = i * (gdesc->len - 1) / (length - 1); 3873 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); 3874 uint w = last - first; 3875 u16 r, g, b; 3876 uint j; 3877 3878 if (w == 0) 3879 continue; 3880 3881 for (j = 0; j <= w; j++) { 3882 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; 3883 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; 3884 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; 3885 3886 r >>= 16 - gdesc->bits; 3887 g >>= 16 - gdesc->bits; 3888 b >>= 16 - gdesc->bits; 3889 3890 table[first + j] = (r << (gdesc->bits * 2)) | 3891 (g << gdesc->bits) | b; 3892 } 3893 } 3894 3895 if (dispc->is_enabled) 3896 dispc_mgr_write_gamma_table(dispc, channel); 3897 } 3898 3899 static int dispc_init_gamma_tables(struct dispc_device *dispc) 3900 { 3901 int channel; 3902 3903 if (!dispc->feat->has_gamma_table) 3904 return 0; 3905 3906 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { 3907 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3908 u32 *gt; 3909 3910 if (channel == OMAP_DSS_CHANNEL_LCD2 && 3911 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) 3912 continue; 3913 3914 if (channel == OMAP_DSS_CHANNEL_LCD3 && 3915 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) 3916 continue; 3917 3918 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, 3919 sizeof(u32), GFP_KERNEL); 3920 if (!gt) 3921 return -ENOMEM; 3922 3923 dispc->gamma_table[channel] = gt; 3924 3925 dispc_mgr_set_gamma(dispc, channel, NULL, 0); 3926 } 3927 return 0; 3928 } 3929 3930 static void _omap_dispc_initial_config(struct dispc_device *dispc) 3931 { 3932 u32 l; 3933 3934 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3935 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { 3936 l = dispc_read_reg(dispc, DISPC_DIVISOR); 3937 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3938 l = FLD_MOD(l, 1, 0, 0); 3939 l = FLD_MOD(l, 1, 23, 16); 3940 dispc_write_reg(dispc, DISPC_DIVISOR, l); 3941 3942 dispc->core_clk_rate = dispc_fclk_rate(dispc); 3943 } 3944 3945 /* Use gamma table mode, instead of palette mode */ 3946 if (dispc->feat->has_gamma_table) 3947 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); 3948 3949 /* For older DSS versions (FEAT_FUNCGATED) this enables 3950 * func-clock auto-gating. For newer versions 3951 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. 3952 */ 3953 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || 3954 dispc->feat->has_gamma_table) 3955 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); 3956 3957 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); 3958 3959 dispc_init_fifos(dispc); 3960 3961 dispc_configure_burst_sizes(dispc); 3962 3963 dispc_ovl_enable_zorder_planes(dispc); 3964 3965 if (dispc->feat->mstandby_workaround) 3966 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); 3967 3968 if (dispc_has_feature(dispc, FEAT_MFLAG)) 3969 dispc_init_mflag(dispc); 3970 } 3971 3972 static const enum dispc_feature_id omap2_dispc_features_list[] = { 3973 FEAT_LCDENABLEPOL, 3974 FEAT_LCDENABLESIGNAL, 3975 FEAT_PCKFREEENABLE, 3976 FEAT_FUNCGATED, 3977 FEAT_ROWREPEATENABLE, 3978 FEAT_RESIZECONF, 3979 }; 3980 3981 static const enum dispc_feature_id omap3_dispc_features_list[] = { 3982 FEAT_LCDENABLEPOL, 3983 FEAT_LCDENABLESIGNAL, 3984 FEAT_PCKFREEENABLE, 3985 FEAT_FUNCGATED, 3986 FEAT_LINEBUFFERSPLIT, 3987 FEAT_ROWREPEATENABLE, 3988 FEAT_RESIZECONF, 3989 FEAT_CPR, 3990 FEAT_PRELOAD, 3991 FEAT_FIR_COEF_V, 3992 FEAT_ALPHA_FIXED_ZORDER, 3993 FEAT_FIFO_MERGE, 3994 FEAT_OMAP3_DSI_FIFO_BUG, 3995 }; 3996 3997 static const enum dispc_feature_id am43xx_dispc_features_list[] = { 3998 FEAT_LCDENABLEPOL, 3999 FEAT_LCDENABLESIGNAL, 4000 FEAT_PCKFREEENABLE, 4001 FEAT_FUNCGATED, 4002 FEAT_LINEBUFFERSPLIT, 4003 FEAT_ROWREPEATENABLE, 4004 FEAT_RESIZECONF, 4005 FEAT_CPR, 4006 FEAT_PRELOAD, 4007 FEAT_FIR_COEF_V, 4008 FEAT_ALPHA_FIXED_ZORDER, 4009 FEAT_FIFO_MERGE, 4010 }; 4011 4012 static const enum dispc_feature_id omap4_dispc_features_list[] = { 4013 FEAT_MGR_LCD2, 4014 FEAT_CORE_CLK_DIV, 4015 FEAT_HANDLE_UV_SEPARATE, 4016 FEAT_ATTR2, 4017 FEAT_CPR, 4018 FEAT_PRELOAD, 4019 FEAT_FIR_COEF_V, 4020 FEAT_ALPHA_FREE_ZORDER, 4021 FEAT_FIFO_MERGE, 4022 FEAT_BURST_2D, 4023 }; 4024 4025 static const enum dispc_feature_id omap5_dispc_features_list[] = { 4026 FEAT_MGR_LCD2, 4027 FEAT_MGR_LCD3, 4028 FEAT_CORE_CLK_DIV, 4029 FEAT_HANDLE_UV_SEPARATE, 4030 FEAT_ATTR2, 4031 FEAT_CPR, 4032 FEAT_PRELOAD, 4033 FEAT_FIR_COEF_V, 4034 FEAT_ALPHA_FREE_ZORDER, 4035 FEAT_FIFO_MERGE, 4036 FEAT_BURST_2D, 4037 FEAT_MFLAG, 4038 }; 4039 4040 static const struct dss_reg_field omap2_dispc_reg_fields[] = { 4041 [FEAT_REG_FIRHINC] = { 11, 0 }, 4042 [FEAT_REG_FIRVINC] = { 27, 16 }, 4043 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, 4044 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, 4045 [FEAT_REG_FIFOSIZE] = { 8, 0 }, 4046 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 4047 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 4048 }; 4049 4050 static const struct dss_reg_field omap3_dispc_reg_fields[] = { 4051 [FEAT_REG_FIRHINC] = { 12, 0 }, 4052 [FEAT_REG_FIRVINC] = { 28, 16 }, 4053 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, 4054 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, 4055 [FEAT_REG_FIFOSIZE] = { 10, 0 }, 4056 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 4057 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 4058 }; 4059 4060 static const struct dss_reg_field omap4_dispc_reg_fields[] = { 4061 [FEAT_REG_FIRHINC] = { 12, 0 }, 4062 [FEAT_REG_FIRVINC] = { 28, 16 }, 4063 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, 4064 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, 4065 [FEAT_REG_FIFOSIZE] = { 15, 0 }, 4066 [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, 4067 [FEAT_REG_VERTICALACCU] = { 26, 16 }, 4068 }; 4069 4070 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { 4071 /* OMAP_DSS_GFX */ 4072 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4073 4074 /* OMAP_DSS_VIDEO1 */ 4075 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4076 OMAP_DSS_OVL_CAP_REPLICATION, 4077 4078 /* OMAP_DSS_VIDEO2 */ 4079 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4080 OMAP_DSS_OVL_CAP_REPLICATION, 4081 }; 4082 4083 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = { 4084 /* OMAP_DSS_GFX */ 4085 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | 4086 OMAP_DSS_OVL_CAP_REPLICATION, 4087 4088 /* OMAP_DSS_VIDEO1 */ 4089 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4090 OMAP_DSS_OVL_CAP_REPLICATION, 4091 4092 /* OMAP_DSS_VIDEO2 */ 4093 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4094 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4095 }; 4096 4097 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = { 4098 /* OMAP_DSS_GFX */ 4099 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 4100 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4101 4102 /* OMAP_DSS_VIDEO1 */ 4103 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 4104 OMAP_DSS_OVL_CAP_REPLICATION, 4105 4106 /* OMAP_DSS_VIDEO2 */ 4107 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4108 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | 4109 OMAP_DSS_OVL_CAP_REPLICATION, 4110 }; 4111 4112 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = { 4113 /* OMAP_DSS_GFX */ 4114 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 4115 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | 4116 OMAP_DSS_OVL_CAP_REPLICATION, 4117 4118 /* OMAP_DSS_VIDEO1 */ 4119 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4120 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4121 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4122 4123 /* OMAP_DSS_VIDEO2 */ 4124 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4125 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4126 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4127 4128 /* OMAP_DSS_VIDEO3 */ 4129 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 4130 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 4131 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 4132 }; 4133 4134 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } 4135 4136 static const u32 *omap2_dispc_supported_color_modes[] = { 4137 4138 /* OMAP_DSS_GFX */ 4139 COLOR_ARRAY( 4140 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 4141 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), 4142 4143 /* OMAP_DSS_VIDEO1 */ 4144 COLOR_ARRAY( 4145 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4146 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4147 DRM_FORMAT_UYVY), 4148 4149 /* OMAP_DSS_VIDEO2 */ 4150 COLOR_ARRAY( 4151 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4152 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4153 DRM_FORMAT_UYVY), 4154 }; 4155 4156 static const u32 *omap3_dispc_supported_color_modes[] = { 4157 /* OMAP_DSS_GFX */ 4158 COLOR_ARRAY( 4159 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4160 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4161 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 4162 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 4163 4164 /* OMAP_DSS_VIDEO1 */ 4165 COLOR_ARRAY( 4166 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, 4167 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 4168 DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), 4169 4170 /* OMAP_DSS_VIDEO2 */ 4171 COLOR_ARRAY( 4172 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4173 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4174 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 4175 DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, 4176 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 4177 }; 4178 4179 static const u32 *omap4_dispc_supported_color_modes[] = { 4180 /* OMAP_DSS_GFX */ 4181 COLOR_ARRAY( 4182 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 4183 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 4184 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 4185 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, 4186 DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, 4187 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), 4188 4189 /* OMAP_DSS_VIDEO1 */ 4190 COLOR_ARRAY( 4191 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4192 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4193 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4194 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4195 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4196 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4197 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4198 DRM_FORMAT_RGBX8888), 4199 4200 /* OMAP_DSS_VIDEO2 */ 4201 COLOR_ARRAY( 4202 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4203 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4204 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4205 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4206 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4207 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4208 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4209 DRM_FORMAT_RGBX8888), 4210 4211 /* OMAP_DSS_VIDEO3 */ 4212 COLOR_ARRAY( 4213 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4214 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4215 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4216 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4217 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4218 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4219 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4220 DRM_FORMAT_RGBX8888), 4221 4222 /* OMAP_DSS_WB */ 4223 COLOR_ARRAY( 4224 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4225 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4226 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4227 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4228 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4229 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4230 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4231 DRM_FORMAT_RGBX8888), 4232 }; 4233 4234 static const u32 omap3_dispc_supported_scaler_color_modes[] = { 4235 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_YUYV, 4236 DRM_FORMAT_UYVY, 4237 0, 4238 }; 4239 4240 static const struct dispc_features omap24xx_dispc_feats = { 4241 .sw_start = 5, 4242 .fp_start = 15, 4243 .bp_start = 27, 4244 .sw_max = 64, 4245 .vp_max = 255, 4246 .hp_max = 256, 4247 .mgr_width_start = 10, 4248 .mgr_height_start = 26, 4249 .mgr_width_max = 2048, 4250 .mgr_height_max = 2048, 4251 .ovl_width_max = 2048, 4252 .ovl_height_max = 2048, 4253 .max_lcd_pclk = 66500000, 4254 .max_downscale = 2, 4255 /* 4256 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler 4257 * cannot scale an image width larger than 768. 4258 */ 4259 .max_line_width = 768, 4260 .min_pcd = 2, 4261 .calc_scaling = dispc_ovl_calc_scaling_24xx, 4262 .calc_core_clk = calc_core_clk_24xx, 4263 .num_fifos = 3, 4264 .features = omap2_dispc_features_list, 4265 .num_features = ARRAY_SIZE(omap2_dispc_features_list), 4266 .reg_fields = omap2_dispc_reg_fields, 4267 .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields), 4268 .overlay_caps = omap2_dispc_overlay_caps, 4269 .supported_color_modes = omap2_dispc_supported_color_modes, 4270 .supported_scaler_color_modes = COLOR_ARRAY(DRM_FORMAT_XRGB8888), 4271 .num_mgrs = 2, 4272 .num_ovls = 3, 4273 .buffer_size_unit = 1, 4274 .burst_size_unit = 8, 4275 .no_framedone_tv = true, 4276 .set_max_preload = false, 4277 .last_pixel_inc_missing = true, 4278 }; 4279 4280 static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 4281 .sw_start = 5, 4282 .fp_start = 15, 4283 .bp_start = 27, 4284 .sw_max = 64, 4285 .vp_max = 255, 4286 .hp_max = 256, 4287 .mgr_width_start = 10, 4288 .mgr_height_start = 26, 4289 .mgr_width_max = 2048, 4290 .mgr_height_max = 2048, 4291 .ovl_width_max = 2048, 4292 .ovl_height_max = 2048, 4293 .max_lcd_pclk = 173000000, 4294 .max_tv_pclk = 59000000, 4295 .max_downscale = 4, 4296 .max_line_width = 1024, 4297 .min_pcd = 1, 4298 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4299 .calc_core_clk = calc_core_clk_34xx, 4300 .num_fifos = 3, 4301 .features = omap3_dispc_features_list, 4302 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4303 .reg_fields = omap3_dispc_reg_fields, 4304 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4305 .overlay_caps = omap3430_dispc_overlay_caps, 4306 .supported_color_modes = omap3_dispc_supported_color_modes, 4307 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4308 .num_mgrs = 2, 4309 .num_ovls = 3, 4310 .buffer_size_unit = 1, 4311 .burst_size_unit = 8, 4312 .no_framedone_tv = true, 4313 .set_max_preload = false, 4314 .last_pixel_inc_missing = true, 4315 }; 4316 4317 static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 4318 .sw_start = 7, 4319 .fp_start = 19, 4320 .bp_start = 31, 4321 .sw_max = 256, 4322 .vp_max = 4095, 4323 .hp_max = 4096, 4324 .mgr_width_start = 10, 4325 .mgr_height_start = 26, 4326 .mgr_width_max = 2048, 4327 .mgr_height_max = 2048, 4328 .ovl_width_max = 2048, 4329 .ovl_height_max = 2048, 4330 .max_lcd_pclk = 173000000, 4331 .max_tv_pclk = 59000000, 4332 .max_downscale = 4, 4333 .max_line_width = 1024, 4334 .min_pcd = 1, 4335 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4336 .calc_core_clk = calc_core_clk_34xx, 4337 .num_fifos = 3, 4338 .features = omap3_dispc_features_list, 4339 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4340 .reg_fields = omap3_dispc_reg_fields, 4341 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4342 .overlay_caps = omap3430_dispc_overlay_caps, 4343 .supported_color_modes = omap3_dispc_supported_color_modes, 4344 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4345 .num_mgrs = 2, 4346 .num_ovls = 3, 4347 .buffer_size_unit = 1, 4348 .burst_size_unit = 8, 4349 .no_framedone_tv = true, 4350 .set_max_preload = false, 4351 .last_pixel_inc_missing = true, 4352 }; 4353 4354 static const struct dispc_features omap36xx_dispc_feats = { 4355 .sw_start = 7, 4356 .fp_start = 19, 4357 .bp_start = 31, 4358 .sw_max = 256, 4359 .vp_max = 4095, 4360 .hp_max = 4096, 4361 .mgr_width_start = 10, 4362 .mgr_height_start = 26, 4363 .mgr_width_max = 2048, 4364 .mgr_height_max = 2048, 4365 .ovl_width_max = 2048, 4366 .ovl_height_max = 2048, 4367 .max_lcd_pclk = 173000000, 4368 .max_tv_pclk = 59000000, 4369 .max_downscale = 4, 4370 .max_line_width = 1024, 4371 .min_pcd = 1, 4372 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4373 .calc_core_clk = calc_core_clk_34xx, 4374 .num_fifos = 3, 4375 .features = omap3_dispc_features_list, 4376 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4377 .reg_fields = omap3_dispc_reg_fields, 4378 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4379 .overlay_caps = omap3630_dispc_overlay_caps, 4380 .supported_color_modes = omap3_dispc_supported_color_modes, 4381 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4382 .num_mgrs = 2, 4383 .num_ovls = 3, 4384 .buffer_size_unit = 1, 4385 .burst_size_unit = 8, 4386 .no_framedone_tv = true, 4387 .set_max_preload = false, 4388 .last_pixel_inc_missing = true, 4389 }; 4390 4391 static const struct dispc_features am43xx_dispc_feats = { 4392 .sw_start = 7, 4393 .fp_start = 19, 4394 .bp_start = 31, 4395 .sw_max = 256, 4396 .vp_max = 4095, 4397 .hp_max = 4096, 4398 .mgr_width_start = 10, 4399 .mgr_height_start = 26, 4400 .mgr_width_max = 2048, 4401 .mgr_height_max = 2048, 4402 .ovl_width_max = 2048, 4403 .ovl_height_max = 2048, 4404 .max_lcd_pclk = 173000000, 4405 .max_tv_pclk = 59000000, 4406 .max_downscale = 4, 4407 .max_line_width = 1024, 4408 .min_pcd = 1, 4409 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4410 .calc_core_clk = calc_core_clk_34xx, 4411 .num_fifos = 3, 4412 .features = am43xx_dispc_features_list, 4413 .num_features = ARRAY_SIZE(am43xx_dispc_features_list), 4414 .reg_fields = omap3_dispc_reg_fields, 4415 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4416 .overlay_caps = omap3430_dispc_overlay_caps, 4417 .supported_color_modes = omap3_dispc_supported_color_modes, 4418 .supported_scaler_color_modes = omap3_dispc_supported_scaler_color_modes, 4419 .num_mgrs = 1, 4420 .num_ovls = 3, 4421 .buffer_size_unit = 1, 4422 .burst_size_unit = 8, 4423 .no_framedone_tv = true, 4424 .set_max_preload = false, 4425 .last_pixel_inc_missing = true, 4426 }; 4427 4428 static const struct dispc_features omap44xx_dispc_feats = { 4429 .sw_start = 7, 4430 .fp_start = 19, 4431 .bp_start = 31, 4432 .sw_max = 256, 4433 .vp_max = 4095, 4434 .hp_max = 4096, 4435 .mgr_width_start = 10, 4436 .mgr_height_start = 26, 4437 .mgr_width_max = 2048, 4438 .mgr_height_max = 2048, 4439 .ovl_width_max = 2048, 4440 .ovl_height_max = 2048, 4441 .max_lcd_pclk = 170000000, 4442 .max_tv_pclk = 185625000, 4443 .max_downscale = 4, 4444 .max_line_width = 2048, 4445 .min_pcd = 1, 4446 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4447 .calc_core_clk = calc_core_clk_44xx, 4448 .num_fifos = 5, 4449 .features = omap4_dispc_features_list, 4450 .num_features = ARRAY_SIZE(omap4_dispc_features_list), 4451 .reg_fields = omap4_dispc_reg_fields, 4452 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4453 .overlay_caps = omap4_dispc_overlay_caps, 4454 .supported_color_modes = omap4_dispc_supported_color_modes, 4455 .num_mgrs = 3, 4456 .num_ovls = 4, 4457 .buffer_size_unit = 16, 4458 .burst_size_unit = 16, 4459 .gfx_fifo_workaround = true, 4460 .set_max_preload = true, 4461 .supports_sync_align = true, 4462 .has_writeback = true, 4463 .supports_double_pixel = true, 4464 .reverse_ilace_field_order = true, 4465 .has_gamma_table = true, 4466 .has_gamma_i734_bug = true, 4467 }; 4468 4469 static const struct dispc_features omap54xx_dispc_feats = { 4470 .sw_start = 7, 4471 .fp_start = 19, 4472 .bp_start = 31, 4473 .sw_max = 256, 4474 .vp_max = 4095, 4475 .hp_max = 4096, 4476 .mgr_width_start = 11, 4477 .mgr_height_start = 27, 4478 .mgr_width_max = 4096, 4479 .mgr_height_max = 4096, 4480 .ovl_width_max = 2048, 4481 .ovl_height_max = 4096, 4482 .max_lcd_pclk = 170000000, 4483 .max_tv_pclk = 192000000, 4484 .max_downscale = 4, 4485 .max_line_width = 2048, 4486 .min_pcd = 1, 4487 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4488 .calc_core_clk = calc_core_clk_44xx, 4489 .num_fifos = 5, 4490 .features = omap5_dispc_features_list, 4491 .num_features = ARRAY_SIZE(omap5_dispc_features_list), 4492 .reg_fields = omap4_dispc_reg_fields, 4493 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4494 .overlay_caps = omap4_dispc_overlay_caps, 4495 .supported_color_modes = omap4_dispc_supported_color_modes, 4496 .num_mgrs = 4, 4497 .num_ovls = 4, 4498 .buffer_size_unit = 16, 4499 .burst_size_unit = 16, 4500 .gfx_fifo_workaround = true, 4501 .mstandby_workaround = true, 4502 .set_max_preload = true, 4503 .supports_sync_align = true, 4504 .has_writeback = true, 4505 .supports_double_pixel = true, 4506 .reverse_ilace_field_order = true, 4507 .has_gamma_table = true, 4508 .has_gamma_i734_bug = true, 4509 }; 4510 4511 static irqreturn_t dispc_irq_handler(int irq, void *arg) 4512 { 4513 struct dispc_device *dispc = arg; 4514 4515 if (!dispc->is_enabled) 4516 return IRQ_NONE; 4517 4518 return dispc->user_handler(irq, dispc->user_data); 4519 } 4520 4521 int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, 4522 void *dev_id) 4523 { 4524 int r; 4525 4526 if (dispc->user_handler != NULL) 4527 return -EBUSY; 4528 4529 dispc->user_handler = handler; 4530 dispc->user_data = dev_id; 4531 4532 /* ensure the dispc_irq_handler sees the values above */ 4533 smp_wmb(); 4534 4535 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, 4536 IRQF_SHARED, "OMAP DISPC", dispc); 4537 if (r) { 4538 dispc->user_handler = NULL; 4539 dispc->user_data = NULL; 4540 } 4541 4542 return r; 4543 } 4544 4545 void dispc_free_irq(struct dispc_device *dispc, void *dev_id) 4546 { 4547 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); 4548 4549 dispc->user_handler = NULL; 4550 dispc->user_data = NULL; 4551 } 4552 4553 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) 4554 { 4555 u32 limit = 0; 4556 4557 /* Optional maximum memory bandwidth */ 4558 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", 4559 &limit); 4560 4561 return limit; 4562 } 4563 4564 /* 4565 * Workaround for errata i734 in DSS dispc 4566 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled 4567 * 4568 * For gamma tables to work on LCD1 the GFX plane has to be used at 4569 * least once after DSS HW has come out of reset. The workaround 4570 * sets up a minimal LCD setup with GFX plane and waits for one 4571 * vertical sync irq before disabling the setup and continuing with 4572 * the context restore. The physical outputs are gated during the 4573 * operation. This workaround requires that gamma table's LOADMODE 4574 * is set to 0x2 in DISPC_CONTROL1 register. 4575 * 4576 * For details see: 4577 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata 4578 * Literature Number: SWPZ037E 4579 * Or some other relevant errata document for the DSS IP version. 4580 */ 4581 4582 static const struct dispc_errata_i734_data { 4583 struct videomode vm; 4584 struct omap_overlay_info ovli; 4585 struct omap_overlay_manager_info mgri; 4586 struct dss_lcd_mgr_config lcd_conf; 4587 } i734 = { 4588 .vm = { 4589 .hactive = 8, .vactive = 1, 4590 .pixelclock = 16000000, 4591 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 4592 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, 4593 4594 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4595 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE | 4596 DISPLAY_FLAGS_PIXDATA_POSEDGE, 4597 }, 4598 .ovli = { 4599 .screen_width = 1, 4600 .width = 1, .height = 1, 4601 .fourcc = DRM_FORMAT_XRGB8888, 4602 .rotation = DRM_MODE_ROTATE_0, 4603 .rotation_type = OMAP_DSS_ROT_NONE, 4604 .pos_x = 0, .pos_y = 0, 4605 .out_width = 0, .out_height = 0, 4606 .global_alpha = 0xff, 4607 .pre_mult_alpha = 0, 4608 .zorder = 0, 4609 }, 4610 .mgri = { 4611 .default_color = 0, 4612 .trans_enabled = false, 4613 .partial_alpha_enabled = false, 4614 .cpr_enable = false, 4615 }, 4616 .lcd_conf = { 4617 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS, 4618 .stallmode = false, 4619 .fifohandcheck = false, 4620 .clock_info = { 4621 .lck_div = 1, 4622 .pck_div = 2, 4623 }, 4624 .video_port_width = 24, 4625 .lcden_sig_polarity = 0, 4626 }, 4627 }; 4628 4629 static struct i734_buf { 4630 size_t size; 4631 dma_addr_t paddr; 4632 void *vaddr; 4633 } i734_buf; 4634 4635 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) 4636 { 4637 if (!dispc->feat->has_gamma_i734_bug) 4638 return 0; 4639 4640 i734_buf.size = i734.ovli.width * i734.ovli.height * 4641 color_mode_to_bpp(i734.ovli.fourcc) / 8; 4642 4643 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, 4644 &i734_buf.paddr, GFP_KERNEL); 4645 if (!i734_buf.vaddr) { 4646 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", 4647 __func__); 4648 return -ENOMEM; 4649 } 4650 4651 return 0; 4652 } 4653 4654 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) 4655 { 4656 if (!dispc->feat->has_gamma_i734_bug) 4657 return; 4658 4659 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, 4660 i734_buf.paddr); 4661 } 4662 4663 static void dispc_errata_i734_wa(struct dispc_device *dispc) 4664 { 4665 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, 4666 OMAP_DSS_CHANNEL_LCD); 4667 struct omap_overlay_info ovli; 4668 struct dss_lcd_mgr_config lcd_conf; 4669 u32 gatestate; 4670 unsigned int count; 4671 4672 if (!dispc->feat->has_gamma_i734_bug) 4673 return; 4674 4675 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); 4676 4677 ovli = i734.ovli; 4678 ovli.paddr = i734_buf.paddr; 4679 lcd_conf = i734.lcd_conf; 4680 4681 /* Gate all LCD1 outputs */ 4682 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); 4683 4684 /* Setup and enable GFX plane */ 4685 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, 4686 OMAP_DSS_CHANNEL_LCD); 4687 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); 4688 4689 /* Set up and enable display manager for LCD1 */ 4690 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); 4691 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), 4692 &lcd_conf.clock_info); 4693 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4694 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); 4695 4696 dispc_clear_irqstatus(dispc, framedone_irq); 4697 4698 /* Enable and shut the channel to produce just one frame */ 4699 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); 4700 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); 4701 4702 /* Busy wait for framedone. We can't fiddle with irq handlers 4703 * in PM resume. Typically the loop runs less than 5 times and 4704 * waits less than a micro second. 4705 */ 4706 count = 0; 4707 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { 4708 if (count++ > 10000) { 4709 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", 4710 __func__); 4711 break; 4712 } 4713 } 4714 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); 4715 4716 /* Clear all irq bits before continuing */ 4717 dispc_clear_irqstatus(dispc, 0xffffffff); 4718 4719 /* Restore the original state to LCD1 output gates */ 4720 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); 4721 } 4722 4723 /* DISPC HW IP initialisation */ 4724 static const struct of_device_id dispc_of_match[] = { 4725 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats }, 4726 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats }, 4727 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats }, 4728 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats }, 4729 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats }, 4730 {}, 4731 }; 4732 4733 static const struct soc_device_attribute dispc_soc_devices[] = { 4734 { .machine = "OMAP3[45]*", 4735 .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, 4736 { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, 4737 { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, 4738 { .machine = "AM43*", .data = &am43xx_dispc_feats }, 4739 { /* sentinel */ } 4740 }; 4741 4742 static int dispc_bind(struct device *dev, struct device *master, void *data) 4743 { 4744 struct platform_device *pdev = to_platform_device(dev); 4745 const struct soc_device_attribute *soc; 4746 struct dss_device *dss = dss_get_device(master); 4747 struct dispc_device *dispc; 4748 u32 rev; 4749 int r = 0; 4750 struct device_node *np = pdev->dev.of_node; 4751 4752 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); 4753 if (!dispc) 4754 return -ENOMEM; 4755 4756 dispc->pdev = pdev; 4757 platform_set_drvdata(pdev, dispc); 4758 dispc->dss = dss; 4759 4760 /* 4761 * The OMAP3-based models can't be told apart using the compatible 4762 * string, use SoC device matching. 4763 */ 4764 soc = soc_device_match(dispc_soc_devices); 4765 if (soc) 4766 dispc->feat = soc->data; 4767 else 4768 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; 4769 4770 r = dispc_errata_i734_wa_init(dispc); 4771 if (r) 4772 goto err_free; 4773 4774 dispc->base = devm_platform_ioremap_resource(pdev, 0); 4775 if (IS_ERR(dispc->base)) { 4776 r = PTR_ERR(dispc->base); 4777 goto err_free; 4778 } 4779 4780 dispc->irq = platform_get_irq(dispc->pdev, 0); 4781 if (dispc->irq < 0) { 4782 DSSERR("platform_get_irq failed\n"); 4783 r = -ENODEV; 4784 goto err_free; 4785 } 4786 4787 if (np && of_property_read_bool(np, "syscon-pol")) { 4788 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 4789 if (IS_ERR(dispc->syscon_pol)) { 4790 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 4791 r = PTR_ERR(dispc->syscon_pol); 4792 goto err_free; 4793 } 4794 4795 if (of_property_read_u32_index(np, "syscon-pol", 1, 4796 &dispc->syscon_pol_offset)) { 4797 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 4798 r = -EINVAL; 4799 goto err_free; 4800 } 4801 } 4802 4803 r = dispc_init_gamma_tables(dispc); 4804 if (r) 4805 goto err_free; 4806 4807 pm_runtime_enable(&pdev->dev); 4808 4809 r = dispc_runtime_get(dispc); 4810 if (r) 4811 goto err_runtime_get; 4812 4813 _omap_dispc_initial_config(dispc); 4814 4815 rev = dispc_read_reg(dispc, DISPC_REVISION); 4816 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 4817 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4818 4819 dispc_runtime_put(dispc); 4820 4821 dss->dispc = dispc; 4822 4823 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, 4824 dispc); 4825 4826 return 0; 4827 4828 err_runtime_get: 4829 pm_runtime_disable(&pdev->dev); 4830 err_free: 4831 kfree(dispc); 4832 return r; 4833 } 4834 4835 static void dispc_unbind(struct device *dev, struct device *master, void *data) 4836 { 4837 struct dispc_device *dispc = dev_get_drvdata(dev); 4838 struct dss_device *dss = dispc->dss; 4839 4840 dss_debugfs_remove_file(dispc->debugfs); 4841 4842 dss->dispc = NULL; 4843 4844 pm_runtime_disable(dev); 4845 4846 dispc_errata_i734_wa_fini(dispc); 4847 4848 kfree(dispc); 4849 } 4850 4851 static const struct component_ops dispc_component_ops = { 4852 .bind = dispc_bind, 4853 .unbind = dispc_unbind, 4854 }; 4855 4856 static int dispc_probe(struct platform_device *pdev) 4857 { 4858 return component_add(&pdev->dev, &dispc_component_ops); 4859 } 4860 4861 static void dispc_remove(struct platform_device *pdev) 4862 { 4863 component_del(&pdev->dev, &dispc_component_ops); 4864 } 4865 4866 static __maybe_unused int dispc_runtime_suspend(struct device *dev) 4867 { 4868 struct dispc_device *dispc = dev_get_drvdata(dev); 4869 4870 dispc->is_enabled = false; 4871 /* ensure the dispc_irq_handler sees the is_enabled value */ 4872 smp_wmb(); 4873 /* wait for current handler to finish before turning the DISPC off */ 4874 synchronize_irq(dispc->irq); 4875 4876 dispc_save_context(dispc); 4877 4878 return 0; 4879 } 4880 4881 static __maybe_unused int dispc_runtime_resume(struct device *dev) 4882 { 4883 struct dispc_device *dispc = dev_get_drvdata(dev); 4884 4885 /* 4886 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4887 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4888 * _omap_dispc_initial_config(). We can thus use it to detect if 4889 * we have lost register context. 4890 */ 4891 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4892 _omap_dispc_initial_config(dispc); 4893 4894 dispc_errata_i734_wa(dispc); 4895 4896 dispc_restore_context(dispc); 4897 4898 dispc_restore_gamma_tables(dispc); 4899 } 4900 4901 dispc->is_enabled = true; 4902 /* ensure the dispc_irq_handler sees the is_enabled value */ 4903 smp_wmb(); 4904 4905 return 0; 4906 } 4907 4908 static const struct dev_pm_ops dispc_pm_ops = { 4909 SET_RUNTIME_PM_OPS(dispc_runtime_suspend, dispc_runtime_resume, NULL) 4910 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 4911 }; 4912 4913 struct platform_driver omap_dispchw_driver = { 4914 .probe = dispc_probe, 4915 .remove_new = dispc_remove, 4916 .driver = { 4917 .name = "omapdss_dispc", 4918 .pm = &dispc_pm_ops, 4919 .of_match_table = dispc_of_match, 4920 .suppress_bind_attrs = true, 4921 }, 4922 }; 4923