1 /* 2 * linux/drivers/video/omap2/dss/dispc.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #define DSS_SUBSYS_NAME "DISPC" 24 25 #include <linux/kernel.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/vmalloc.h> 28 #include <linux/export.h> 29 #include <linux/clk.h> 30 #include <linux/io.h> 31 #include <linux/jiffies.h> 32 #include <linux/seq_file.h> 33 #include <linux/delay.h> 34 #include <linux/workqueue.h> 35 #include <linux/hardirq.h> 36 #include <linux/platform_device.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/sizes.h> 39 #include <linux/mfd/syscon.h> 40 #include <linux/regmap.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/component.h> 44 #include <linux/sys_soc.h> 45 #include <drm/drm_fourcc.h> 46 #include <drm/drm_blend.h> 47 48 #include "omapdss.h" 49 #include "dss.h" 50 #include "dispc.h" 51 52 /* DISPC */ 53 #define DISPC_SZ_REGS SZ_4K 54 55 enum omap_burst_size { 56 BURST_SIZE_X2 = 0, 57 BURST_SIZE_X4 = 1, 58 BURST_SIZE_X8 = 2, 59 }; 60 61 #define REG_GET(idx, start, end) \ 62 FLD_GET(dispc_read_reg(idx), start, end) 63 64 #define REG_FLD_MOD(idx, val, start, end) \ 65 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 66 67 /* DISPC has feature id */ 68 enum dispc_feature_id { 69 FEAT_LCDENABLEPOL, 70 FEAT_LCDENABLESIGNAL, 71 FEAT_PCKFREEENABLE, 72 FEAT_FUNCGATED, 73 FEAT_MGR_LCD2, 74 FEAT_MGR_LCD3, 75 FEAT_LINEBUFFERSPLIT, 76 FEAT_ROWREPEATENABLE, 77 FEAT_RESIZECONF, 78 /* Independent core clk divider */ 79 FEAT_CORE_CLK_DIV, 80 FEAT_HANDLE_UV_SEPARATE, 81 FEAT_ATTR2, 82 FEAT_CPR, 83 FEAT_PRELOAD, 84 FEAT_FIR_COEF_V, 85 FEAT_ALPHA_FIXED_ZORDER, 86 FEAT_ALPHA_FREE_ZORDER, 87 FEAT_FIFO_MERGE, 88 /* An unknown HW bug causing the normal FIFO thresholds not to work */ 89 FEAT_OMAP3_DSI_FIFO_BUG, 90 FEAT_BURST_2D, 91 FEAT_MFLAG, 92 }; 93 94 struct dispc_features { 95 u8 sw_start; 96 u8 fp_start; 97 u8 bp_start; 98 u16 sw_max; 99 u16 vp_max; 100 u16 hp_max; 101 u8 mgr_width_start; 102 u8 mgr_height_start; 103 u16 mgr_width_max; 104 u16 mgr_height_max; 105 unsigned long max_lcd_pclk; 106 unsigned long max_tv_pclk; 107 unsigned int max_downscale; 108 unsigned int max_line_width; 109 unsigned int min_pcd; 110 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 111 const struct videomode *vm, 112 u16 width, u16 height, u16 out_width, u16 out_height, 113 u32 fourcc, bool *five_taps, 114 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 115 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 116 unsigned long (*calc_core_clk) (unsigned long pclk, 117 u16 width, u16 height, u16 out_width, u16 out_height, 118 bool mem_to_mem); 119 u8 num_fifos; 120 const enum dispc_feature_id *features; 121 unsigned int num_features; 122 const struct dss_reg_field *reg_fields; 123 const unsigned int num_reg_fields; 124 const enum omap_overlay_caps *overlay_caps; 125 const u32 **supported_color_modes; 126 unsigned int num_mgrs; 127 unsigned int num_ovls; 128 unsigned int buffer_size_unit; 129 unsigned int burst_size_unit; 130 131 /* swap GFX & WB fifos */ 132 bool gfx_fifo_workaround:1; 133 134 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 135 bool no_framedone_tv:1; 136 137 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 138 bool mstandby_workaround:1; 139 140 bool set_max_preload:1; 141 142 /* PIXEL_INC is not added to the last pixel of a line */ 143 bool last_pixel_inc_missing:1; 144 145 /* POL_FREQ has ALIGN bit */ 146 bool supports_sync_align:1; 147 148 bool has_writeback:1; 149 150 bool supports_double_pixel:1; 151 152 /* 153 * Field order for VENC is different than HDMI. We should handle this in 154 * some intelligent manner, but as the SoCs have either HDMI or VENC, 155 * never both, we can just use this flag for now. 156 */ 157 bool reverse_ilace_field_order:1; 158 159 bool has_gamma_table:1; 160 161 bool has_gamma_i734_bug:1; 162 }; 163 164 #define DISPC_MAX_NR_FIFOS 5 165 #define DISPC_MAX_CHANNEL_GAMMA 4 166 167 static struct { 168 struct platform_device *pdev; 169 void __iomem *base; 170 171 int irq; 172 irq_handler_t user_handler; 173 void *user_data; 174 175 unsigned long core_clk_rate; 176 unsigned long tv_pclk_rate; 177 178 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 179 /* maps which plane is using a fifo. fifo-id -> plane-id */ 180 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 181 182 bool ctx_valid; 183 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 184 185 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA]; 186 187 const struct dispc_features *feat; 188 189 bool is_enabled; 190 191 struct regmap *syscon_pol; 192 u32 syscon_pol_offset; 193 194 /* DISPC_CONTROL & DISPC_CONFIG lock*/ 195 spinlock_t control_lock; 196 } dispc; 197 198 enum omap_color_component { 199 /* used for all color formats for OMAP3 and earlier 200 * and for RGB and Y color component on OMAP4 201 */ 202 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 203 /* used for UV component for 204 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12 205 * color formats on OMAP4 206 */ 207 DISPC_COLOR_COMPONENT_UV = 1 << 1, 208 }; 209 210 enum mgr_reg_fields { 211 DISPC_MGR_FLD_ENABLE, 212 DISPC_MGR_FLD_STNTFT, 213 DISPC_MGR_FLD_GO, 214 DISPC_MGR_FLD_TFTDATALINES, 215 DISPC_MGR_FLD_STALLMODE, 216 DISPC_MGR_FLD_TCKENABLE, 217 DISPC_MGR_FLD_TCKSELECTION, 218 DISPC_MGR_FLD_CPR, 219 DISPC_MGR_FLD_FIFOHANDCHECK, 220 /* used to maintain a count of the above fields */ 221 DISPC_MGR_FLD_NUM, 222 }; 223 224 /* DISPC register field id */ 225 enum dispc_feat_reg_field { 226 FEAT_REG_FIRHINC, 227 FEAT_REG_FIRVINC, 228 FEAT_REG_FIFOHIGHTHRESHOLD, 229 FEAT_REG_FIFOLOWTHRESHOLD, 230 FEAT_REG_FIFOSIZE, 231 FEAT_REG_HORIZONTALACCU, 232 FEAT_REG_VERTICALACCU, 233 }; 234 235 struct dispc_reg_field { 236 u16 reg; 237 u8 high; 238 u8 low; 239 }; 240 241 struct dispc_gamma_desc { 242 u32 len; 243 u32 bits; 244 u16 reg; 245 bool has_index; 246 }; 247 248 static const struct { 249 const char *name; 250 u32 vsync_irq; 251 u32 framedone_irq; 252 u32 sync_lost_irq; 253 struct dispc_gamma_desc gamma; 254 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 255 } mgr_desc[] = { 256 [OMAP_DSS_CHANNEL_LCD] = { 257 .name = "LCD", 258 .vsync_irq = DISPC_IRQ_VSYNC, 259 .framedone_irq = DISPC_IRQ_FRAMEDONE, 260 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 261 .gamma = { 262 .len = 256, 263 .bits = 8, 264 .reg = DISPC_GAMMA_TABLE0, 265 .has_index = true, 266 }, 267 .reg_desc = { 268 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 269 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 270 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 271 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 272 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 273 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 274 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 275 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 276 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 277 }, 278 }, 279 [OMAP_DSS_CHANNEL_DIGIT] = { 280 .name = "DIGIT", 281 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 282 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 283 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 284 .gamma = { 285 .len = 1024, 286 .bits = 10, 287 .reg = DISPC_GAMMA_TABLE2, 288 .has_index = false, 289 }, 290 .reg_desc = { 291 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 292 [DISPC_MGR_FLD_STNTFT] = { }, 293 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 294 [DISPC_MGR_FLD_TFTDATALINES] = { }, 295 [DISPC_MGR_FLD_STALLMODE] = { }, 296 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 297 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 298 [DISPC_MGR_FLD_CPR] = { }, 299 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 300 }, 301 }, 302 [OMAP_DSS_CHANNEL_LCD2] = { 303 .name = "LCD2", 304 .vsync_irq = DISPC_IRQ_VSYNC2, 305 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 306 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 307 .gamma = { 308 .len = 256, 309 .bits = 8, 310 .reg = DISPC_GAMMA_TABLE1, 311 .has_index = true, 312 }, 313 .reg_desc = { 314 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 315 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 316 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 317 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 318 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 319 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 320 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 321 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 322 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 323 }, 324 }, 325 [OMAP_DSS_CHANNEL_LCD3] = { 326 .name = "LCD3", 327 .vsync_irq = DISPC_IRQ_VSYNC3, 328 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 329 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 330 .gamma = { 331 .len = 256, 332 .bits = 8, 333 .reg = DISPC_GAMMA_TABLE3, 334 .has_index = true, 335 }, 336 .reg_desc = { 337 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 338 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 339 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 340 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 341 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 342 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 343 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 344 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 345 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 346 }, 347 }, 348 }; 349 350 struct color_conv_coef { 351 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; 352 int full_range; 353 }; 354 355 static unsigned long dispc_fclk_rate(void); 356 static unsigned long dispc_core_clk_rate(void); 357 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 358 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 359 360 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane); 361 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane); 362 363 static void dispc_clear_irqstatus(u32 mask); 364 static bool dispc_mgr_is_enabled(enum omap_channel channel); 365 static void dispc_clear_irqstatus(u32 mask); 366 367 static inline void dispc_write_reg(const u16 idx, u32 val) 368 { 369 __raw_writel(val, dispc.base + idx); 370 } 371 372 static inline u32 dispc_read_reg(const u16 idx) 373 { 374 return __raw_readl(dispc.base + idx); 375 } 376 377 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) 378 { 379 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 380 return REG_GET(rfld.reg, rfld.high, rfld.low); 381 } 382 383 static void mgr_fld_write(enum omap_channel channel, 384 enum mgr_reg_fields regfld, int val) { 385 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 386 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; 387 unsigned long flags; 388 389 if (need_lock) 390 spin_lock_irqsave(&dispc.control_lock, flags); 391 392 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 393 394 if (need_lock) 395 spin_unlock_irqrestore(&dispc.control_lock, flags); 396 } 397 398 static int dispc_get_num_ovls(void) 399 { 400 return dispc.feat->num_ovls; 401 } 402 403 static int dispc_get_num_mgrs(void) 404 { 405 return dispc.feat->num_mgrs; 406 } 407 408 static void dispc_get_reg_field(enum dispc_feat_reg_field id, 409 u8 *start, u8 *end) 410 { 411 if (id >= dispc.feat->num_reg_fields) 412 BUG(); 413 414 *start = dispc.feat->reg_fields[id].start; 415 *end = dispc.feat->reg_fields[id].end; 416 } 417 418 static bool dispc_has_feature(enum dispc_feature_id id) 419 { 420 unsigned int i; 421 422 for (i = 0; i < dispc.feat->num_features; i++) { 423 if (dispc.feat->features[i] == id) 424 return true; 425 } 426 427 return false; 428 } 429 430 #define SR(reg) \ 431 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 432 #define RR(reg) \ 433 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) 434 435 static void dispc_save_context(void) 436 { 437 int i, j; 438 439 DSSDBG("dispc_save_context\n"); 440 441 SR(IRQENABLE); 442 SR(CONTROL); 443 SR(CONFIG); 444 SR(LINE_NUMBER); 445 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 446 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 447 SR(GLOBAL_ALPHA); 448 if (dispc_has_feature(FEAT_MGR_LCD2)) { 449 SR(CONTROL2); 450 SR(CONFIG2); 451 } 452 if (dispc_has_feature(FEAT_MGR_LCD3)) { 453 SR(CONTROL3); 454 SR(CONFIG3); 455 } 456 457 for (i = 0; i < dispc_get_num_mgrs(); i++) { 458 SR(DEFAULT_COLOR(i)); 459 SR(TRANS_COLOR(i)); 460 SR(SIZE_MGR(i)); 461 if (i == OMAP_DSS_CHANNEL_DIGIT) 462 continue; 463 SR(TIMING_H(i)); 464 SR(TIMING_V(i)); 465 SR(POL_FREQ(i)); 466 SR(DIVISORo(i)); 467 468 SR(DATA_CYCLE1(i)); 469 SR(DATA_CYCLE2(i)); 470 SR(DATA_CYCLE3(i)); 471 472 if (dispc_has_feature(FEAT_CPR)) { 473 SR(CPR_COEF_R(i)); 474 SR(CPR_COEF_G(i)); 475 SR(CPR_COEF_B(i)); 476 } 477 } 478 479 for (i = 0; i < dispc_get_num_ovls(); i++) { 480 SR(OVL_BA0(i)); 481 SR(OVL_BA1(i)); 482 SR(OVL_POSITION(i)); 483 SR(OVL_SIZE(i)); 484 SR(OVL_ATTRIBUTES(i)); 485 SR(OVL_FIFO_THRESHOLD(i)); 486 SR(OVL_ROW_INC(i)); 487 SR(OVL_PIXEL_INC(i)); 488 if (dispc_has_feature(FEAT_PRELOAD)) 489 SR(OVL_PRELOAD(i)); 490 if (i == OMAP_DSS_GFX) { 491 SR(OVL_WINDOW_SKIP(i)); 492 SR(OVL_TABLE_BA(i)); 493 continue; 494 } 495 SR(OVL_FIR(i)); 496 SR(OVL_PICTURE_SIZE(i)); 497 SR(OVL_ACCU0(i)); 498 SR(OVL_ACCU1(i)); 499 500 for (j = 0; j < 8; j++) 501 SR(OVL_FIR_COEF_H(i, j)); 502 503 for (j = 0; j < 8; j++) 504 SR(OVL_FIR_COEF_HV(i, j)); 505 506 for (j = 0; j < 5; j++) 507 SR(OVL_CONV_COEF(i, j)); 508 509 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 510 for (j = 0; j < 8; j++) 511 SR(OVL_FIR_COEF_V(i, j)); 512 } 513 514 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 515 SR(OVL_BA0_UV(i)); 516 SR(OVL_BA1_UV(i)); 517 SR(OVL_FIR2(i)); 518 SR(OVL_ACCU2_0(i)); 519 SR(OVL_ACCU2_1(i)); 520 521 for (j = 0; j < 8; j++) 522 SR(OVL_FIR_COEF_H2(i, j)); 523 524 for (j = 0; j < 8; j++) 525 SR(OVL_FIR_COEF_HV2(i, j)); 526 527 for (j = 0; j < 8; j++) 528 SR(OVL_FIR_COEF_V2(i, j)); 529 } 530 if (dispc_has_feature(FEAT_ATTR2)) 531 SR(OVL_ATTRIBUTES2(i)); 532 } 533 534 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 535 SR(DIVISOR); 536 537 dispc.ctx_valid = true; 538 539 DSSDBG("context saved\n"); 540 } 541 542 static void dispc_restore_context(void) 543 { 544 int i, j; 545 546 DSSDBG("dispc_restore_context\n"); 547 548 if (!dispc.ctx_valid) 549 return; 550 551 /*RR(IRQENABLE);*/ 552 /*RR(CONTROL);*/ 553 RR(CONFIG); 554 RR(LINE_NUMBER); 555 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 556 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 557 RR(GLOBAL_ALPHA); 558 if (dispc_has_feature(FEAT_MGR_LCD2)) 559 RR(CONFIG2); 560 if (dispc_has_feature(FEAT_MGR_LCD3)) 561 RR(CONFIG3); 562 563 for (i = 0; i < dispc_get_num_mgrs(); i++) { 564 RR(DEFAULT_COLOR(i)); 565 RR(TRANS_COLOR(i)); 566 RR(SIZE_MGR(i)); 567 if (i == OMAP_DSS_CHANNEL_DIGIT) 568 continue; 569 RR(TIMING_H(i)); 570 RR(TIMING_V(i)); 571 RR(POL_FREQ(i)); 572 RR(DIVISORo(i)); 573 574 RR(DATA_CYCLE1(i)); 575 RR(DATA_CYCLE2(i)); 576 RR(DATA_CYCLE3(i)); 577 578 if (dispc_has_feature(FEAT_CPR)) { 579 RR(CPR_COEF_R(i)); 580 RR(CPR_COEF_G(i)); 581 RR(CPR_COEF_B(i)); 582 } 583 } 584 585 for (i = 0; i < dispc_get_num_ovls(); i++) { 586 RR(OVL_BA0(i)); 587 RR(OVL_BA1(i)); 588 RR(OVL_POSITION(i)); 589 RR(OVL_SIZE(i)); 590 RR(OVL_ATTRIBUTES(i)); 591 RR(OVL_FIFO_THRESHOLD(i)); 592 RR(OVL_ROW_INC(i)); 593 RR(OVL_PIXEL_INC(i)); 594 if (dispc_has_feature(FEAT_PRELOAD)) 595 RR(OVL_PRELOAD(i)); 596 if (i == OMAP_DSS_GFX) { 597 RR(OVL_WINDOW_SKIP(i)); 598 RR(OVL_TABLE_BA(i)); 599 continue; 600 } 601 RR(OVL_FIR(i)); 602 RR(OVL_PICTURE_SIZE(i)); 603 RR(OVL_ACCU0(i)); 604 RR(OVL_ACCU1(i)); 605 606 for (j = 0; j < 8; j++) 607 RR(OVL_FIR_COEF_H(i, j)); 608 609 for (j = 0; j < 8; j++) 610 RR(OVL_FIR_COEF_HV(i, j)); 611 612 for (j = 0; j < 5; j++) 613 RR(OVL_CONV_COEF(i, j)); 614 615 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 616 for (j = 0; j < 8; j++) 617 RR(OVL_FIR_COEF_V(i, j)); 618 } 619 620 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 621 RR(OVL_BA0_UV(i)); 622 RR(OVL_BA1_UV(i)); 623 RR(OVL_FIR2(i)); 624 RR(OVL_ACCU2_0(i)); 625 RR(OVL_ACCU2_1(i)); 626 627 for (j = 0; j < 8; j++) 628 RR(OVL_FIR_COEF_H2(i, j)); 629 630 for (j = 0; j < 8; j++) 631 RR(OVL_FIR_COEF_HV2(i, j)); 632 633 for (j = 0; j < 8; j++) 634 RR(OVL_FIR_COEF_V2(i, j)); 635 } 636 if (dispc_has_feature(FEAT_ATTR2)) 637 RR(OVL_ATTRIBUTES2(i)); 638 } 639 640 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 641 RR(DIVISOR); 642 643 /* enable last, because LCD & DIGIT enable are here */ 644 RR(CONTROL); 645 if (dispc_has_feature(FEAT_MGR_LCD2)) 646 RR(CONTROL2); 647 if (dispc_has_feature(FEAT_MGR_LCD3)) 648 RR(CONTROL3); 649 /* clear spurious SYNC_LOST_DIGIT interrupts */ 650 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); 651 652 /* 653 * enable last so IRQs won't trigger before 654 * the context is fully restored 655 */ 656 RR(IRQENABLE); 657 658 DSSDBG("context restored\n"); 659 } 660 661 #undef SR 662 #undef RR 663 664 int dispc_runtime_get(void) 665 { 666 int r; 667 668 DSSDBG("dispc_runtime_get\n"); 669 670 r = pm_runtime_get_sync(&dispc.pdev->dev); 671 WARN_ON(r < 0); 672 return r < 0 ? r : 0; 673 } 674 675 void dispc_runtime_put(void) 676 { 677 int r; 678 679 DSSDBG("dispc_runtime_put\n"); 680 681 r = pm_runtime_put_sync(&dispc.pdev->dev); 682 WARN_ON(r < 0 && r != -ENOSYS); 683 } 684 685 static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 686 { 687 return mgr_desc[channel].vsync_irq; 688 } 689 690 static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 691 { 692 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) 693 return 0; 694 695 return mgr_desc[channel].framedone_irq; 696 } 697 698 static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 699 { 700 return mgr_desc[channel].sync_lost_irq; 701 } 702 703 u32 dispc_wb_get_framedone_irq(void) 704 { 705 return DISPC_IRQ_FRAMEDONEWB; 706 } 707 708 static void dispc_mgr_enable(enum omap_channel channel, bool enable) 709 { 710 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); 711 /* flush posted write */ 712 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 713 } 714 715 static bool dispc_mgr_is_enabled(enum omap_channel channel) 716 { 717 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 718 } 719 720 static bool dispc_mgr_go_busy(enum omap_channel channel) 721 { 722 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 723 } 724 725 static void dispc_mgr_go(enum omap_channel channel) 726 { 727 WARN_ON(!dispc_mgr_is_enabled(channel)); 728 WARN_ON(dispc_mgr_go_busy(channel)); 729 730 DSSDBG("GO %s\n", mgr_desc[channel].name); 731 732 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 733 } 734 735 bool dispc_wb_go_busy(void) 736 { 737 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; 738 } 739 740 void dispc_wb_go(void) 741 { 742 enum omap_plane_id plane = OMAP_DSS_WB; 743 bool enable, go; 744 745 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 746 747 if (!enable) 748 return; 749 750 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; 751 if (go) { 752 DSSERR("GO bit not down for WB\n"); 753 return; 754 } 755 756 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); 757 } 758 759 static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg, 760 u32 value) 761 { 762 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 763 } 764 765 static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg, 766 u32 value) 767 { 768 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 769 } 770 771 static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg, 772 u32 value) 773 { 774 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 775 } 776 777 static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg, 778 u32 value) 779 { 780 BUG_ON(plane == OMAP_DSS_GFX); 781 782 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 783 } 784 785 static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg, 786 u32 value) 787 { 788 BUG_ON(plane == OMAP_DSS_GFX); 789 790 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 791 } 792 793 static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg, 794 u32 value) 795 { 796 BUG_ON(plane == OMAP_DSS_GFX); 797 798 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 799 } 800 801 static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc, 802 int fir_vinc, int five_taps, 803 enum omap_color_component color_comp) 804 { 805 const struct dispc_coef *h_coef, *v_coef; 806 int i; 807 808 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 809 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 810 811 for (i = 0; i < 8; i++) { 812 u32 h, hv; 813 814 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 815 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 816 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 817 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 818 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 819 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 820 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 821 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 822 823 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 824 dispc_ovl_write_firh_reg(plane, i, h); 825 dispc_ovl_write_firhv_reg(plane, i, hv); 826 } else { 827 dispc_ovl_write_firh2_reg(plane, i, h); 828 dispc_ovl_write_firhv2_reg(plane, i, hv); 829 } 830 831 } 832 833 if (five_taps) { 834 for (i = 0; i < 8; i++) { 835 u32 v; 836 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 837 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 838 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 839 dispc_ovl_write_firv_reg(plane, i, v); 840 else 841 dispc_ovl_write_firv2_reg(plane, i, v); 842 } 843 } 844 } 845 846 847 static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, 848 const struct color_conv_coef *ct) 849 { 850 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 851 852 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 853 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 854 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 855 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 856 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 857 858 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 859 860 #undef CVAL 861 } 862 863 static void dispc_setup_color_conv_coef(void) 864 { 865 int i; 866 int num_ovl = dispc_get_num_ovls(); 867 const struct color_conv_coef ctbl_bt601_5_ovl = { 868 /* YUV -> RGB */ 869 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 870 }; 871 const struct color_conv_coef ctbl_bt601_5_wb = { 872 /* RGB -> YUV */ 873 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 874 }; 875 876 for (i = 1; i < num_ovl; i++) 877 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 878 879 if (dispc.feat->has_writeback) 880 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 881 } 882 883 static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr) 884 { 885 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 886 } 887 888 static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr) 889 { 890 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 891 } 892 893 static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr) 894 { 895 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 896 } 897 898 static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr) 899 { 900 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 901 } 902 903 static void dispc_ovl_set_pos(enum omap_plane_id plane, 904 enum omap_overlay_caps caps, int x, int y) 905 { 906 u32 val; 907 908 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 909 return; 910 911 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 912 913 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 914 } 915 916 static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width, 917 int height) 918 { 919 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 920 921 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 922 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 923 else 924 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 925 } 926 927 static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width, 928 int height) 929 { 930 u32 val; 931 932 BUG_ON(plane == OMAP_DSS_GFX); 933 934 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 935 936 if (plane == OMAP_DSS_WB) 937 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 938 else 939 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 940 } 941 942 static void dispc_ovl_set_zorder(enum omap_plane_id plane, 943 enum omap_overlay_caps caps, u8 zorder) 944 { 945 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 946 return; 947 948 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 949 } 950 951 static void dispc_ovl_enable_zorder_planes(void) 952 { 953 int i; 954 955 if (!dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 956 return; 957 958 for (i = 0; i < dispc_get_num_ovls(); i++) 959 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 960 } 961 962 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane, 963 enum omap_overlay_caps caps, bool enable) 964 { 965 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 966 return; 967 968 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 969 } 970 971 static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane, 972 enum omap_overlay_caps caps, u8 global_alpha) 973 { 974 static const unsigned shifts[] = { 0, 8, 16, 24, }; 975 int shift; 976 977 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 978 return; 979 980 shift = shifts[plane]; 981 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 982 } 983 984 static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc) 985 { 986 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 987 } 988 989 static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc) 990 { 991 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 992 } 993 994 static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc) 995 { 996 u32 m = 0; 997 if (plane != OMAP_DSS_GFX) { 998 switch (fourcc) { 999 case DRM_FORMAT_NV12: 1000 m = 0x0; break; 1001 case DRM_FORMAT_XRGB4444: 1002 m = 0x1; break; 1003 case DRM_FORMAT_RGBA4444: 1004 m = 0x2; break; 1005 case DRM_FORMAT_RGBX4444: 1006 m = 0x4; break; 1007 case DRM_FORMAT_ARGB4444: 1008 m = 0x5; break; 1009 case DRM_FORMAT_RGB565: 1010 m = 0x6; break; 1011 case DRM_FORMAT_ARGB1555: 1012 m = 0x7; break; 1013 case DRM_FORMAT_XRGB8888: 1014 m = 0x8; break; 1015 case DRM_FORMAT_RGB888: 1016 m = 0x9; break; 1017 case DRM_FORMAT_YUYV: 1018 m = 0xa; break; 1019 case DRM_FORMAT_UYVY: 1020 m = 0xb; break; 1021 case DRM_FORMAT_ARGB8888: 1022 m = 0xc; break; 1023 case DRM_FORMAT_RGBA8888: 1024 m = 0xd; break; 1025 case DRM_FORMAT_RGBX8888: 1026 m = 0xe; break; 1027 case DRM_FORMAT_XRGB1555: 1028 m = 0xf; break; 1029 default: 1030 BUG(); return; 1031 } 1032 } else { 1033 switch (fourcc) { 1034 case DRM_FORMAT_RGBX4444: 1035 m = 0x4; break; 1036 case DRM_FORMAT_ARGB4444: 1037 m = 0x5; break; 1038 case DRM_FORMAT_RGB565: 1039 m = 0x6; break; 1040 case DRM_FORMAT_ARGB1555: 1041 m = 0x7; break; 1042 case DRM_FORMAT_XRGB8888: 1043 m = 0x8; break; 1044 case DRM_FORMAT_RGB888: 1045 m = 0x9; break; 1046 case DRM_FORMAT_XRGB4444: 1047 m = 0xa; break; 1048 case DRM_FORMAT_RGBA4444: 1049 m = 0xb; break; 1050 case DRM_FORMAT_ARGB8888: 1051 m = 0xc; break; 1052 case DRM_FORMAT_RGBA8888: 1053 m = 0xd; break; 1054 case DRM_FORMAT_RGBX8888: 1055 m = 0xe; break; 1056 case DRM_FORMAT_XRGB1555: 1057 m = 0xf; break; 1058 default: 1059 BUG(); return; 1060 } 1061 } 1062 1063 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 1064 } 1065 1066 static bool format_is_yuv(u32 fourcc) 1067 { 1068 switch (fourcc) { 1069 case DRM_FORMAT_YUYV: 1070 case DRM_FORMAT_UYVY: 1071 case DRM_FORMAT_NV12: 1072 return true; 1073 default: 1074 return false; 1075 } 1076 } 1077 1078 static void dispc_ovl_configure_burst_type(enum omap_plane_id plane, 1079 enum omap_dss_rotation_type rotation_type) 1080 { 1081 if (dispc_has_feature(FEAT_BURST_2D) == 0) 1082 return; 1083 1084 if (rotation_type == OMAP_DSS_ROT_TILER) 1085 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 1086 else 1087 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 1088 } 1089 1090 static void dispc_ovl_set_channel_out(enum omap_plane_id plane, 1091 enum omap_channel channel) 1092 { 1093 int shift; 1094 u32 val; 1095 int chan = 0, chan2 = 0; 1096 1097 switch (plane) { 1098 case OMAP_DSS_GFX: 1099 shift = 8; 1100 break; 1101 case OMAP_DSS_VIDEO1: 1102 case OMAP_DSS_VIDEO2: 1103 case OMAP_DSS_VIDEO3: 1104 shift = 16; 1105 break; 1106 default: 1107 BUG(); 1108 return; 1109 } 1110 1111 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1112 if (dispc_has_feature(FEAT_MGR_LCD2)) { 1113 switch (channel) { 1114 case OMAP_DSS_CHANNEL_LCD: 1115 chan = 0; 1116 chan2 = 0; 1117 break; 1118 case OMAP_DSS_CHANNEL_DIGIT: 1119 chan = 1; 1120 chan2 = 0; 1121 break; 1122 case OMAP_DSS_CHANNEL_LCD2: 1123 chan = 0; 1124 chan2 = 1; 1125 break; 1126 case OMAP_DSS_CHANNEL_LCD3: 1127 if (dispc_has_feature(FEAT_MGR_LCD3)) { 1128 chan = 0; 1129 chan2 = 2; 1130 } else { 1131 BUG(); 1132 return; 1133 } 1134 break; 1135 case OMAP_DSS_CHANNEL_WB: 1136 chan = 0; 1137 chan2 = 3; 1138 break; 1139 default: 1140 BUG(); 1141 return; 1142 } 1143 1144 val = FLD_MOD(val, chan, shift, shift); 1145 val = FLD_MOD(val, chan2, 31, 30); 1146 } else { 1147 val = FLD_MOD(val, channel, shift, shift); 1148 } 1149 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1150 } 1151 1152 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane) 1153 { 1154 int shift; 1155 u32 val; 1156 1157 switch (plane) { 1158 case OMAP_DSS_GFX: 1159 shift = 8; 1160 break; 1161 case OMAP_DSS_VIDEO1: 1162 case OMAP_DSS_VIDEO2: 1163 case OMAP_DSS_VIDEO3: 1164 shift = 16; 1165 break; 1166 default: 1167 BUG(); 1168 return 0; 1169 } 1170 1171 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1172 1173 if (FLD_GET(val, shift, shift) == 1) 1174 return OMAP_DSS_CHANNEL_DIGIT; 1175 1176 if (!dispc_has_feature(FEAT_MGR_LCD2)) 1177 return OMAP_DSS_CHANNEL_LCD; 1178 1179 switch (FLD_GET(val, 31, 30)) { 1180 case 0: 1181 default: 1182 return OMAP_DSS_CHANNEL_LCD; 1183 case 1: 1184 return OMAP_DSS_CHANNEL_LCD2; 1185 case 2: 1186 return OMAP_DSS_CHANNEL_LCD3; 1187 case 3: 1188 return OMAP_DSS_CHANNEL_WB; 1189 } 1190 } 1191 1192 void dispc_wb_set_channel_in(enum dss_writeback_channel channel) 1193 { 1194 enum omap_plane_id plane = OMAP_DSS_WB; 1195 1196 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); 1197 } 1198 1199 static void dispc_ovl_set_burst_size(enum omap_plane_id plane, 1200 enum omap_burst_size burst_size) 1201 { 1202 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1203 int shift; 1204 1205 shift = shifts[plane]; 1206 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1207 } 1208 1209 static void dispc_configure_burst_sizes(void) 1210 { 1211 int i; 1212 const int burst_size = BURST_SIZE_X8; 1213 1214 /* Configure burst size always to maximum size */ 1215 for (i = 0; i < dispc_get_num_ovls(); ++i) 1216 dispc_ovl_set_burst_size(i, burst_size); 1217 if (dispc.feat->has_writeback) 1218 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1219 } 1220 1221 static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) 1222 { 1223 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1224 return dispc.feat->burst_size_unit * 8; 1225 } 1226 1227 static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc) 1228 { 1229 const u32 *modes; 1230 unsigned int i; 1231 1232 modes = dispc.feat->supported_color_modes[plane]; 1233 1234 for (i = 0; modes[i]; ++i) { 1235 if (modes[i] == fourcc) 1236 return true; 1237 } 1238 1239 return false; 1240 } 1241 1242 static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) 1243 { 1244 return dispc.feat->supported_color_modes[plane]; 1245 } 1246 1247 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 1248 { 1249 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1250 return; 1251 1252 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); 1253 } 1254 1255 static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 1256 const struct omap_dss_cpr_coefs *coefs) 1257 { 1258 u32 coef_r, coef_g, coef_b; 1259 1260 if (!dss_mgr_is_lcd(channel)) 1261 return; 1262 1263 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1264 FLD_VAL(coefs->rb, 9, 0); 1265 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1266 FLD_VAL(coefs->gb, 9, 0); 1267 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1268 FLD_VAL(coefs->bb, 9, 0); 1269 1270 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); 1271 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); 1272 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1273 } 1274 1275 static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane, 1276 bool enable) 1277 { 1278 u32 val; 1279 1280 BUG_ON(plane == OMAP_DSS_GFX); 1281 1282 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1283 val = FLD_MOD(val, enable, 9, 9); 1284 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1285 } 1286 1287 static void dispc_ovl_enable_replication(enum omap_plane_id plane, 1288 enum omap_overlay_caps caps, bool enable) 1289 { 1290 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1291 int shift; 1292 1293 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1294 return; 1295 1296 shift = shifts[plane]; 1297 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1298 } 1299 1300 static void dispc_mgr_set_size(enum omap_channel channel, u16 width, 1301 u16 height) 1302 { 1303 u32 val; 1304 1305 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | 1306 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); 1307 1308 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1309 } 1310 1311 static void dispc_init_fifos(void) 1312 { 1313 u32 size; 1314 int fifo; 1315 u8 start, end; 1316 u32 unit; 1317 int i; 1318 1319 unit = dispc.feat->buffer_size_unit; 1320 1321 dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1322 1323 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1324 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); 1325 size *= unit; 1326 dispc.fifo_size[fifo] = size; 1327 1328 /* 1329 * By default fifos are mapped directly to overlays, fifo 0 to 1330 * ovl 0, fifo 1 to ovl 1, etc. 1331 */ 1332 dispc.fifo_assignment[fifo] = fifo; 1333 } 1334 1335 /* 1336 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1337 * causes problems with certain use cases, like using the tiler in 2D 1338 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1339 * giving GFX plane a larger fifo. WB but should work fine with a 1340 * smaller fifo. 1341 */ 1342 if (dispc.feat->gfx_fifo_workaround) { 1343 u32 v; 1344 1345 v = dispc_read_reg(DISPC_GLOBAL_BUFFER); 1346 1347 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1348 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1349 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1350 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1351 1352 dispc_write_reg(DISPC_GLOBAL_BUFFER, v); 1353 1354 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1355 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1356 } 1357 1358 /* 1359 * Setup default fifo thresholds. 1360 */ 1361 for (i = 0; i < dispc_get_num_ovls(); ++i) { 1362 u32 low, high; 1363 const bool use_fifomerge = false; 1364 const bool manual_update = false; 1365 1366 dispc_ovl_compute_fifo_thresholds(i, &low, &high, 1367 use_fifomerge, manual_update); 1368 1369 dispc_ovl_set_fifo_threshold(i, low, high); 1370 } 1371 1372 if (dispc.feat->has_writeback) { 1373 u32 low, high; 1374 const bool use_fifomerge = false; 1375 const bool manual_update = false; 1376 1377 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, 1378 use_fifomerge, manual_update); 1379 1380 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); 1381 } 1382 } 1383 1384 static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane) 1385 { 1386 int fifo; 1387 u32 size = 0; 1388 1389 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1390 if (dispc.fifo_assignment[fifo] == plane) 1391 size += dispc.fifo_size[fifo]; 1392 } 1393 1394 return size; 1395 } 1396 1397 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 1398 u32 high) 1399 { 1400 u8 hi_start, hi_end, lo_start, lo_end; 1401 u32 unit; 1402 1403 unit = dispc.feat->buffer_size_unit; 1404 1405 WARN_ON(low % unit != 0); 1406 WARN_ON(high % unit != 0); 1407 1408 low /= unit; 1409 high /= unit; 1410 1411 dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1412 dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1413 1414 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1415 plane, 1416 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1417 lo_start, lo_end) * unit, 1418 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1419 hi_start, hi_end) * unit, 1420 low * unit, high * unit); 1421 1422 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1423 FLD_VAL(high, hi_start, hi_end) | 1424 FLD_VAL(low, lo_start, lo_end)); 1425 1426 /* 1427 * configure the preload to the pipeline's high threhold, if HT it's too 1428 * large for the preload field, set the threshold to the maximum value 1429 * that can be held by the preload register 1430 */ 1431 if (dispc_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && 1432 plane != OMAP_DSS_WB) 1433 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); 1434 } 1435 1436 void dispc_enable_fifomerge(bool enable) 1437 { 1438 if (!dispc_has_feature(FEAT_FIFO_MERGE)) { 1439 WARN_ON(enable); 1440 return; 1441 } 1442 1443 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1444 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1445 } 1446 1447 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 1448 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1449 bool manual_update) 1450 { 1451 /* 1452 * All sizes are in bytes. Both the buffer and burst are made of 1453 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1454 */ 1455 1456 unsigned buf_unit = dispc.feat->buffer_size_unit; 1457 unsigned ovl_fifo_size, total_fifo_size, burst_size; 1458 int i; 1459 1460 burst_size = dispc_ovl_get_burst_size(plane); 1461 ovl_fifo_size = dispc_ovl_get_fifo_size(plane); 1462 1463 if (use_fifomerge) { 1464 total_fifo_size = 0; 1465 for (i = 0; i < dispc_get_num_ovls(); ++i) 1466 total_fifo_size += dispc_ovl_get_fifo_size(i); 1467 } else { 1468 total_fifo_size = ovl_fifo_size; 1469 } 1470 1471 /* 1472 * We use the same low threshold for both fifomerge and non-fifomerge 1473 * cases, but for fifomerge we calculate the high threshold using the 1474 * combined fifo size 1475 */ 1476 1477 if (manual_update && dispc_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { 1478 *fifo_low = ovl_fifo_size - burst_size * 2; 1479 *fifo_high = total_fifo_size - burst_size; 1480 } else if (plane == OMAP_DSS_WB) { 1481 /* 1482 * Most optimal configuration for writeback is to push out data 1483 * to the interconnect the moment writeback pushes enough pixels 1484 * in the FIFO to form a burst 1485 */ 1486 *fifo_low = 0; 1487 *fifo_high = burst_size; 1488 } else { 1489 *fifo_low = ovl_fifo_size - burst_size; 1490 *fifo_high = total_fifo_size - buf_unit; 1491 } 1492 } 1493 1494 static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable) 1495 { 1496 int bit; 1497 1498 if (plane == OMAP_DSS_GFX) 1499 bit = 14; 1500 else 1501 bit = 23; 1502 1503 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1504 } 1505 1506 static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane, 1507 int low, int high) 1508 { 1509 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1510 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1511 } 1512 1513 static void dispc_init_mflag(void) 1514 { 1515 int i; 1516 1517 /* 1518 * HACK: NV12 color format and MFLAG seem to have problems working 1519 * together: using two displays, and having an NV12 overlay on one of 1520 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1521 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1522 * remove the errors, but there doesn't seem to be a clear logic on 1523 * which values work and which not. 1524 * 1525 * As a work-around, set force MFLAG to always on. 1526 */ 1527 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1528 (1 << 0) | /* MFLAG_CTRL = force always on */ 1529 (0 << 2)); /* MFLAG_START = disable */ 1530 1531 for (i = 0; i < dispc_get_num_ovls(); ++i) { 1532 u32 size = dispc_ovl_get_fifo_size(i); 1533 u32 unit = dispc.feat->buffer_size_unit; 1534 u32 low, high; 1535 1536 dispc_ovl_set_mflag(i, true); 1537 1538 /* 1539 * Simulation team suggests below thesholds: 1540 * HT = fifosize * 5 / 8; 1541 * LT = fifosize * 4 / 8; 1542 */ 1543 1544 low = size * 4 / 8 / unit; 1545 high = size * 5 / 8 / unit; 1546 1547 dispc_ovl_set_mflag_threshold(i, low, high); 1548 } 1549 1550 if (dispc.feat->has_writeback) { 1551 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); 1552 u32 unit = dispc.feat->buffer_size_unit; 1553 u32 low, high; 1554 1555 dispc_ovl_set_mflag(OMAP_DSS_WB, true); 1556 1557 /* 1558 * Simulation team suggests below thesholds: 1559 * HT = fifosize * 5 / 8; 1560 * LT = fifosize * 4 / 8; 1561 */ 1562 1563 low = size * 4 / 8 / unit; 1564 high = size * 5 / 8 / unit; 1565 1566 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); 1567 } 1568 } 1569 1570 static void dispc_ovl_set_fir(enum omap_plane_id plane, 1571 int hinc, int vinc, 1572 enum omap_color_component color_comp) 1573 { 1574 u32 val; 1575 1576 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1577 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1578 1579 dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); 1580 dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); 1581 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1582 FLD_VAL(hinc, hinc_start, hinc_end); 1583 1584 dispc_write_reg(DISPC_OVL_FIR(plane), val); 1585 } else { 1586 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1587 dispc_write_reg(DISPC_OVL_FIR2(plane), val); 1588 } 1589 } 1590 1591 static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, 1592 int vaccu) 1593 { 1594 u32 val; 1595 u8 hor_start, hor_end, vert_start, vert_end; 1596 1597 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1598 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1599 1600 val = FLD_VAL(vaccu, vert_start, vert_end) | 1601 FLD_VAL(haccu, hor_start, hor_end); 1602 1603 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1604 } 1605 1606 static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, 1607 int vaccu) 1608 { 1609 u32 val; 1610 u8 hor_start, hor_end, vert_start, vert_end; 1611 1612 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1613 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1614 1615 val = FLD_VAL(vaccu, vert_start, vert_end) | 1616 FLD_VAL(haccu, hor_start, hor_end); 1617 1618 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1619 } 1620 1621 static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu, 1622 int vaccu) 1623 { 1624 u32 val; 1625 1626 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1627 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1628 } 1629 1630 static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu, 1631 int vaccu) 1632 { 1633 u32 val; 1634 1635 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1636 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1637 } 1638 1639 static void dispc_ovl_set_scale_param(enum omap_plane_id plane, 1640 u16 orig_width, u16 orig_height, 1641 u16 out_width, u16 out_height, 1642 bool five_taps, u8 rotation, 1643 enum omap_color_component color_comp) 1644 { 1645 int fir_hinc, fir_vinc; 1646 1647 fir_hinc = 1024 * orig_width / out_width; 1648 fir_vinc = 1024 * orig_height / out_height; 1649 1650 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, 1651 color_comp); 1652 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1653 } 1654 1655 static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, 1656 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1657 bool ilace, u32 fourcc, u8 rotation) 1658 { 1659 int h_accu2_0, h_accu2_1; 1660 int v_accu2_0, v_accu2_1; 1661 int chroma_hinc, chroma_vinc; 1662 int idx; 1663 1664 struct accu { 1665 s8 h0_m, h0_n; 1666 s8 h1_m, h1_n; 1667 s8 v0_m, v0_n; 1668 s8 v1_m, v1_n; 1669 }; 1670 1671 const struct accu *accu_table; 1672 const struct accu *accu_val; 1673 1674 static const struct accu accu_nv12[4] = { 1675 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1676 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1677 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1678 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1679 }; 1680 1681 static const struct accu accu_nv12_ilace[4] = { 1682 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1683 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1684 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1685 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1686 }; 1687 1688 static const struct accu accu_yuv[4] = { 1689 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1690 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1691 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1692 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1693 }; 1694 1695 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1696 switch (rotation & DRM_MODE_ROTATE_MASK) { 1697 default: 1698 case DRM_MODE_ROTATE_0: 1699 idx = 0; 1700 break; 1701 case DRM_MODE_ROTATE_90: 1702 idx = 3; 1703 break; 1704 case DRM_MODE_ROTATE_180: 1705 idx = 2; 1706 break; 1707 case DRM_MODE_ROTATE_270: 1708 idx = 1; 1709 break; 1710 } 1711 1712 switch (fourcc) { 1713 case DRM_FORMAT_NV12: 1714 if (ilace) 1715 accu_table = accu_nv12_ilace; 1716 else 1717 accu_table = accu_nv12; 1718 break; 1719 case DRM_FORMAT_YUYV: 1720 case DRM_FORMAT_UYVY: 1721 accu_table = accu_yuv; 1722 break; 1723 default: 1724 BUG(); 1725 return; 1726 } 1727 1728 accu_val = &accu_table[idx]; 1729 1730 chroma_hinc = 1024 * orig_width / out_width; 1731 chroma_vinc = 1024 * orig_height / out_height; 1732 1733 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1734 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1735 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1736 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1737 1738 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); 1739 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1740 } 1741 1742 static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, 1743 u16 orig_width, u16 orig_height, 1744 u16 out_width, u16 out_height, 1745 bool ilace, bool five_taps, 1746 bool fieldmode, u32 fourcc, 1747 u8 rotation) 1748 { 1749 int accu0 = 0; 1750 int accu1 = 0; 1751 u32 l; 1752 1753 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1754 out_width, out_height, five_taps, 1755 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1756 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1757 1758 /* RESIZEENABLE and VERTICALTAPS */ 1759 l &= ~((0x3 << 5) | (0x1 << 21)); 1760 l |= (orig_width != out_width) ? (1 << 5) : 0; 1761 l |= (orig_height != out_height) ? (1 << 6) : 0; 1762 l |= five_taps ? (1 << 21) : 0; 1763 1764 /* VRESIZECONF and HRESIZECONF */ 1765 if (dispc_has_feature(FEAT_RESIZECONF)) { 1766 l &= ~(0x3 << 7); 1767 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1768 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1769 } 1770 1771 /* LINEBUFFERSPLIT */ 1772 if (dispc_has_feature(FEAT_LINEBUFFERSPLIT)) { 1773 l &= ~(0x1 << 22); 1774 l |= five_taps ? (1 << 22) : 0; 1775 } 1776 1777 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 1778 1779 /* 1780 * field 0 = even field = bottom field 1781 * field 1 = odd field = top field 1782 */ 1783 if (ilace && !fieldmode) { 1784 accu1 = 0; 1785 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1786 if (accu0 >= 1024/2) { 1787 accu1 = 1024/2; 1788 accu0 -= accu1; 1789 } 1790 } 1791 1792 dispc_ovl_set_vid_accu0(plane, 0, accu0); 1793 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1794 } 1795 1796 static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, 1797 u16 orig_width, u16 orig_height, 1798 u16 out_width, u16 out_height, 1799 bool ilace, bool five_taps, 1800 bool fieldmode, u32 fourcc, 1801 u8 rotation) 1802 { 1803 int scale_x = out_width != orig_width; 1804 int scale_y = out_height != orig_height; 1805 bool chroma_upscale = plane != OMAP_DSS_WB; 1806 1807 if (!dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1808 return; 1809 1810 if (!format_is_yuv(fourcc)) { 1811 /* reset chroma resampling for RGB formats */ 1812 if (plane != OMAP_DSS_WB) 1813 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); 1814 return; 1815 } 1816 1817 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, 1818 out_height, ilace, fourcc, rotation); 1819 1820 switch (fourcc) { 1821 case DRM_FORMAT_NV12: 1822 if (chroma_upscale) { 1823 /* UV is subsampled by 2 horizontally and vertically */ 1824 orig_height >>= 1; 1825 orig_width >>= 1; 1826 } else { 1827 /* UV is downsampled by 2 horizontally and vertically */ 1828 orig_height <<= 1; 1829 orig_width <<= 1; 1830 } 1831 1832 break; 1833 case DRM_FORMAT_YUYV: 1834 case DRM_FORMAT_UYVY: 1835 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1836 if (!drm_rotation_90_or_270(rotation)) { 1837 if (chroma_upscale) 1838 /* UV is subsampled by 2 horizontally */ 1839 orig_width >>= 1; 1840 else 1841 /* UV is downsampled by 2 horizontally */ 1842 orig_width <<= 1; 1843 } 1844 1845 /* must use FIR for YUV422 if rotated */ 1846 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0) 1847 scale_x = scale_y = true; 1848 1849 break; 1850 default: 1851 BUG(); 1852 return; 1853 } 1854 1855 if (out_width != orig_width) 1856 scale_x = true; 1857 if (out_height != orig_height) 1858 scale_y = true; 1859 1860 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1861 out_width, out_height, five_taps, 1862 rotation, DISPC_COLOR_COMPONENT_UV); 1863 1864 if (plane != OMAP_DSS_WB) 1865 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 1866 (scale_x || scale_y) ? 1 : 0, 8, 8); 1867 1868 /* set H scaling */ 1869 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1870 /* set V scaling */ 1871 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1872 } 1873 1874 static void dispc_ovl_set_scaling(enum omap_plane_id plane, 1875 u16 orig_width, u16 orig_height, 1876 u16 out_width, u16 out_height, 1877 bool ilace, bool five_taps, 1878 bool fieldmode, u32 fourcc, 1879 u8 rotation) 1880 { 1881 BUG_ON(plane == OMAP_DSS_GFX); 1882 1883 dispc_ovl_set_scaling_common(plane, 1884 orig_width, orig_height, 1885 out_width, out_height, 1886 ilace, five_taps, 1887 fieldmode, fourcc, 1888 rotation); 1889 1890 dispc_ovl_set_scaling_uv(plane, 1891 orig_width, orig_height, 1892 out_width, out_height, 1893 ilace, five_taps, 1894 fieldmode, fourcc, 1895 rotation); 1896 } 1897 1898 static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, 1899 enum omap_dss_rotation_type rotation_type, u32 fourcc) 1900 { 1901 bool row_repeat = false; 1902 int vidrot = 0; 1903 1904 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1905 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) { 1906 1907 if (rotation & DRM_MODE_REFLECT_X) { 1908 switch (rotation & DRM_MODE_ROTATE_MASK) { 1909 case DRM_MODE_ROTATE_0: 1910 vidrot = 2; 1911 break; 1912 case DRM_MODE_ROTATE_90: 1913 vidrot = 1; 1914 break; 1915 case DRM_MODE_ROTATE_180: 1916 vidrot = 0; 1917 break; 1918 case DRM_MODE_ROTATE_270: 1919 vidrot = 3; 1920 break; 1921 } 1922 } else { 1923 switch (rotation & DRM_MODE_ROTATE_MASK) { 1924 case DRM_MODE_ROTATE_0: 1925 vidrot = 0; 1926 break; 1927 case DRM_MODE_ROTATE_90: 1928 vidrot = 3; 1929 break; 1930 case DRM_MODE_ROTATE_180: 1931 vidrot = 2; 1932 break; 1933 case DRM_MODE_ROTATE_270: 1934 vidrot = 1; 1935 break; 1936 } 1937 } 1938 1939 if (drm_rotation_90_or_270(rotation)) 1940 row_repeat = true; 1941 else 1942 row_repeat = false; 1943 } 1944 1945 /* 1946 * OMAP4/5 Errata i631: 1947 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 1948 * rows beyond the framebuffer, which may cause OCP error. 1949 */ 1950 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) 1951 vidrot = 1; 1952 1953 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 1954 if (dispc_has_feature(FEAT_ROWREPEATENABLE)) 1955 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1956 row_repeat ? 1 : 0, 18, 18); 1957 1958 if (dispc_ovl_color_mode_supported(plane, DRM_FORMAT_NV12)) { 1959 bool doublestride = 1960 fourcc == DRM_FORMAT_NV12 && 1961 rotation_type == OMAP_DSS_ROT_TILER && 1962 !drm_rotation_90_or_270(rotation); 1963 1964 /* DOUBLESTRIDE */ 1965 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); 1966 } 1967 } 1968 1969 static int color_mode_to_bpp(u32 fourcc) 1970 { 1971 switch (fourcc) { 1972 case DRM_FORMAT_NV12: 1973 return 8; 1974 case DRM_FORMAT_RGBX4444: 1975 case DRM_FORMAT_RGB565: 1976 case DRM_FORMAT_ARGB4444: 1977 case DRM_FORMAT_YUYV: 1978 case DRM_FORMAT_UYVY: 1979 case DRM_FORMAT_RGBA4444: 1980 case DRM_FORMAT_XRGB4444: 1981 case DRM_FORMAT_ARGB1555: 1982 case DRM_FORMAT_XRGB1555: 1983 return 16; 1984 case DRM_FORMAT_RGB888: 1985 return 24; 1986 case DRM_FORMAT_XRGB8888: 1987 case DRM_FORMAT_ARGB8888: 1988 case DRM_FORMAT_RGBA8888: 1989 case DRM_FORMAT_RGBX8888: 1990 return 32; 1991 default: 1992 BUG(); 1993 return 0; 1994 } 1995 } 1996 1997 static s32 pixinc(int pixels, u8 ps) 1998 { 1999 if (pixels == 1) 2000 return 1; 2001 else if (pixels > 1) 2002 return 1 + (pixels - 1) * ps; 2003 else if (pixels < 0) 2004 return 1 - (-pixels + 1) * ps; 2005 else 2006 BUG(); 2007 return 0; 2008 } 2009 2010 static void calc_offset(u16 screen_width, u16 width, 2011 u32 fourcc, bool fieldmode, 2012 unsigned int field_offset, unsigned *offset0, unsigned *offset1, 2013 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, 2014 enum omap_dss_rotation_type rotation_type, u8 rotation) 2015 { 2016 u8 ps; 2017 2018 ps = color_mode_to_bpp(fourcc) / 8; 2019 2020 DSSDBG("scrw %d, width %d\n", screen_width, width); 2021 2022 if (rotation_type == OMAP_DSS_ROT_TILER && 2023 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && 2024 drm_rotation_90_or_270(rotation)) { 2025 /* 2026 * HACK: ROW_INC needs to be calculated with TILER units. 2027 * We get such 'screen_width' that multiplying it with the 2028 * YUV422 pixel size gives the correct TILER container width. 2029 * However, 'width' is in pixels and multiplying it with YUV422 2030 * pixel size gives incorrect result. We thus multiply it here 2031 * with 2 to match the 32 bit TILER unit size. 2032 */ 2033 width *= 2; 2034 } 2035 2036 /* 2037 * field 0 = even field = bottom field 2038 * field 1 = odd field = top field 2039 */ 2040 *offset0 = field_offset * screen_width * ps; 2041 *offset1 = 0; 2042 2043 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 2044 (fieldmode ? screen_width : 0), ps); 2045 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) 2046 *pix_inc = pixinc(x_predecim, 2 * ps); 2047 else 2048 *pix_inc = pixinc(x_predecim, ps); 2049 } 2050 2051 /* 2052 * This function is used to avoid synclosts in OMAP3, because of some 2053 * undocumented horizontal position and timing related limitations. 2054 */ 2055 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2056 const struct videomode *vm, u16 pos_x, 2057 u16 width, u16 height, u16 out_width, u16 out_height, 2058 bool five_taps) 2059 { 2060 const int ds = DIV_ROUND_UP(height, out_height); 2061 unsigned long nonactive; 2062 static const u8 limits[3] = { 8, 10, 20 }; 2063 u64 val, blank; 2064 int i; 2065 2066 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + 2067 vm->hback_porch - out_width; 2068 2069 i = 0; 2070 if (out_height < height) 2071 i++; 2072 if (out_width < width) 2073 i++; 2074 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * 2075 lclk, pclk); 2076 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2077 if (blank <= limits[i]) 2078 return -EINVAL; 2079 2080 /* FIXME add checks for 3-tap filter once the limitations are known */ 2081 if (!five_taps) 2082 return 0; 2083 2084 /* 2085 * Pixel data should be prepared before visible display point starts. 2086 * So, atleast DS-2 lines must have already been fetched by DISPC 2087 * during nonactive - pos_x period. 2088 */ 2089 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 2090 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2091 val, max(0, ds - 2) * width); 2092 if (val < max(0, ds - 2) * width) 2093 return -EINVAL; 2094 2095 /* 2096 * All lines need to be refilled during the nonactive period of which 2097 * only one line can be loaded during the active period. So, atleast 2098 * DS - 1 lines should be loaded during nonactive period. 2099 */ 2100 val = div_u64((u64)nonactive * lclk, pclk); 2101 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2102 val, max(0, ds - 1) * width); 2103 if (val < max(0, ds - 1) * width) 2104 return -EINVAL; 2105 2106 return 0; 2107 } 2108 2109 static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2110 const struct videomode *vm, u16 width, 2111 u16 height, u16 out_width, u16 out_height, 2112 u32 fourcc) 2113 { 2114 u32 core_clk = 0; 2115 u64 tmp; 2116 2117 if (height <= out_height && width <= out_width) 2118 return (unsigned long) pclk; 2119 2120 if (height > out_height) { 2121 unsigned int ppl = vm->hactive; 2122 2123 tmp = (u64)pclk * height * out_width; 2124 do_div(tmp, 2 * out_height * ppl); 2125 core_clk = tmp; 2126 2127 if (height > 2 * out_height) { 2128 if (ppl == out_width) 2129 return 0; 2130 2131 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2132 do_div(tmp, 2 * out_height * (ppl - out_width)); 2133 core_clk = max_t(u32, core_clk, tmp); 2134 } 2135 } 2136 2137 if (width > out_width) { 2138 tmp = (u64)pclk * width; 2139 do_div(tmp, out_width); 2140 core_clk = max_t(u32, core_clk, tmp); 2141 2142 if (fourcc == DRM_FORMAT_XRGB8888) 2143 core_clk <<= 1; 2144 } 2145 2146 return core_clk; 2147 } 2148 2149 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2150 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2151 { 2152 if (height > out_height && width > out_width) 2153 return pclk * 4; 2154 else 2155 return pclk * 2; 2156 } 2157 2158 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2159 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2160 { 2161 unsigned int hf, vf; 2162 2163 /* 2164 * FIXME how to determine the 'A' factor 2165 * for the no downscaling case ? 2166 */ 2167 2168 if (width > 3 * out_width) 2169 hf = 4; 2170 else if (width > 2 * out_width) 2171 hf = 3; 2172 else if (width > out_width) 2173 hf = 2; 2174 else 2175 hf = 1; 2176 if (height > out_height) 2177 vf = 2; 2178 else 2179 vf = 1; 2180 2181 return pclk * vf * hf; 2182 } 2183 2184 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2185 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2186 { 2187 /* 2188 * If the overlay/writeback is in mem to mem mode, there are no 2189 * downscaling limitations with respect to pixel clock, return 1 as 2190 * required core clock to represent that we have sufficient enough 2191 * core clock to do maximum downscaling 2192 */ 2193 if (mem_to_mem) 2194 return 1; 2195 2196 if (width > out_width) 2197 return DIV_ROUND_UP(pclk, out_width) * width; 2198 else 2199 return pclk; 2200 } 2201 2202 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2203 const struct videomode *vm, 2204 u16 width, u16 height, u16 out_width, u16 out_height, 2205 u32 fourcc, bool *five_taps, 2206 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2207 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2208 { 2209 int error; 2210 u16 in_width, in_height; 2211 int min_factor = min(*decim_x, *decim_y); 2212 const int maxsinglelinewidth = dispc.feat->max_line_width; 2213 2214 *five_taps = false; 2215 2216 do { 2217 in_height = height / *decim_y; 2218 in_width = width / *decim_x; 2219 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2220 in_height, out_width, out_height, mem_to_mem); 2221 error = (in_width > maxsinglelinewidth || !*core_clk || 2222 *core_clk > dispc_core_clk_rate()); 2223 if (error) { 2224 if (*decim_x == *decim_y) { 2225 *decim_x = min_factor; 2226 ++*decim_y; 2227 } else { 2228 swap(*decim_x, *decim_y); 2229 if (*decim_x < *decim_y) 2230 ++*decim_x; 2231 } 2232 } 2233 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2234 2235 if (error) { 2236 DSSERR("failed to find scaling settings\n"); 2237 return -EINVAL; 2238 } 2239 2240 if (in_width > maxsinglelinewidth) { 2241 DSSERR("Cannot scale max input width exceeded"); 2242 return -EINVAL; 2243 } 2244 return 0; 2245 } 2246 2247 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2248 const struct videomode *vm, 2249 u16 width, u16 height, u16 out_width, u16 out_height, 2250 u32 fourcc, bool *five_taps, 2251 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2252 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2253 { 2254 int error; 2255 u16 in_width, in_height; 2256 const int maxsinglelinewidth = dispc.feat->max_line_width; 2257 2258 do { 2259 in_height = height / *decim_y; 2260 in_width = width / *decim_x; 2261 *five_taps = in_height > out_height; 2262 2263 if (in_width > maxsinglelinewidth) 2264 if (in_height > out_height && 2265 in_height < out_height * 2) 2266 *five_taps = false; 2267 again: 2268 if (*five_taps) 2269 *core_clk = calc_core_clk_five_taps(pclk, vm, 2270 in_width, in_height, out_width, 2271 out_height, fourcc); 2272 else 2273 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2274 in_height, out_width, out_height, 2275 mem_to_mem); 2276 2277 error = check_horiz_timing_omap3(pclk, lclk, vm, 2278 pos_x, in_width, in_height, out_width, 2279 out_height, *five_taps); 2280 if (error && *five_taps) { 2281 *five_taps = false; 2282 goto again; 2283 } 2284 2285 error = (error || in_width > maxsinglelinewidth * 2 || 2286 (in_width > maxsinglelinewidth && *five_taps) || 2287 !*core_clk || *core_clk > dispc_core_clk_rate()); 2288 2289 if (!error) { 2290 /* verify that we're inside the limits of scaler */ 2291 if (in_width / 4 > out_width) 2292 error = 1; 2293 2294 if (*five_taps) { 2295 if (in_height / 4 > out_height) 2296 error = 1; 2297 } else { 2298 if (in_height / 2 > out_height) 2299 error = 1; 2300 } 2301 } 2302 2303 if (error) 2304 ++*decim_y; 2305 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2306 2307 if (error) { 2308 DSSERR("failed to find scaling settings\n"); 2309 return -EINVAL; 2310 } 2311 2312 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width, 2313 in_height, out_width, out_height, *five_taps)) { 2314 DSSERR("horizontal timing too tight\n"); 2315 return -EINVAL; 2316 } 2317 2318 if (in_width > (maxsinglelinewidth * 2)) { 2319 DSSERR("Cannot setup scaling"); 2320 DSSERR("width exceeds maximum width possible"); 2321 return -EINVAL; 2322 } 2323 2324 if (in_width > maxsinglelinewidth && *five_taps) { 2325 DSSERR("cannot setup scaling with five taps"); 2326 return -EINVAL; 2327 } 2328 return 0; 2329 } 2330 2331 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2332 const struct videomode *vm, 2333 u16 width, u16 height, u16 out_width, u16 out_height, 2334 u32 fourcc, bool *five_taps, 2335 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2336 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2337 { 2338 u16 in_width, in_width_max; 2339 int decim_x_min = *decim_x; 2340 u16 in_height = height / *decim_y; 2341 const int maxsinglelinewidth = dispc.feat->max_line_width; 2342 const int maxdownscale = dispc.feat->max_downscale; 2343 2344 if (mem_to_mem) { 2345 in_width_max = out_width * maxdownscale; 2346 } else { 2347 in_width_max = dispc_core_clk_rate() / 2348 DIV_ROUND_UP(pclk, out_width); 2349 } 2350 2351 *decim_x = DIV_ROUND_UP(width, in_width_max); 2352 2353 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; 2354 if (*decim_x > *x_predecim) 2355 return -EINVAL; 2356 2357 do { 2358 in_width = width / *decim_x; 2359 } while (*decim_x <= *x_predecim && 2360 in_width > maxsinglelinewidth && ++*decim_x); 2361 2362 if (in_width > maxsinglelinewidth) { 2363 DSSERR("Cannot scale width exceeds max line width"); 2364 return -EINVAL; 2365 } 2366 2367 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) { 2368 /* 2369 * Let's disable all scaling that requires horizontal 2370 * decimation with higher factor than 4, until we have 2371 * better estimates of what we can and can not 2372 * do. However, NV12 color format appears to work Ok 2373 * with all decimation factors. 2374 * 2375 * When decimating horizontally by more that 4 the dss 2376 * is not able to fetch the data in burst mode. When 2377 * this happens it is hard to tell if there enough 2378 * bandwidth. Despite what theory says this appears to 2379 * be true also for 16-bit color formats. 2380 */ 2381 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x); 2382 2383 return -EINVAL; 2384 } 2385 2386 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, 2387 out_width, out_height, mem_to_mem); 2388 return 0; 2389 } 2390 2391 #define DIV_FRAC(dividend, divisor) \ 2392 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2393 2394 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2395 enum omap_overlay_caps caps, 2396 const struct videomode *vm, 2397 u16 width, u16 height, u16 out_width, u16 out_height, 2398 u32 fourcc, bool *five_taps, 2399 int *x_predecim, int *y_predecim, u16 pos_x, 2400 enum omap_dss_rotation_type rotation_type, bool mem_to_mem) 2401 { 2402 const int maxdownscale = dispc.feat->max_downscale; 2403 const int max_decim_limit = 16; 2404 unsigned long core_clk = 0; 2405 int decim_x, decim_y, ret; 2406 2407 if (width == out_width && height == out_height) 2408 return 0; 2409 2410 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { 2411 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2412 return -EINVAL; 2413 } 2414 2415 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2416 return -EINVAL; 2417 2418 if (mem_to_mem) { 2419 *x_predecim = *y_predecim = 1; 2420 } else { 2421 *x_predecim = max_decim_limit; 2422 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2423 dispc_has_feature(FEAT_BURST_2D)) ? 2424 2 : max_decim_limit; 2425 } 2426 2427 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); 2428 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); 2429 2430 if (decim_x > *x_predecim || out_width > width * 8) 2431 return -EINVAL; 2432 2433 if (decim_y > *y_predecim || out_height > height * 8) 2434 return -EINVAL; 2435 2436 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height, 2437 out_width, out_height, fourcc, five_taps, 2438 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2439 mem_to_mem); 2440 if (ret) 2441 return ret; 2442 2443 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2444 width, height, 2445 out_width, out_height, 2446 out_width / width, DIV_FRAC(out_width, width), 2447 out_height / height, DIV_FRAC(out_height, height), 2448 2449 decim_x, decim_y, 2450 width / decim_x, height / decim_y, 2451 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2452 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2453 2454 *five_taps ? 5 : 3, 2455 core_clk, dispc_core_clk_rate()); 2456 2457 if (!core_clk || core_clk > dispc_core_clk_rate()) { 2458 DSSERR("failed to set up scaling, " 2459 "required core clk rate = %lu Hz, " 2460 "current core clk rate = %lu Hz\n", 2461 core_clk, dispc_core_clk_rate()); 2462 return -EINVAL; 2463 } 2464 2465 *x_predecim = decim_x; 2466 *y_predecim = decim_y; 2467 return 0; 2468 } 2469 2470 static int dispc_ovl_setup_common(enum omap_plane_id plane, 2471 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2472 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2473 u16 out_width, u16 out_height, u32 fourcc, 2474 u8 rotation, u8 zorder, u8 pre_mult_alpha, 2475 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2476 bool replication, const struct videomode *vm, 2477 bool mem_to_mem) 2478 { 2479 bool five_taps = true; 2480 bool fieldmode = false; 2481 int r, cconv = 0; 2482 unsigned offset0, offset1; 2483 s32 row_inc; 2484 s32 pix_inc; 2485 u16 frame_width, frame_height; 2486 unsigned int field_offset = 0; 2487 u16 in_height = height; 2488 u16 in_width = width; 2489 int x_predecim = 1, y_predecim = 1; 2490 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); 2491 unsigned long pclk = dispc_plane_pclk_rate(plane); 2492 unsigned long lclk = dispc_plane_lclk_rate(plane); 2493 2494 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2495 return -EINVAL; 2496 2497 if (format_is_yuv(fourcc) && (in_width & 1)) { 2498 DSSERR("input width %d is not even for YUV format\n", in_width); 2499 return -EINVAL; 2500 } 2501 2502 out_width = out_width == 0 ? width : out_width; 2503 out_height = out_height == 0 ? height : out_height; 2504 2505 if (ilace && height == out_height) 2506 fieldmode = true; 2507 2508 if (ilace) { 2509 if (fieldmode) 2510 in_height /= 2; 2511 pos_y /= 2; 2512 out_height /= 2; 2513 2514 DSSDBG("adjusting for ilace: height %d, pos_y %d, " 2515 "out_height %d\n", in_height, pos_y, 2516 out_height); 2517 } 2518 2519 if (!dispc_ovl_color_mode_supported(plane, fourcc)) 2520 return -EINVAL; 2521 2522 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width, 2523 in_height, out_width, out_height, fourcc, 2524 &five_taps, &x_predecim, &y_predecim, pos_x, 2525 rotation_type, mem_to_mem); 2526 if (r) 2527 return r; 2528 2529 in_width = in_width / x_predecim; 2530 in_height = in_height / y_predecim; 2531 2532 if (x_predecim > 1 || y_predecim > 1) 2533 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2534 x_predecim, y_predecim, in_width, in_height); 2535 2536 if (format_is_yuv(fourcc) && (in_width & 1)) { 2537 DSSDBG("predecimated input width is not even for YUV format\n"); 2538 DSSDBG("adjusting input width %d -> %d\n", 2539 in_width, in_width & ~1); 2540 2541 in_width &= ~1; 2542 } 2543 2544 if (format_is_yuv(fourcc)) 2545 cconv = 1; 2546 2547 if (ilace && !fieldmode) { 2548 /* 2549 * when downscaling the bottom field may have to start several 2550 * source lines below the top field. Unfortunately ACCUI 2551 * registers will only hold the fractional part of the offset 2552 * so the integer part must be added to the base address of the 2553 * bottom field. 2554 */ 2555 if (!in_height || in_height == out_height) 2556 field_offset = 0; 2557 else 2558 field_offset = in_height / out_height / 2; 2559 } 2560 2561 /* Fields are independent but interleaved in memory. */ 2562 if (fieldmode) 2563 field_offset = 1; 2564 2565 offset0 = 0; 2566 offset1 = 0; 2567 row_inc = 0; 2568 pix_inc = 0; 2569 2570 if (plane == OMAP_DSS_WB) { 2571 frame_width = out_width; 2572 frame_height = out_height; 2573 } else { 2574 frame_width = in_width; 2575 frame_height = height; 2576 } 2577 2578 calc_offset(screen_width, frame_width, 2579 fourcc, fieldmode, field_offset, 2580 &offset0, &offset1, &row_inc, &pix_inc, 2581 x_predecim, y_predecim, 2582 rotation_type, rotation); 2583 2584 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2585 offset0, offset1, row_inc, pix_inc); 2586 2587 dispc_ovl_set_color_mode(plane, fourcc); 2588 2589 dispc_ovl_configure_burst_type(plane, rotation_type); 2590 2591 if (dispc.feat->reverse_ilace_field_order) 2592 swap(offset0, offset1); 2593 2594 dispc_ovl_set_ba0(plane, paddr + offset0); 2595 dispc_ovl_set_ba1(plane, paddr + offset1); 2596 2597 if (fourcc == DRM_FORMAT_NV12) { 2598 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); 2599 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); 2600 } 2601 2602 if (dispc.feat->last_pixel_inc_missing) 2603 row_inc += pix_inc - 1; 2604 2605 dispc_ovl_set_row_inc(plane, row_inc); 2606 dispc_ovl_set_pix_inc(plane, pix_inc); 2607 2608 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2609 in_height, out_width, out_height); 2610 2611 dispc_ovl_set_pos(plane, caps, pos_x, pos_y); 2612 2613 dispc_ovl_set_input_size(plane, in_width, in_height); 2614 2615 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2616 dispc_ovl_set_scaling(plane, in_width, in_height, out_width, 2617 out_height, ilace, five_taps, fieldmode, 2618 fourcc, rotation); 2619 dispc_ovl_set_output_size(plane, out_width, out_height); 2620 dispc_ovl_set_vid_color_conv(plane, cconv); 2621 } 2622 2623 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc); 2624 2625 dispc_ovl_set_zorder(plane, caps, zorder); 2626 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); 2627 dispc_ovl_setup_global_alpha(plane, caps, global_alpha); 2628 2629 dispc_ovl_enable_replication(plane, caps, replication); 2630 2631 return 0; 2632 } 2633 2634 static int dispc_ovl_setup(enum omap_plane_id plane, 2635 const struct omap_overlay_info *oi, 2636 const struct videomode *vm, bool mem_to_mem, 2637 enum omap_channel channel) 2638 { 2639 int r; 2640 enum omap_overlay_caps caps = dispc.feat->overlay_caps[plane]; 2641 const bool replication = true; 2642 2643 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2644 " %dx%d, cmode %x, rot %d, chan %d repl %d\n", 2645 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2646 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2647 oi->fourcc, oi->rotation, channel, replication); 2648 2649 dispc_ovl_set_channel_out(plane, channel); 2650 2651 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, 2652 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2653 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, 2654 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2655 oi->rotation_type, replication, vm, mem_to_mem); 2656 2657 return r; 2658 } 2659 2660 int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2661 bool mem_to_mem, const struct videomode *vm) 2662 { 2663 int r; 2664 u32 l; 2665 enum omap_plane_id plane = OMAP_DSS_WB; 2666 const int pos_x = 0, pos_y = 0; 2667 const u8 zorder = 0, global_alpha = 0; 2668 const bool replication = true; 2669 bool truncation; 2670 int in_width = vm->hactive; 2671 int in_height = vm->vactive; 2672 enum omap_overlay_caps caps = 2673 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2674 2675 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " 2676 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, 2677 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); 2678 2679 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, 2680 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2681 wi->height, wi->fourcc, wi->rotation, zorder, 2682 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2683 replication, vm, mem_to_mem); 2684 2685 switch (wi->fourcc) { 2686 case DRM_FORMAT_RGB565: 2687 case DRM_FORMAT_RGB888: 2688 case DRM_FORMAT_ARGB4444: 2689 case DRM_FORMAT_RGBA4444: 2690 case DRM_FORMAT_RGBX4444: 2691 case DRM_FORMAT_ARGB1555: 2692 case DRM_FORMAT_XRGB1555: 2693 case DRM_FORMAT_XRGB4444: 2694 truncation = true; 2695 break; 2696 default: 2697 truncation = false; 2698 break; 2699 } 2700 2701 /* setup extra DISPC_WB_ATTRIBUTES */ 2702 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 2703 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ 2704 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ 2705 if (mem_to_mem) 2706 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ 2707 else 2708 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ 2709 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 2710 2711 if (mem_to_mem) { 2712 /* WBDELAYCOUNT */ 2713 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); 2714 } else { 2715 int wbdelay; 2716 2717 wbdelay = min(vm->vfront_porch + 2718 vm->vsync_len + vm->vback_porch, (u32)255); 2719 2720 /* WBDELAYCOUNT */ 2721 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2722 } 2723 2724 return r; 2725 } 2726 2727 static int dispc_ovl_enable(enum omap_plane_id plane, bool enable) 2728 { 2729 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2730 2731 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2732 2733 return 0; 2734 } 2735 2736 static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) 2737 { 2738 return dss_get_supported_outputs(channel); 2739 } 2740 2741 static void dispc_lcd_enable_signal_polarity(bool act_high) 2742 { 2743 if (!dispc_has_feature(FEAT_LCDENABLEPOL)) 2744 return; 2745 2746 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2747 } 2748 2749 void dispc_lcd_enable_signal(bool enable) 2750 { 2751 if (!dispc_has_feature(FEAT_LCDENABLESIGNAL)) 2752 return; 2753 2754 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2755 } 2756 2757 void dispc_pck_free_enable(bool enable) 2758 { 2759 if (!dispc_has_feature(FEAT_PCKFREEENABLE)) 2760 return; 2761 2762 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2763 } 2764 2765 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2766 { 2767 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2768 } 2769 2770 2771 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2772 { 2773 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2774 } 2775 2776 static void dispc_set_loadmode(enum omap_dss_load_mode mode) 2777 { 2778 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2779 } 2780 2781 2782 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) 2783 { 2784 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2785 } 2786 2787 static void dispc_mgr_set_trans_key(enum omap_channel ch, 2788 enum omap_dss_trans_key_type type, 2789 u32 trans_key) 2790 { 2791 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); 2792 2793 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2794 } 2795 2796 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2797 { 2798 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); 2799 } 2800 2801 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2802 bool enable) 2803 { 2804 if (!dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER)) 2805 return; 2806 2807 if (ch == OMAP_DSS_CHANNEL_LCD) 2808 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2809 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2810 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2811 } 2812 2813 static void dispc_mgr_setup(enum omap_channel channel, 2814 const struct omap_overlay_manager_info *info) 2815 { 2816 dispc_mgr_set_default_color(channel, info->default_color); 2817 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); 2818 dispc_mgr_enable_trans_key(channel, info->trans_enabled); 2819 dispc_mgr_enable_alpha_fixed_zorder(channel, 2820 info->partial_alpha_enabled); 2821 if (dispc_has_feature(FEAT_CPR)) { 2822 dispc_mgr_enable_cpr(channel, info->cpr_enable); 2823 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 2824 } 2825 } 2826 2827 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2828 { 2829 int code; 2830 2831 switch (data_lines) { 2832 case 12: 2833 code = 0; 2834 break; 2835 case 16: 2836 code = 1; 2837 break; 2838 case 18: 2839 code = 2; 2840 break; 2841 case 24: 2842 code = 3; 2843 break; 2844 default: 2845 BUG(); 2846 return; 2847 } 2848 2849 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 2850 } 2851 2852 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2853 { 2854 u32 l; 2855 int gpout0, gpout1; 2856 2857 switch (mode) { 2858 case DSS_IO_PAD_MODE_RESET: 2859 gpout0 = 0; 2860 gpout1 = 0; 2861 break; 2862 case DSS_IO_PAD_MODE_RFBI: 2863 gpout0 = 1; 2864 gpout1 = 0; 2865 break; 2866 case DSS_IO_PAD_MODE_BYPASS: 2867 gpout0 = 1; 2868 gpout1 = 1; 2869 break; 2870 default: 2871 BUG(); 2872 return; 2873 } 2874 2875 l = dispc_read_reg(DISPC_CONTROL); 2876 l = FLD_MOD(l, gpout0, 15, 15); 2877 l = FLD_MOD(l, gpout1, 16, 16); 2878 dispc_write_reg(DISPC_CONTROL, l); 2879 } 2880 2881 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2882 { 2883 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 2884 } 2885 2886 static void dispc_mgr_set_lcd_config(enum omap_channel channel, 2887 const struct dss_lcd_mgr_config *config) 2888 { 2889 dispc_mgr_set_io_pad_mode(config->io_pad_mode); 2890 2891 dispc_mgr_enable_stallmode(channel, config->stallmode); 2892 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); 2893 2894 dispc_mgr_set_clock_div(channel, &config->clock_info); 2895 2896 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); 2897 2898 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); 2899 2900 dispc_mgr_set_lcd_type_tft(channel); 2901 } 2902 2903 static bool _dispc_mgr_size_ok(u16 width, u16 height) 2904 { 2905 return width <= dispc.feat->mgr_width_max && 2906 height <= dispc.feat->mgr_height_max; 2907 } 2908 2909 static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp, 2910 int vsw, int vfp, int vbp) 2911 { 2912 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max || 2913 hfp < 1 || hfp > dispc.feat->hp_max || 2914 hbp < 1 || hbp > dispc.feat->hp_max || 2915 vsw < 1 || vsw > dispc.feat->sw_max || 2916 vfp < 0 || vfp > dispc.feat->vp_max || 2917 vbp < 0 || vbp > dispc.feat->vp_max) 2918 return false; 2919 return true; 2920 } 2921 2922 static bool _dispc_mgr_pclk_ok(enum omap_channel channel, 2923 unsigned long pclk) 2924 { 2925 if (dss_mgr_is_lcd(channel)) 2926 return pclk <= dispc.feat->max_lcd_pclk; 2927 else 2928 return pclk <= dispc.feat->max_tv_pclk; 2929 } 2930 2931 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm) 2932 { 2933 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive)) 2934 return false; 2935 2936 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock)) 2937 return false; 2938 2939 if (dss_mgr_is_lcd(channel)) { 2940 /* TODO: OMAP4+ supports interlace for LCD outputs */ 2941 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2942 return false; 2943 2944 if (!_dispc_lcd_timings_ok(vm->hsync_len, 2945 vm->hfront_porch, vm->hback_porch, 2946 vm->vsync_len, vm->vfront_porch, 2947 vm->vback_porch)) 2948 return false; 2949 } 2950 2951 return true; 2952 } 2953 2954 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, 2955 const struct videomode *vm) 2956 { 2957 u32 timing_h, timing_v, l; 2958 bool onoff, rf, ipc, vs, hs, de; 2959 2960 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) | 2961 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) | 2962 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20); 2963 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) | 2964 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) | 2965 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20); 2966 2967 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 2968 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 2969 2970 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH) 2971 vs = false; 2972 else 2973 vs = true; 2974 2975 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH) 2976 hs = false; 2977 else 2978 hs = true; 2979 2980 if (vm->flags & DISPLAY_FLAGS_DE_HIGH) 2981 de = false; 2982 else 2983 de = true; 2984 2985 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 2986 ipc = false; 2987 else 2988 ipc = true; 2989 2990 /* always use the 'rf' setting */ 2991 onoff = true; 2992 2993 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE) 2994 rf = true; 2995 else 2996 rf = false; 2997 2998 l = FLD_VAL(onoff, 17, 17) | 2999 FLD_VAL(rf, 16, 16) | 3000 FLD_VAL(de, 15, 15) | 3001 FLD_VAL(ipc, 14, 14) | 3002 FLD_VAL(hs, 13, 13) | 3003 FLD_VAL(vs, 12, 12); 3004 3005 /* always set ALIGN bit when available */ 3006 if (dispc.feat->supports_sync_align) 3007 l |= (1 << 18); 3008 3009 dispc_write_reg(DISPC_POL_FREQ(channel), l); 3010 3011 if (dispc.syscon_pol) { 3012 const int shifts[] = { 3013 [OMAP_DSS_CHANNEL_LCD] = 0, 3014 [OMAP_DSS_CHANNEL_LCD2] = 1, 3015 [OMAP_DSS_CHANNEL_LCD3] = 2, 3016 }; 3017 3018 u32 mask, val; 3019 3020 mask = (1 << 0) | (1 << 3) | (1 << 6); 3021 val = (rf << 0) | (ipc << 3) | (onoff << 6); 3022 3023 mask <<= 16 + shifts[channel]; 3024 val <<= 16 + shifts[channel]; 3025 3026 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, 3027 mask, val); 3028 } 3029 } 3030 3031 static int vm_flag_to_int(enum display_flags flags, enum display_flags high, 3032 enum display_flags low) 3033 { 3034 if (flags & high) 3035 return 1; 3036 if (flags & low) 3037 return -1; 3038 return 0; 3039 } 3040 3041 /* change name to mode? */ 3042 static void dispc_mgr_set_timings(enum omap_channel channel, 3043 const struct videomode *vm) 3044 { 3045 unsigned xtot, ytot; 3046 unsigned long ht, vt; 3047 struct videomode t = *vm; 3048 3049 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 3050 3051 if (!dispc_mgr_timings_ok(channel, &t)) { 3052 BUG(); 3053 return; 3054 } 3055 3056 if (dss_mgr_is_lcd(channel)) { 3057 _dispc_mgr_set_lcd_timings(channel, &t); 3058 3059 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3060 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 3061 3062 ht = vm->pixelclock / xtot; 3063 vt = vm->pixelclock / xtot / ytot; 3064 3065 DSSDBG("pck %lu\n", vm->pixelclock); 3066 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3067 t.hsync_len, t.hfront_porch, t.hback_porch, 3068 t.vsync_len, t.vfront_porch, t.vback_porch); 3069 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3070 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW), 3071 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW), 3072 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE), 3073 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW), 3074 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE)); 3075 3076 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3077 } else { 3078 if (t.flags & DISPLAY_FLAGS_INTERLACED) 3079 t.vactive /= 2; 3080 3081 if (dispc.feat->supports_double_pixel) 3082 REG_FLD_MOD(DISPC_CONTROL, 3083 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), 3084 19, 17); 3085 } 3086 3087 dispc_mgr_set_size(channel, t.hactive, t.vactive); 3088 } 3089 3090 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 3091 u16 pck_div) 3092 { 3093 BUG_ON(lck_div < 1); 3094 BUG_ON(pck_div < 1); 3095 3096 dispc_write_reg(DISPC_DIVISORo(channel), 3097 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3098 3099 if (!dispc_has_feature(FEAT_CORE_CLK_DIV) && 3100 channel == OMAP_DSS_CHANNEL_LCD) 3101 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; 3102 } 3103 3104 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, 3105 int *pck_div) 3106 { 3107 u32 l; 3108 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3109 *lck_div = FLD_GET(l, 23, 16); 3110 *pck_div = FLD_GET(l, 7, 0); 3111 } 3112 3113 static unsigned long dispc_fclk_rate(void) 3114 { 3115 unsigned long r; 3116 enum dss_clk_source src; 3117 3118 src = dss_get_dispc_clk_source(); 3119 3120 if (src == DSS_CLK_SRC_FCK) { 3121 r = dss_get_dispc_clk_rate(); 3122 } else { 3123 struct dss_pll *pll; 3124 unsigned clkout_idx; 3125 3126 pll = dss_pll_find_by_src(src); 3127 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3128 3129 r = pll->cinfo.clkout[clkout_idx]; 3130 } 3131 3132 return r; 3133 } 3134 3135 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3136 { 3137 int lcd; 3138 unsigned long r; 3139 enum dss_clk_source src; 3140 3141 /* for TV, LCLK rate is the FCLK rate */ 3142 if (!dss_mgr_is_lcd(channel)) 3143 return dispc_fclk_rate(); 3144 3145 src = dss_get_lcd_clk_source(channel); 3146 3147 if (src == DSS_CLK_SRC_FCK) { 3148 r = dss_get_dispc_clk_rate(); 3149 } else { 3150 struct dss_pll *pll; 3151 unsigned clkout_idx; 3152 3153 pll = dss_pll_find_by_src(src); 3154 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3155 3156 r = pll->cinfo.clkout[clkout_idx]; 3157 } 3158 3159 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3160 3161 return r / lcd; 3162 } 3163 3164 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) 3165 { 3166 unsigned long r; 3167 3168 if (dss_mgr_is_lcd(channel)) { 3169 int pcd; 3170 u32 l; 3171 3172 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3173 3174 pcd = FLD_GET(l, 7, 0); 3175 3176 r = dispc_mgr_lclk_rate(channel); 3177 3178 return r / pcd; 3179 } else { 3180 return dispc.tv_pclk_rate; 3181 } 3182 } 3183 3184 void dispc_set_tv_pclk(unsigned long pclk) 3185 { 3186 dispc.tv_pclk_rate = pclk; 3187 } 3188 3189 static unsigned long dispc_core_clk_rate(void) 3190 { 3191 return dispc.core_clk_rate; 3192 } 3193 3194 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane) 3195 { 3196 enum omap_channel channel; 3197 3198 if (plane == OMAP_DSS_WB) 3199 return 0; 3200 3201 channel = dispc_ovl_get_channel_out(plane); 3202 3203 return dispc_mgr_pclk_rate(channel); 3204 } 3205 3206 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane) 3207 { 3208 enum omap_channel channel; 3209 3210 if (plane == OMAP_DSS_WB) 3211 return 0; 3212 3213 channel = dispc_ovl_get_channel_out(plane); 3214 3215 return dispc_mgr_lclk_rate(channel); 3216 } 3217 3218 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3219 { 3220 int lcd, pcd; 3221 enum dss_clk_source lcd_clk_src; 3222 3223 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3224 3225 lcd_clk_src = dss_get_lcd_clk_source(channel); 3226 3227 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3228 dss_get_clk_source_name(lcd_clk_src)); 3229 3230 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3231 3232 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3233 dispc_mgr_lclk_rate(channel), lcd); 3234 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3235 dispc_mgr_pclk_rate(channel), pcd); 3236 } 3237 3238 void dispc_dump_clocks(struct seq_file *s) 3239 { 3240 int lcd; 3241 u32 l; 3242 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3243 3244 if (dispc_runtime_get()) 3245 return; 3246 3247 seq_printf(s, "- DISPC -\n"); 3248 3249 seq_printf(s, "dispc fclk source = %s\n", 3250 dss_get_clk_source_name(dispc_clk_src)); 3251 3252 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3253 3254 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { 3255 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3256 l = dispc_read_reg(DISPC_DIVISOR); 3257 lcd = FLD_GET(l, 23, 16); 3258 3259 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3260 (dispc_fclk_rate()/lcd), lcd); 3261 } 3262 3263 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); 3264 3265 if (dispc_has_feature(FEAT_MGR_LCD2)) 3266 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); 3267 if (dispc_has_feature(FEAT_MGR_LCD3)) 3268 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); 3269 3270 dispc_runtime_put(); 3271 } 3272 3273 static void dispc_dump_regs(struct seq_file *s) 3274 { 3275 int i, j; 3276 const char *mgr_names[] = { 3277 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3278 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3279 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3280 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3281 }; 3282 const char *ovl_names[] = { 3283 [OMAP_DSS_GFX] = "GFX", 3284 [OMAP_DSS_VIDEO1] = "VID1", 3285 [OMAP_DSS_VIDEO2] = "VID2", 3286 [OMAP_DSS_VIDEO3] = "VID3", 3287 [OMAP_DSS_WB] = "WB", 3288 }; 3289 const char **p_names; 3290 3291 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) 3292 3293 if (dispc_runtime_get()) 3294 return; 3295 3296 /* DISPC common registers */ 3297 DUMPREG(DISPC_REVISION); 3298 DUMPREG(DISPC_SYSCONFIG); 3299 DUMPREG(DISPC_SYSSTATUS); 3300 DUMPREG(DISPC_IRQSTATUS); 3301 DUMPREG(DISPC_IRQENABLE); 3302 DUMPREG(DISPC_CONTROL); 3303 DUMPREG(DISPC_CONFIG); 3304 DUMPREG(DISPC_CAPABLE); 3305 DUMPREG(DISPC_LINE_STATUS); 3306 DUMPREG(DISPC_LINE_NUMBER); 3307 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 3308 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 3309 DUMPREG(DISPC_GLOBAL_ALPHA); 3310 if (dispc_has_feature(FEAT_MGR_LCD2)) { 3311 DUMPREG(DISPC_CONTROL2); 3312 DUMPREG(DISPC_CONFIG2); 3313 } 3314 if (dispc_has_feature(FEAT_MGR_LCD3)) { 3315 DUMPREG(DISPC_CONTROL3); 3316 DUMPREG(DISPC_CONFIG3); 3317 } 3318 if (dispc_has_feature(FEAT_MFLAG)) 3319 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3320 3321 #undef DUMPREG 3322 3323 #define DISPC_REG(i, name) name(i) 3324 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3325 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3326 dispc_read_reg(DISPC_REG(i, r))) 3327 3328 p_names = mgr_names; 3329 3330 /* DISPC channel specific registers */ 3331 for (i = 0; i < dispc_get_num_mgrs(); i++) { 3332 DUMPREG(i, DISPC_DEFAULT_COLOR); 3333 DUMPREG(i, DISPC_TRANS_COLOR); 3334 DUMPREG(i, DISPC_SIZE_MGR); 3335 3336 if (i == OMAP_DSS_CHANNEL_DIGIT) 3337 continue; 3338 3339 DUMPREG(i, DISPC_TIMING_H); 3340 DUMPREG(i, DISPC_TIMING_V); 3341 DUMPREG(i, DISPC_POL_FREQ); 3342 DUMPREG(i, DISPC_DIVISORo); 3343 3344 DUMPREG(i, DISPC_DATA_CYCLE1); 3345 DUMPREG(i, DISPC_DATA_CYCLE2); 3346 DUMPREG(i, DISPC_DATA_CYCLE3); 3347 3348 if (dispc_has_feature(FEAT_CPR)) { 3349 DUMPREG(i, DISPC_CPR_COEF_R); 3350 DUMPREG(i, DISPC_CPR_COEF_G); 3351 DUMPREG(i, DISPC_CPR_COEF_B); 3352 } 3353 } 3354 3355 p_names = ovl_names; 3356 3357 for (i = 0; i < dispc_get_num_ovls(); i++) { 3358 DUMPREG(i, DISPC_OVL_BA0); 3359 DUMPREG(i, DISPC_OVL_BA1); 3360 DUMPREG(i, DISPC_OVL_POSITION); 3361 DUMPREG(i, DISPC_OVL_SIZE); 3362 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3363 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3364 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3365 DUMPREG(i, DISPC_OVL_ROW_INC); 3366 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3367 3368 if (dispc_has_feature(FEAT_PRELOAD)) 3369 DUMPREG(i, DISPC_OVL_PRELOAD); 3370 if (dispc_has_feature(FEAT_MFLAG)) 3371 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3372 3373 if (i == OMAP_DSS_GFX) { 3374 DUMPREG(i, DISPC_OVL_WINDOW_SKIP); 3375 DUMPREG(i, DISPC_OVL_TABLE_BA); 3376 continue; 3377 } 3378 3379 DUMPREG(i, DISPC_OVL_FIR); 3380 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3381 DUMPREG(i, DISPC_OVL_ACCU0); 3382 DUMPREG(i, DISPC_OVL_ACCU1); 3383 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3384 DUMPREG(i, DISPC_OVL_BA0_UV); 3385 DUMPREG(i, DISPC_OVL_BA1_UV); 3386 DUMPREG(i, DISPC_OVL_FIR2); 3387 DUMPREG(i, DISPC_OVL_ACCU2_0); 3388 DUMPREG(i, DISPC_OVL_ACCU2_1); 3389 } 3390 if (dispc_has_feature(FEAT_ATTR2)) 3391 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3392 } 3393 3394 if (dispc.feat->has_writeback) { 3395 i = OMAP_DSS_WB; 3396 DUMPREG(i, DISPC_OVL_BA0); 3397 DUMPREG(i, DISPC_OVL_BA1); 3398 DUMPREG(i, DISPC_OVL_SIZE); 3399 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3400 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3401 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3402 DUMPREG(i, DISPC_OVL_ROW_INC); 3403 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3404 3405 if (dispc_has_feature(FEAT_MFLAG)) 3406 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3407 3408 DUMPREG(i, DISPC_OVL_FIR); 3409 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3410 DUMPREG(i, DISPC_OVL_ACCU0); 3411 DUMPREG(i, DISPC_OVL_ACCU1); 3412 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3413 DUMPREG(i, DISPC_OVL_BA0_UV); 3414 DUMPREG(i, DISPC_OVL_BA1_UV); 3415 DUMPREG(i, DISPC_OVL_FIR2); 3416 DUMPREG(i, DISPC_OVL_ACCU2_0); 3417 DUMPREG(i, DISPC_OVL_ACCU2_1); 3418 } 3419 if (dispc_has_feature(FEAT_ATTR2)) 3420 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3421 } 3422 3423 #undef DISPC_REG 3424 #undef DUMPREG 3425 3426 #define DISPC_REG(plane, name, i) name(plane, i) 3427 #define DUMPREG(plane, name, i) \ 3428 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3429 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3430 dispc_read_reg(DISPC_REG(plane, name, i))) 3431 3432 /* Video pipeline coefficient registers */ 3433 3434 /* start from OMAP_DSS_VIDEO1 */ 3435 for (i = 1; i < dispc_get_num_ovls(); i++) { 3436 for (j = 0; j < 8; j++) 3437 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); 3438 3439 for (j = 0; j < 8; j++) 3440 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); 3441 3442 for (j = 0; j < 5; j++) 3443 DUMPREG(i, DISPC_OVL_CONV_COEF, j); 3444 3445 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 3446 for (j = 0; j < 8; j++) 3447 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); 3448 } 3449 3450 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3451 for (j = 0; j < 8; j++) 3452 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); 3453 3454 for (j = 0; j < 8; j++) 3455 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); 3456 3457 for (j = 0; j < 8; j++) 3458 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); 3459 } 3460 } 3461 3462 dispc_runtime_put(); 3463 3464 #undef DISPC_REG 3465 #undef DUMPREG 3466 } 3467 3468 /* calculate clock rates using dividers in cinfo */ 3469 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3470 struct dispc_clock_info *cinfo) 3471 { 3472 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3473 return -EINVAL; 3474 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3475 return -EINVAL; 3476 3477 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3478 cinfo->pck = cinfo->lck / cinfo->pck_div; 3479 3480 return 0; 3481 } 3482 3483 bool dispc_div_calc(unsigned long dispc_freq, 3484 unsigned long pck_min, unsigned long pck_max, 3485 dispc_div_calc_func func, void *data) 3486 { 3487 int lckd, lckd_start, lckd_stop; 3488 int pckd, pckd_start, pckd_stop; 3489 unsigned long pck, lck; 3490 unsigned long lck_max; 3491 unsigned long pckd_hw_min, pckd_hw_max; 3492 unsigned min_fck_per_pck; 3493 unsigned long fck; 3494 3495 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK 3496 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; 3497 #else 3498 min_fck_per_pck = 0; 3499 #endif 3500 3501 pckd_hw_min = dispc.feat->min_pcd; 3502 pckd_hw_max = 255; 3503 3504 lck_max = dss_get_max_fck_rate(); 3505 3506 pck_min = pck_min ? pck_min : 1; 3507 pck_max = pck_max ? pck_max : ULONG_MAX; 3508 3509 lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul); 3510 lckd_stop = min(dispc_freq / pck_min, 255ul); 3511 3512 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3513 lck = dispc_freq / lckd; 3514 3515 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3516 pckd_stop = min(lck / pck_min, pckd_hw_max); 3517 3518 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3519 pck = lck / pckd; 3520 3521 /* 3522 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3523 * clock, which means we're configuring DISPC fclk here 3524 * also. Thus we need to use the calculated lck. For 3525 * OMAP4+ the DISPC fclk is a separate clock. 3526 */ 3527 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 3528 fck = dispc_core_clk_rate(); 3529 else 3530 fck = lck; 3531 3532 if (fck < pck * min_fck_per_pck) 3533 continue; 3534 3535 if (func(lckd, pckd, lck, pck, data)) 3536 return true; 3537 } 3538 } 3539 3540 return false; 3541 } 3542 3543 void dispc_mgr_set_clock_div(enum omap_channel channel, 3544 const struct dispc_clock_info *cinfo) 3545 { 3546 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3547 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3548 3549 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); 3550 } 3551 3552 int dispc_mgr_get_clock_div(enum omap_channel channel, 3553 struct dispc_clock_info *cinfo) 3554 { 3555 unsigned long fck; 3556 3557 fck = dispc_fclk_rate(); 3558 3559 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3560 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); 3561 3562 cinfo->lck = fck / cinfo->lck_div; 3563 cinfo->pck = cinfo->lck / cinfo->pck_div; 3564 3565 return 0; 3566 } 3567 3568 static u32 dispc_read_irqstatus(void) 3569 { 3570 return dispc_read_reg(DISPC_IRQSTATUS); 3571 } 3572 3573 static void dispc_clear_irqstatus(u32 mask) 3574 { 3575 dispc_write_reg(DISPC_IRQSTATUS, mask); 3576 } 3577 3578 static void dispc_write_irqenable(u32 mask) 3579 { 3580 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3581 3582 /* clear the irqstatus for newly enabled irqs */ 3583 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3584 3585 dispc_write_reg(DISPC_IRQENABLE, mask); 3586 3587 /* flush posted write */ 3588 dispc_read_reg(DISPC_IRQENABLE); 3589 } 3590 3591 void dispc_enable_sidle(void) 3592 { 3593 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ 3594 } 3595 3596 void dispc_disable_sidle(void) 3597 { 3598 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3599 } 3600 3601 static u32 dispc_mgr_gamma_size(enum omap_channel channel) 3602 { 3603 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3604 3605 if (!dispc.feat->has_gamma_table) 3606 return 0; 3607 3608 return gdesc->len; 3609 } 3610 3611 static void dispc_mgr_write_gamma_table(enum omap_channel channel) 3612 { 3613 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3614 u32 *table = dispc.gamma_table[channel]; 3615 unsigned int i; 3616 3617 DSSDBG("%s: channel %d\n", __func__, channel); 3618 3619 for (i = 0; i < gdesc->len; ++i) { 3620 u32 v = table[i]; 3621 3622 if (gdesc->has_index) 3623 v |= i << 24; 3624 else if (i == 0) 3625 v |= 1 << 31; 3626 3627 dispc_write_reg(gdesc->reg, v); 3628 } 3629 } 3630 3631 static void dispc_restore_gamma_tables(void) 3632 { 3633 DSSDBG("%s()\n", __func__); 3634 3635 if (!dispc.feat->has_gamma_table) 3636 return; 3637 3638 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD); 3639 3640 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT); 3641 3642 if (dispc_has_feature(FEAT_MGR_LCD2)) 3643 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2); 3644 3645 if (dispc_has_feature(FEAT_MGR_LCD3)) 3646 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3); 3647 } 3648 3649 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 3650 { .red = 0, .green = 0, .blue = 0, }, 3651 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 3652 }; 3653 3654 static void dispc_mgr_set_gamma(enum omap_channel channel, 3655 const struct drm_color_lut *lut, 3656 unsigned int length) 3657 { 3658 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3659 u32 *table = dispc.gamma_table[channel]; 3660 uint i; 3661 3662 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__, 3663 channel, length, gdesc->len); 3664 3665 if (!dispc.feat->has_gamma_table) 3666 return; 3667 3668 if (lut == NULL || length < 2) { 3669 lut = dispc_mgr_gamma_default_lut; 3670 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut); 3671 } 3672 3673 for (i = 0; i < length - 1; ++i) { 3674 uint first = i * (gdesc->len - 1) / (length - 1); 3675 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); 3676 uint w = last - first; 3677 u16 r, g, b; 3678 uint j; 3679 3680 if (w == 0) 3681 continue; 3682 3683 for (j = 0; j <= w; j++) { 3684 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; 3685 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; 3686 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; 3687 3688 r >>= 16 - gdesc->bits; 3689 g >>= 16 - gdesc->bits; 3690 b >>= 16 - gdesc->bits; 3691 3692 table[first + j] = (r << (gdesc->bits * 2)) | 3693 (g << gdesc->bits) | b; 3694 } 3695 } 3696 3697 if (dispc.is_enabled) 3698 dispc_mgr_write_gamma_table(channel); 3699 } 3700 3701 static int dispc_init_gamma_tables(void) 3702 { 3703 int channel; 3704 3705 if (!dispc.feat->has_gamma_table) 3706 return 0; 3707 3708 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) { 3709 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3710 u32 *gt; 3711 3712 if (channel == OMAP_DSS_CHANNEL_LCD2 && 3713 !dispc_has_feature(FEAT_MGR_LCD2)) 3714 continue; 3715 3716 if (channel == OMAP_DSS_CHANNEL_LCD3 && 3717 !dispc_has_feature(FEAT_MGR_LCD3)) 3718 continue; 3719 3720 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len, 3721 sizeof(u32), GFP_KERNEL); 3722 if (!gt) 3723 return -ENOMEM; 3724 3725 dispc.gamma_table[channel] = gt; 3726 3727 dispc_mgr_set_gamma(channel, NULL, 0); 3728 } 3729 return 0; 3730 } 3731 3732 static void _omap_dispc_initial_config(void) 3733 { 3734 u32 l; 3735 3736 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3737 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { 3738 l = dispc_read_reg(DISPC_DIVISOR); 3739 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3740 l = FLD_MOD(l, 1, 0, 0); 3741 l = FLD_MOD(l, 1, 23, 16); 3742 dispc_write_reg(DISPC_DIVISOR, l); 3743 3744 dispc.core_clk_rate = dispc_fclk_rate(); 3745 } 3746 3747 /* Use gamma table mode, instead of palette mode */ 3748 if (dispc.feat->has_gamma_table) 3749 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3); 3750 3751 /* For older DSS versions (FEAT_FUNCGATED) this enables 3752 * func-clock auto-gating. For newer versions 3753 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables. 3754 */ 3755 if (dispc_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) 3756 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3757 3758 dispc_setup_color_conv_coef(); 3759 3760 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3761 3762 dispc_init_fifos(); 3763 3764 dispc_configure_burst_sizes(); 3765 3766 dispc_ovl_enable_zorder_planes(); 3767 3768 if (dispc.feat->mstandby_workaround) 3769 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3770 3771 if (dispc_has_feature(FEAT_MFLAG)) 3772 dispc_init_mflag(); 3773 } 3774 3775 static const enum dispc_feature_id omap2_dispc_features_list[] = { 3776 FEAT_LCDENABLEPOL, 3777 FEAT_LCDENABLESIGNAL, 3778 FEAT_PCKFREEENABLE, 3779 FEAT_FUNCGATED, 3780 FEAT_ROWREPEATENABLE, 3781 FEAT_RESIZECONF, 3782 }; 3783 3784 static const enum dispc_feature_id omap3_dispc_features_list[] = { 3785 FEAT_LCDENABLEPOL, 3786 FEAT_LCDENABLESIGNAL, 3787 FEAT_PCKFREEENABLE, 3788 FEAT_FUNCGATED, 3789 FEAT_LINEBUFFERSPLIT, 3790 FEAT_ROWREPEATENABLE, 3791 FEAT_RESIZECONF, 3792 FEAT_CPR, 3793 FEAT_PRELOAD, 3794 FEAT_FIR_COEF_V, 3795 FEAT_ALPHA_FIXED_ZORDER, 3796 FEAT_FIFO_MERGE, 3797 FEAT_OMAP3_DSI_FIFO_BUG, 3798 }; 3799 3800 static const enum dispc_feature_id am43xx_dispc_features_list[] = { 3801 FEAT_LCDENABLEPOL, 3802 FEAT_LCDENABLESIGNAL, 3803 FEAT_PCKFREEENABLE, 3804 FEAT_FUNCGATED, 3805 FEAT_LINEBUFFERSPLIT, 3806 FEAT_ROWREPEATENABLE, 3807 FEAT_RESIZECONF, 3808 FEAT_CPR, 3809 FEAT_PRELOAD, 3810 FEAT_FIR_COEF_V, 3811 FEAT_ALPHA_FIXED_ZORDER, 3812 FEAT_FIFO_MERGE, 3813 }; 3814 3815 static const enum dispc_feature_id omap4_dispc_features_list[] = { 3816 FEAT_MGR_LCD2, 3817 FEAT_CORE_CLK_DIV, 3818 FEAT_HANDLE_UV_SEPARATE, 3819 FEAT_ATTR2, 3820 FEAT_CPR, 3821 FEAT_PRELOAD, 3822 FEAT_FIR_COEF_V, 3823 FEAT_ALPHA_FREE_ZORDER, 3824 FEAT_FIFO_MERGE, 3825 FEAT_BURST_2D, 3826 }; 3827 3828 static const enum dispc_feature_id omap5_dispc_features_list[] = { 3829 FEAT_MGR_LCD2, 3830 FEAT_MGR_LCD3, 3831 FEAT_CORE_CLK_DIV, 3832 FEAT_HANDLE_UV_SEPARATE, 3833 FEAT_ATTR2, 3834 FEAT_CPR, 3835 FEAT_PRELOAD, 3836 FEAT_FIR_COEF_V, 3837 FEAT_ALPHA_FREE_ZORDER, 3838 FEAT_FIFO_MERGE, 3839 FEAT_BURST_2D, 3840 FEAT_MFLAG, 3841 }; 3842 3843 static const struct dss_reg_field omap2_dispc_reg_fields[] = { 3844 [FEAT_REG_FIRHINC] = { 11, 0 }, 3845 [FEAT_REG_FIRVINC] = { 27, 16 }, 3846 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, 3847 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, 3848 [FEAT_REG_FIFOSIZE] = { 8, 0 }, 3849 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 3850 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 3851 }; 3852 3853 static const struct dss_reg_field omap3_dispc_reg_fields[] = { 3854 [FEAT_REG_FIRHINC] = { 12, 0 }, 3855 [FEAT_REG_FIRVINC] = { 28, 16 }, 3856 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, 3857 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, 3858 [FEAT_REG_FIFOSIZE] = { 10, 0 }, 3859 [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, 3860 [FEAT_REG_VERTICALACCU] = { 25, 16 }, 3861 }; 3862 3863 static const struct dss_reg_field omap4_dispc_reg_fields[] = { 3864 [FEAT_REG_FIRHINC] = { 12, 0 }, 3865 [FEAT_REG_FIRVINC] = { 28, 16 }, 3866 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, 3867 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, 3868 [FEAT_REG_FIFOSIZE] = { 15, 0 }, 3869 [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, 3870 [FEAT_REG_VERTICALACCU] = { 26, 16 }, 3871 }; 3872 3873 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { 3874 /* OMAP_DSS_GFX */ 3875 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3876 3877 /* OMAP_DSS_VIDEO1 */ 3878 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 3879 OMAP_DSS_OVL_CAP_REPLICATION, 3880 3881 /* OMAP_DSS_VIDEO2 */ 3882 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 3883 OMAP_DSS_OVL_CAP_REPLICATION, 3884 }; 3885 3886 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = { 3887 /* OMAP_DSS_GFX */ 3888 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | 3889 OMAP_DSS_OVL_CAP_REPLICATION, 3890 3891 /* OMAP_DSS_VIDEO1 */ 3892 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 3893 OMAP_DSS_OVL_CAP_REPLICATION, 3894 3895 /* OMAP_DSS_VIDEO2 */ 3896 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 3897 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3898 }; 3899 3900 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = { 3901 /* OMAP_DSS_GFX */ 3902 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 3903 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3904 3905 /* OMAP_DSS_VIDEO1 */ 3906 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | 3907 OMAP_DSS_OVL_CAP_REPLICATION, 3908 3909 /* OMAP_DSS_VIDEO2 */ 3910 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 3911 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | 3912 OMAP_DSS_OVL_CAP_REPLICATION, 3913 }; 3914 3915 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = { 3916 /* OMAP_DSS_GFX */ 3917 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | 3918 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | 3919 OMAP_DSS_OVL_CAP_REPLICATION, 3920 3921 /* OMAP_DSS_VIDEO1 */ 3922 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 3923 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 3924 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3925 3926 /* OMAP_DSS_VIDEO2 */ 3927 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 3928 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 3929 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3930 3931 /* OMAP_DSS_VIDEO3 */ 3932 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | 3933 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | 3934 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 3935 }; 3936 3937 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } 3938 3939 static const u32 *omap2_dispc_supported_color_modes[] = { 3940 3941 /* OMAP_DSS_GFX */ 3942 COLOR_ARRAY( 3943 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 3944 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), 3945 3946 /* OMAP_DSS_VIDEO1 */ 3947 COLOR_ARRAY( 3948 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 3949 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 3950 DRM_FORMAT_UYVY), 3951 3952 /* OMAP_DSS_VIDEO2 */ 3953 COLOR_ARRAY( 3954 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 3955 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 3956 DRM_FORMAT_UYVY), 3957 }; 3958 3959 static const u32 *omap3_dispc_supported_color_modes[] = { 3960 /* OMAP_DSS_GFX */ 3961 COLOR_ARRAY( 3962 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 3963 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 3964 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 3965 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 3966 3967 /* OMAP_DSS_VIDEO1 */ 3968 COLOR_ARRAY( 3969 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, 3970 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, 3971 DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), 3972 3973 /* OMAP_DSS_VIDEO2 */ 3974 COLOR_ARRAY( 3975 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 3976 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 3977 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, 3978 DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, 3979 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), 3980 }; 3981 3982 static const u32 *omap4_dispc_supported_color_modes[] = { 3983 /* OMAP_DSS_GFX */ 3984 COLOR_ARRAY( 3985 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, 3986 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 3987 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, 3988 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, 3989 DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, 3990 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), 3991 3992 /* OMAP_DSS_VIDEO1 */ 3993 COLOR_ARRAY( 3994 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 3995 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 3996 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 3997 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 3998 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 3999 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4000 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4001 DRM_FORMAT_RGBX8888), 4002 4003 /* OMAP_DSS_VIDEO2 */ 4004 COLOR_ARRAY( 4005 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4006 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4007 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4008 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4009 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4010 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4011 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4012 DRM_FORMAT_RGBX8888), 4013 4014 /* OMAP_DSS_VIDEO3 */ 4015 COLOR_ARRAY( 4016 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4017 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4018 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4019 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4020 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4021 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4022 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4023 DRM_FORMAT_RGBX8888), 4024 4025 /* OMAP_DSS_WB */ 4026 COLOR_ARRAY( 4027 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, 4028 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, 4029 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, 4030 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, 4031 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, 4032 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, 4033 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, 4034 DRM_FORMAT_RGBX8888), 4035 }; 4036 4037 static const struct dispc_features omap24xx_dispc_feats = { 4038 .sw_start = 5, 4039 .fp_start = 15, 4040 .bp_start = 27, 4041 .sw_max = 64, 4042 .vp_max = 255, 4043 .hp_max = 256, 4044 .mgr_width_start = 10, 4045 .mgr_height_start = 26, 4046 .mgr_width_max = 2048, 4047 .mgr_height_max = 2048, 4048 .max_lcd_pclk = 66500000, 4049 .max_downscale = 2, 4050 /* 4051 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler 4052 * cannot scale an image width larger than 768. 4053 */ 4054 .max_line_width = 768, 4055 .min_pcd = 2, 4056 .calc_scaling = dispc_ovl_calc_scaling_24xx, 4057 .calc_core_clk = calc_core_clk_24xx, 4058 .num_fifos = 3, 4059 .features = omap2_dispc_features_list, 4060 .num_features = ARRAY_SIZE(omap2_dispc_features_list), 4061 .reg_fields = omap2_dispc_reg_fields, 4062 .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields), 4063 .overlay_caps = omap2_dispc_overlay_caps, 4064 .supported_color_modes = omap2_dispc_supported_color_modes, 4065 .num_mgrs = 2, 4066 .num_ovls = 3, 4067 .buffer_size_unit = 1, 4068 .burst_size_unit = 8, 4069 .no_framedone_tv = true, 4070 .set_max_preload = false, 4071 .last_pixel_inc_missing = true, 4072 }; 4073 4074 static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 4075 .sw_start = 5, 4076 .fp_start = 15, 4077 .bp_start = 27, 4078 .sw_max = 64, 4079 .vp_max = 255, 4080 .hp_max = 256, 4081 .mgr_width_start = 10, 4082 .mgr_height_start = 26, 4083 .mgr_width_max = 2048, 4084 .mgr_height_max = 2048, 4085 .max_lcd_pclk = 173000000, 4086 .max_tv_pclk = 59000000, 4087 .max_downscale = 4, 4088 .max_line_width = 1024, 4089 .min_pcd = 1, 4090 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4091 .calc_core_clk = calc_core_clk_34xx, 4092 .num_fifos = 3, 4093 .features = omap3_dispc_features_list, 4094 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4095 .reg_fields = omap3_dispc_reg_fields, 4096 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4097 .overlay_caps = omap3430_dispc_overlay_caps, 4098 .supported_color_modes = omap3_dispc_supported_color_modes, 4099 .num_mgrs = 2, 4100 .num_ovls = 3, 4101 .buffer_size_unit = 1, 4102 .burst_size_unit = 8, 4103 .no_framedone_tv = true, 4104 .set_max_preload = false, 4105 .last_pixel_inc_missing = true, 4106 }; 4107 4108 static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 4109 .sw_start = 7, 4110 .fp_start = 19, 4111 .bp_start = 31, 4112 .sw_max = 256, 4113 .vp_max = 4095, 4114 .hp_max = 4096, 4115 .mgr_width_start = 10, 4116 .mgr_height_start = 26, 4117 .mgr_width_max = 2048, 4118 .mgr_height_max = 2048, 4119 .max_lcd_pclk = 173000000, 4120 .max_tv_pclk = 59000000, 4121 .max_downscale = 4, 4122 .max_line_width = 1024, 4123 .min_pcd = 1, 4124 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4125 .calc_core_clk = calc_core_clk_34xx, 4126 .num_fifos = 3, 4127 .features = omap3_dispc_features_list, 4128 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4129 .reg_fields = omap3_dispc_reg_fields, 4130 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4131 .overlay_caps = omap3430_dispc_overlay_caps, 4132 .supported_color_modes = omap3_dispc_supported_color_modes, 4133 .num_mgrs = 2, 4134 .num_ovls = 3, 4135 .buffer_size_unit = 1, 4136 .burst_size_unit = 8, 4137 .no_framedone_tv = true, 4138 .set_max_preload = false, 4139 .last_pixel_inc_missing = true, 4140 }; 4141 4142 static const struct dispc_features omap36xx_dispc_feats = { 4143 .sw_start = 7, 4144 .fp_start = 19, 4145 .bp_start = 31, 4146 .sw_max = 256, 4147 .vp_max = 4095, 4148 .hp_max = 4096, 4149 .mgr_width_start = 10, 4150 .mgr_height_start = 26, 4151 .mgr_width_max = 2048, 4152 .mgr_height_max = 2048, 4153 .max_lcd_pclk = 173000000, 4154 .max_tv_pclk = 59000000, 4155 .max_downscale = 4, 4156 .max_line_width = 1024, 4157 .min_pcd = 1, 4158 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4159 .calc_core_clk = calc_core_clk_34xx, 4160 .num_fifos = 3, 4161 .features = omap3_dispc_features_list, 4162 .num_features = ARRAY_SIZE(omap3_dispc_features_list), 4163 .reg_fields = omap3_dispc_reg_fields, 4164 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4165 .overlay_caps = omap3630_dispc_overlay_caps, 4166 .supported_color_modes = omap3_dispc_supported_color_modes, 4167 .num_mgrs = 2, 4168 .num_ovls = 3, 4169 .buffer_size_unit = 1, 4170 .burst_size_unit = 8, 4171 .no_framedone_tv = true, 4172 .set_max_preload = false, 4173 .last_pixel_inc_missing = true, 4174 }; 4175 4176 static const struct dispc_features am43xx_dispc_feats = { 4177 .sw_start = 7, 4178 .fp_start = 19, 4179 .bp_start = 31, 4180 .sw_max = 256, 4181 .vp_max = 4095, 4182 .hp_max = 4096, 4183 .mgr_width_start = 10, 4184 .mgr_height_start = 26, 4185 .mgr_width_max = 2048, 4186 .mgr_height_max = 2048, 4187 .max_lcd_pclk = 173000000, 4188 .max_tv_pclk = 59000000, 4189 .max_downscale = 4, 4190 .max_line_width = 1024, 4191 .min_pcd = 1, 4192 .calc_scaling = dispc_ovl_calc_scaling_34xx, 4193 .calc_core_clk = calc_core_clk_34xx, 4194 .num_fifos = 3, 4195 .features = am43xx_dispc_features_list, 4196 .num_features = ARRAY_SIZE(am43xx_dispc_features_list), 4197 .reg_fields = omap3_dispc_reg_fields, 4198 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), 4199 .overlay_caps = omap3430_dispc_overlay_caps, 4200 .supported_color_modes = omap3_dispc_supported_color_modes, 4201 .num_mgrs = 1, 4202 .num_ovls = 3, 4203 .buffer_size_unit = 1, 4204 .burst_size_unit = 8, 4205 .no_framedone_tv = true, 4206 .set_max_preload = false, 4207 .last_pixel_inc_missing = true, 4208 }; 4209 4210 static const struct dispc_features omap44xx_dispc_feats = { 4211 .sw_start = 7, 4212 .fp_start = 19, 4213 .bp_start = 31, 4214 .sw_max = 256, 4215 .vp_max = 4095, 4216 .hp_max = 4096, 4217 .mgr_width_start = 10, 4218 .mgr_height_start = 26, 4219 .mgr_width_max = 2048, 4220 .mgr_height_max = 2048, 4221 .max_lcd_pclk = 170000000, 4222 .max_tv_pclk = 185625000, 4223 .max_downscale = 4, 4224 .max_line_width = 2048, 4225 .min_pcd = 1, 4226 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4227 .calc_core_clk = calc_core_clk_44xx, 4228 .num_fifos = 5, 4229 .features = omap4_dispc_features_list, 4230 .num_features = ARRAY_SIZE(omap4_dispc_features_list), 4231 .reg_fields = omap4_dispc_reg_fields, 4232 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4233 .overlay_caps = omap4_dispc_overlay_caps, 4234 .supported_color_modes = omap4_dispc_supported_color_modes, 4235 .num_mgrs = 3, 4236 .num_ovls = 4, 4237 .buffer_size_unit = 16, 4238 .burst_size_unit = 16, 4239 .gfx_fifo_workaround = true, 4240 .set_max_preload = true, 4241 .supports_sync_align = true, 4242 .has_writeback = true, 4243 .supports_double_pixel = true, 4244 .reverse_ilace_field_order = true, 4245 .has_gamma_table = true, 4246 .has_gamma_i734_bug = true, 4247 }; 4248 4249 static const struct dispc_features omap54xx_dispc_feats = { 4250 .sw_start = 7, 4251 .fp_start = 19, 4252 .bp_start = 31, 4253 .sw_max = 256, 4254 .vp_max = 4095, 4255 .hp_max = 4096, 4256 .mgr_width_start = 11, 4257 .mgr_height_start = 27, 4258 .mgr_width_max = 4096, 4259 .mgr_height_max = 4096, 4260 .max_lcd_pclk = 170000000, 4261 .max_tv_pclk = 186000000, 4262 .max_downscale = 4, 4263 .max_line_width = 2048, 4264 .min_pcd = 1, 4265 .calc_scaling = dispc_ovl_calc_scaling_44xx, 4266 .calc_core_clk = calc_core_clk_44xx, 4267 .num_fifos = 5, 4268 .features = omap5_dispc_features_list, 4269 .num_features = ARRAY_SIZE(omap5_dispc_features_list), 4270 .reg_fields = omap4_dispc_reg_fields, 4271 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), 4272 .overlay_caps = omap4_dispc_overlay_caps, 4273 .supported_color_modes = omap4_dispc_supported_color_modes, 4274 .num_mgrs = 4, 4275 .num_ovls = 4, 4276 .buffer_size_unit = 16, 4277 .burst_size_unit = 16, 4278 .gfx_fifo_workaround = true, 4279 .mstandby_workaround = true, 4280 .set_max_preload = true, 4281 .supports_sync_align = true, 4282 .has_writeback = true, 4283 .supports_double_pixel = true, 4284 .reverse_ilace_field_order = true, 4285 .has_gamma_table = true, 4286 .has_gamma_i734_bug = true, 4287 }; 4288 4289 static irqreturn_t dispc_irq_handler(int irq, void *arg) 4290 { 4291 if (!dispc.is_enabled) 4292 return IRQ_NONE; 4293 4294 return dispc.user_handler(irq, dispc.user_data); 4295 } 4296 4297 static int dispc_request_irq(irq_handler_t handler, void *dev_id) 4298 { 4299 int r; 4300 4301 if (dispc.user_handler != NULL) 4302 return -EBUSY; 4303 4304 dispc.user_handler = handler; 4305 dispc.user_data = dev_id; 4306 4307 /* ensure the dispc_irq_handler sees the values above */ 4308 smp_wmb(); 4309 4310 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, 4311 IRQF_SHARED, "OMAP DISPC", &dispc); 4312 if (r) { 4313 dispc.user_handler = NULL; 4314 dispc.user_data = NULL; 4315 } 4316 4317 return r; 4318 } 4319 4320 static void dispc_free_irq(void *dev_id) 4321 { 4322 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); 4323 4324 dispc.user_handler = NULL; 4325 dispc.user_data = NULL; 4326 } 4327 4328 /* 4329 * Workaround for errata i734 in DSS dispc 4330 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled 4331 * 4332 * For gamma tables to work on LCD1 the GFX plane has to be used at 4333 * least once after DSS HW has come out of reset. The workaround 4334 * sets up a minimal LCD setup with GFX plane and waits for one 4335 * vertical sync irq before disabling the setup and continuing with 4336 * the context restore. The physical outputs are gated during the 4337 * operation. This workaround requires that gamma table's LOADMODE 4338 * is set to 0x2 in DISPC_CONTROL1 register. 4339 * 4340 * For details see: 4341 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata 4342 * Literature Number: SWPZ037E 4343 * Or some other relevant errata document for the DSS IP version. 4344 */ 4345 4346 static const struct dispc_errata_i734_data { 4347 struct videomode vm; 4348 struct omap_overlay_info ovli; 4349 struct omap_overlay_manager_info mgri; 4350 struct dss_lcd_mgr_config lcd_conf; 4351 } i734 = { 4352 .vm = { 4353 .hactive = 8, .vactive = 1, 4354 .pixelclock = 16000000, 4355 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 4356 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, 4357 4358 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4359 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE | 4360 DISPLAY_FLAGS_PIXDATA_POSEDGE, 4361 }, 4362 .ovli = { 4363 .screen_width = 1, 4364 .width = 1, .height = 1, 4365 .fourcc = DRM_FORMAT_XRGB8888, 4366 .rotation = DRM_MODE_ROTATE_0, 4367 .rotation_type = OMAP_DSS_ROT_NONE, 4368 .pos_x = 0, .pos_y = 0, 4369 .out_width = 0, .out_height = 0, 4370 .global_alpha = 0xff, 4371 .pre_mult_alpha = 0, 4372 .zorder = 0, 4373 }, 4374 .mgri = { 4375 .default_color = 0, 4376 .trans_enabled = false, 4377 .partial_alpha_enabled = false, 4378 .cpr_enable = false, 4379 }, 4380 .lcd_conf = { 4381 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS, 4382 .stallmode = false, 4383 .fifohandcheck = false, 4384 .clock_info = { 4385 .lck_div = 1, 4386 .pck_div = 2, 4387 }, 4388 .video_port_width = 24, 4389 .lcden_sig_polarity = 0, 4390 }, 4391 }; 4392 4393 static struct i734_buf { 4394 size_t size; 4395 dma_addr_t paddr; 4396 void *vaddr; 4397 } i734_buf; 4398 4399 static int dispc_errata_i734_wa_init(void) 4400 { 4401 if (!dispc.feat->has_gamma_i734_bug) 4402 return 0; 4403 4404 i734_buf.size = i734.ovli.width * i734.ovli.height * 4405 color_mode_to_bpp(i734.ovli.fourcc) / 8; 4406 4407 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size, 4408 &i734_buf.paddr, GFP_KERNEL); 4409 if (!i734_buf.vaddr) { 4410 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed", 4411 __func__); 4412 return -ENOMEM; 4413 } 4414 4415 return 0; 4416 } 4417 4418 static void dispc_errata_i734_wa_fini(void) 4419 { 4420 if (!dispc.feat->has_gamma_i734_bug) 4421 return; 4422 4423 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr, 4424 i734_buf.paddr); 4425 } 4426 4427 static void dispc_errata_i734_wa(void) 4428 { 4429 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD); 4430 struct omap_overlay_info ovli; 4431 struct dss_lcd_mgr_config lcd_conf; 4432 u32 gatestate; 4433 unsigned int count; 4434 4435 if (!dispc.feat->has_gamma_i734_bug) 4436 return; 4437 4438 gatestate = REG_GET(DISPC_CONFIG, 8, 4); 4439 4440 ovli = i734.ovli; 4441 ovli.paddr = i734_buf.paddr; 4442 lcd_conf = i734.lcd_conf; 4443 4444 /* Gate all LCD1 outputs */ 4445 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4); 4446 4447 /* Setup and enable GFX plane */ 4448 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false, 4449 OMAP_DSS_CHANNEL_LCD); 4450 dispc_ovl_enable(OMAP_DSS_GFX, true); 4451 4452 /* Set up and enable display manager for LCD1 */ 4453 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri); 4454 dispc_calc_clock_rates(dss_get_dispc_clk_rate(), 4455 &lcd_conf.clock_info); 4456 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4457 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm); 4458 4459 dispc_clear_irqstatus(framedone_irq); 4460 4461 /* Enable and shut the channel to produce just one frame */ 4462 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true); 4463 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false); 4464 4465 /* Busy wait for framedone. We can't fiddle with irq handlers 4466 * in PM resume. Typically the loop runs less than 5 times and 4467 * waits less than a micro second. 4468 */ 4469 count = 0; 4470 while (!(dispc_read_irqstatus() & framedone_irq)) { 4471 if (count++ > 10000) { 4472 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n", 4473 __func__); 4474 break; 4475 } 4476 } 4477 dispc_ovl_enable(OMAP_DSS_GFX, false); 4478 4479 /* Clear all irq bits before continuing */ 4480 dispc_clear_irqstatus(0xffffffff); 4481 4482 /* Restore the original state to LCD1 output gates */ 4483 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4); 4484 } 4485 4486 static const struct dispc_ops dispc_ops = { 4487 .read_irqstatus = dispc_read_irqstatus, 4488 .clear_irqstatus = dispc_clear_irqstatus, 4489 .write_irqenable = dispc_write_irqenable, 4490 4491 .request_irq = dispc_request_irq, 4492 .free_irq = dispc_free_irq, 4493 4494 .runtime_get = dispc_runtime_get, 4495 .runtime_put = dispc_runtime_put, 4496 4497 .get_num_ovls = dispc_get_num_ovls, 4498 .get_num_mgrs = dispc_get_num_mgrs, 4499 4500 .mgr_enable = dispc_mgr_enable, 4501 .mgr_is_enabled = dispc_mgr_is_enabled, 4502 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, 4503 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq, 4504 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq, 4505 .mgr_go_busy = dispc_mgr_go_busy, 4506 .mgr_go = dispc_mgr_go, 4507 .mgr_set_lcd_config = dispc_mgr_set_lcd_config, 4508 .mgr_set_timings = dispc_mgr_set_timings, 4509 .mgr_setup = dispc_mgr_setup, 4510 .mgr_get_supported_outputs = dispc_mgr_get_supported_outputs, 4511 .mgr_gamma_size = dispc_mgr_gamma_size, 4512 .mgr_set_gamma = dispc_mgr_set_gamma, 4513 4514 .ovl_enable = dispc_ovl_enable, 4515 .ovl_setup = dispc_ovl_setup, 4516 .ovl_get_color_modes = dispc_ovl_get_color_modes, 4517 }; 4518 4519 /* DISPC HW IP initialisation */ 4520 static const struct of_device_id dispc_of_match[] = { 4521 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats }, 4522 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats }, 4523 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats }, 4524 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats }, 4525 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats }, 4526 {}, 4527 }; 4528 4529 static const struct soc_device_attribute dispc_soc_devices[] = { 4530 { .machine = "OMAP3[45]*", 4531 .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, 4532 { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, 4533 { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, 4534 { .machine = "AM43*", .data = &am43xx_dispc_feats }, 4535 { /* sentinel */ } 4536 }; 4537 4538 static int dispc_bind(struct device *dev, struct device *master, void *data) 4539 { 4540 struct platform_device *pdev = to_platform_device(dev); 4541 const struct soc_device_attribute *soc; 4542 u32 rev; 4543 int r = 0; 4544 struct resource *dispc_mem; 4545 struct device_node *np = pdev->dev.of_node; 4546 4547 dispc.pdev = pdev; 4548 4549 spin_lock_init(&dispc.control_lock); 4550 4551 /* 4552 * The OMAP3-based models can't be told apart using the compatible 4553 * string, use SoC device matching. 4554 */ 4555 soc = soc_device_match(dispc_soc_devices); 4556 if (soc) 4557 dispc.feat = soc->data; 4558 else 4559 dispc.feat = of_match_device(dispc_of_match, &pdev->dev)->data; 4560 4561 r = dispc_errata_i734_wa_init(); 4562 if (r) 4563 return r; 4564 4565 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); 4566 dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem); 4567 if (IS_ERR(dispc.base)) 4568 return PTR_ERR(dispc.base); 4569 4570 dispc.irq = platform_get_irq(dispc.pdev, 0); 4571 if (dispc.irq < 0) { 4572 DSSERR("platform_get_irq failed\n"); 4573 return -ENODEV; 4574 } 4575 4576 if (np && of_property_read_bool(np, "syscon-pol")) { 4577 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 4578 if (IS_ERR(dispc.syscon_pol)) { 4579 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 4580 return PTR_ERR(dispc.syscon_pol); 4581 } 4582 4583 if (of_property_read_u32_index(np, "syscon-pol", 1, 4584 &dispc.syscon_pol_offset)) { 4585 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 4586 return -EINVAL; 4587 } 4588 } 4589 4590 r = dispc_init_gamma_tables(); 4591 if (r) 4592 return r; 4593 4594 pm_runtime_enable(&pdev->dev); 4595 4596 r = dispc_runtime_get(); 4597 if (r) 4598 goto err_runtime_get; 4599 4600 _omap_dispc_initial_config(); 4601 4602 rev = dispc_read_reg(DISPC_REVISION); 4603 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 4604 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4605 4606 dispc_runtime_put(); 4607 4608 dispc_set_ops(&dispc_ops); 4609 4610 dss_debugfs_create_file("dispc", dispc_dump_regs); 4611 4612 return 0; 4613 4614 err_runtime_get: 4615 pm_runtime_disable(&pdev->dev); 4616 return r; 4617 } 4618 4619 static void dispc_unbind(struct device *dev, struct device *master, 4620 void *data) 4621 { 4622 dispc_set_ops(NULL); 4623 4624 pm_runtime_disable(dev); 4625 4626 dispc_errata_i734_wa_fini(); 4627 } 4628 4629 static const struct component_ops dispc_component_ops = { 4630 .bind = dispc_bind, 4631 .unbind = dispc_unbind, 4632 }; 4633 4634 static int dispc_probe(struct platform_device *pdev) 4635 { 4636 return component_add(&pdev->dev, &dispc_component_ops); 4637 } 4638 4639 static int dispc_remove(struct platform_device *pdev) 4640 { 4641 component_del(&pdev->dev, &dispc_component_ops); 4642 return 0; 4643 } 4644 4645 static int dispc_runtime_suspend(struct device *dev) 4646 { 4647 dispc.is_enabled = false; 4648 /* ensure the dispc_irq_handler sees the is_enabled value */ 4649 smp_wmb(); 4650 /* wait for current handler to finish before turning the DISPC off */ 4651 synchronize_irq(dispc.irq); 4652 4653 dispc_save_context(); 4654 4655 return 0; 4656 } 4657 4658 static int dispc_runtime_resume(struct device *dev) 4659 { 4660 /* 4661 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4662 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4663 * _omap_dispc_initial_config(). We can thus use it to detect if 4664 * we have lost register context. 4665 */ 4666 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4667 _omap_dispc_initial_config(); 4668 4669 dispc_errata_i734_wa(); 4670 4671 dispc_restore_context(); 4672 4673 dispc_restore_gamma_tables(); 4674 } 4675 4676 dispc.is_enabled = true; 4677 /* ensure the dispc_irq_handler sees the is_enabled value */ 4678 smp_wmb(); 4679 4680 return 0; 4681 } 4682 4683 static const struct dev_pm_ops dispc_pm_ops = { 4684 .runtime_suspend = dispc_runtime_suspend, 4685 .runtime_resume = dispc_runtime_resume, 4686 }; 4687 4688 static struct platform_driver omap_dispchw_driver = { 4689 .probe = dispc_probe, 4690 .remove = dispc_remove, 4691 .driver = { 4692 .name = "omapdss_dispc", 4693 .pm = &dispc_pm_ops, 4694 .of_match_table = dispc_of_match, 4695 .suppress_bind_attrs = true, 4696 }, 4697 }; 4698 4699 int __init dispc_init_platform_driver(void) 4700 { 4701 return platform_driver_register(&omap_dispchw_driver); 4702 } 4703 4704 void dispc_uninit_platform_driver(void) 4705 { 4706 platform_driver_unregister(&omap_dispchw_driver); 4707 } 4708