1 /* 2 * linux/drivers/video/omap2/dss/dispc.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #define DSS_SUBSYS_NAME "DISPC" 24 25 #include <linux/kernel.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/vmalloc.h> 28 #include <linux/export.h> 29 #include <linux/clk.h> 30 #include <linux/io.h> 31 #include <linux/jiffies.h> 32 #include <linux/seq_file.h> 33 #include <linux/delay.h> 34 #include <linux/workqueue.h> 35 #include <linux/hardirq.h> 36 #include <linux/platform_device.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/sizes.h> 39 #include <linux/mfd/syscon.h> 40 #include <linux/regmap.h> 41 #include <linux/of.h> 42 #include <linux/component.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_blend.h> 45 46 #include "omapdss.h" 47 #include "dss.h" 48 #include "dss_features.h" 49 #include "dispc.h" 50 51 /* DISPC */ 52 #define DISPC_SZ_REGS SZ_4K 53 54 enum omap_burst_size { 55 BURST_SIZE_X2 = 0, 56 BURST_SIZE_X4 = 1, 57 BURST_SIZE_X8 = 2, 58 }; 59 60 #define REG_GET(idx, start, end) \ 61 FLD_GET(dispc_read_reg(idx), start, end) 62 63 #define REG_FLD_MOD(idx, val, start, end) \ 64 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 65 66 struct dispc_features { 67 u8 sw_start; 68 u8 fp_start; 69 u8 bp_start; 70 u16 sw_max; 71 u16 vp_max; 72 u16 hp_max; 73 u8 mgr_width_start; 74 u8 mgr_height_start; 75 u16 mgr_width_max; 76 u16 mgr_height_max; 77 unsigned long max_lcd_pclk; 78 unsigned long max_tv_pclk; 79 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 80 const struct videomode *vm, 81 u16 width, u16 height, u16 out_width, u16 out_height, 82 u32 fourcc, bool *five_taps, 83 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 84 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 85 unsigned long (*calc_core_clk) (unsigned long pclk, 86 u16 width, u16 height, u16 out_width, u16 out_height, 87 bool mem_to_mem); 88 u8 num_fifos; 89 90 /* swap GFX & WB fifos */ 91 bool gfx_fifo_workaround:1; 92 93 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 94 bool no_framedone_tv:1; 95 96 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 97 bool mstandby_workaround:1; 98 99 bool set_max_preload:1; 100 101 /* PIXEL_INC is not added to the last pixel of a line */ 102 bool last_pixel_inc_missing:1; 103 104 /* POL_FREQ has ALIGN bit */ 105 bool supports_sync_align:1; 106 107 bool has_writeback:1; 108 109 bool supports_double_pixel:1; 110 111 /* 112 * Field order for VENC is different than HDMI. We should handle this in 113 * some intelligent manner, but as the SoCs have either HDMI or VENC, 114 * never both, we can just use this flag for now. 115 */ 116 bool reverse_ilace_field_order:1; 117 118 bool has_gamma_table:1; 119 120 bool has_gamma_i734_bug:1; 121 }; 122 123 #define DISPC_MAX_NR_FIFOS 5 124 #define DISPC_MAX_CHANNEL_GAMMA 4 125 126 static struct { 127 struct platform_device *pdev; 128 void __iomem *base; 129 130 int irq; 131 irq_handler_t user_handler; 132 void *user_data; 133 134 unsigned long core_clk_rate; 135 unsigned long tv_pclk_rate; 136 137 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 138 /* maps which plane is using a fifo. fifo-id -> plane-id */ 139 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 140 141 bool ctx_valid; 142 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 143 144 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA]; 145 146 const struct dispc_features *feat; 147 148 bool is_enabled; 149 150 struct regmap *syscon_pol; 151 u32 syscon_pol_offset; 152 153 /* DISPC_CONTROL & DISPC_CONFIG lock*/ 154 spinlock_t control_lock; 155 } dispc; 156 157 enum omap_color_component { 158 /* used for all color formats for OMAP3 and earlier 159 * and for RGB and Y color component on OMAP4 160 */ 161 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 162 /* used for UV component for 163 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12 164 * color formats on OMAP4 165 */ 166 DISPC_COLOR_COMPONENT_UV = 1 << 1, 167 }; 168 169 enum mgr_reg_fields { 170 DISPC_MGR_FLD_ENABLE, 171 DISPC_MGR_FLD_STNTFT, 172 DISPC_MGR_FLD_GO, 173 DISPC_MGR_FLD_TFTDATALINES, 174 DISPC_MGR_FLD_STALLMODE, 175 DISPC_MGR_FLD_TCKENABLE, 176 DISPC_MGR_FLD_TCKSELECTION, 177 DISPC_MGR_FLD_CPR, 178 DISPC_MGR_FLD_FIFOHANDCHECK, 179 /* used to maintain a count of the above fields */ 180 DISPC_MGR_FLD_NUM, 181 }; 182 183 struct dispc_reg_field { 184 u16 reg; 185 u8 high; 186 u8 low; 187 }; 188 189 struct dispc_gamma_desc { 190 u32 len; 191 u32 bits; 192 u16 reg; 193 bool has_index; 194 }; 195 196 static const struct { 197 const char *name; 198 u32 vsync_irq; 199 u32 framedone_irq; 200 u32 sync_lost_irq; 201 struct dispc_gamma_desc gamma; 202 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 203 } mgr_desc[] = { 204 [OMAP_DSS_CHANNEL_LCD] = { 205 .name = "LCD", 206 .vsync_irq = DISPC_IRQ_VSYNC, 207 .framedone_irq = DISPC_IRQ_FRAMEDONE, 208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 209 .gamma = { 210 .len = 256, 211 .bits = 8, 212 .reg = DISPC_GAMMA_TABLE0, 213 .has_index = true, 214 }, 215 .reg_desc = { 216 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 217 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 218 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 219 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 220 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 221 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 222 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 223 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 224 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 225 }, 226 }, 227 [OMAP_DSS_CHANNEL_DIGIT] = { 228 .name = "DIGIT", 229 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 230 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 231 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 232 .gamma = { 233 .len = 1024, 234 .bits = 10, 235 .reg = DISPC_GAMMA_TABLE2, 236 .has_index = false, 237 }, 238 .reg_desc = { 239 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 240 [DISPC_MGR_FLD_STNTFT] = { }, 241 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 242 [DISPC_MGR_FLD_TFTDATALINES] = { }, 243 [DISPC_MGR_FLD_STALLMODE] = { }, 244 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 245 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 246 [DISPC_MGR_FLD_CPR] = { }, 247 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 248 }, 249 }, 250 [OMAP_DSS_CHANNEL_LCD2] = { 251 .name = "LCD2", 252 .vsync_irq = DISPC_IRQ_VSYNC2, 253 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 254 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 255 .gamma = { 256 .len = 256, 257 .bits = 8, 258 .reg = DISPC_GAMMA_TABLE1, 259 .has_index = true, 260 }, 261 .reg_desc = { 262 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 263 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 264 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 265 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 266 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 267 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 268 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 269 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 270 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 271 }, 272 }, 273 [OMAP_DSS_CHANNEL_LCD3] = { 274 .name = "LCD3", 275 .vsync_irq = DISPC_IRQ_VSYNC3, 276 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 277 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 278 .gamma = { 279 .len = 256, 280 .bits = 8, 281 .reg = DISPC_GAMMA_TABLE3, 282 .has_index = true, 283 }, 284 .reg_desc = { 285 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 286 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 287 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 288 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 289 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 290 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 291 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 292 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 293 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 294 }, 295 }, 296 }; 297 298 struct color_conv_coef { 299 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; 300 int full_range; 301 }; 302 303 static unsigned long dispc_fclk_rate(void); 304 static unsigned long dispc_core_clk_rate(void); 305 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 306 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 307 308 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane); 309 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane); 310 311 static void dispc_clear_irqstatus(u32 mask); 312 static bool dispc_mgr_is_enabled(enum omap_channel channel); 313 static void dispc_clear_irqstatus(u32 mask); 314 315 static inline void dispc_write_reg(const u16 idx, u32 val) 316 { 317 __raw_writel(val, dispc.base + idx); 318 } 319 320 static inline u32 dispc_read_reg(const u16 idx) 321 { 322 return __raw_readl(dispc.base + idx); 323 } 324 325 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) 326 { 327 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 328 return REG_GET(rfld.reg, rfld.high, rfld.low); 329 } 330 331 static void mgr_fld_write(enum omap_channel channel, 332 enum mgr_reg_fields regfld, int val) { 333 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 334 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; 335 unsigned long flags; 336 337 if (need_lock) 338 spin_lock_irqsave(&dispc.control_lock, flags); 339 340 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 341 342 if (need_lock) 343 spin_unlock_irqrestore(&dispc.control_lock, flags); 344 } 345 346 #define SR(reg) \ 347 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 348 #define RR(reg) \ 349 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) 350 351 static void dispc_save_context(void) 352 { 353 int i, j; 354 355 DSSDBG("dispc_save_context\n"); 356 357 SR(IRQENABLE); 358 SR(CONTROL); 359 SR(CONFIG); 360 SR(LINE_NUMBER); 361 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 362 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 363 SR(GLOBAL_ALPHA); 364 if (dss_has_feature(FEAT_MGR_LCD2)) { 365 SR(CONTROL2); 366 SR(CONFIG2); 367 } 368 if (dss_has_feature(FEAT_MGR_LCD3)) { 369 SR(CONTROL3); 370 SR(CONFIG3); 371 } 372 373 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 374 SR(DEFAULT_COLOR(i)); 375 SR(TRANS_COLOR(i)); 376 SR(SIZE_MGR(i)); 377 if (i == OMAP_DSS_CHANNEL_DIGIT) 378 continue; 379 SR(TIMING_H(i)); 380 SR(TIMING_V(i)); 381 SR(POL_FREQ(i)); 382 SR(DIVISORo(i)); 383 384 SR(DATA_CYCLE1(i)); 385 SR(DATA_CYCLE2(i)); 386 SR(DATA_CYCLE3(i)); 387 388 if (dss_has_feature(FEAT_CPR)) { 389 SR(CPR_COEF_R(i)); 390 SR(CPR_COEF_G(i)); 391 SR(CPR_COEF_B(i)); 392 } 393 } 394 395 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 396 SR(OVL_BA0(i)); 397 SR(OVL_BA1(i)); 398 SR(OVL_POSITION(i)); 399 SR(OVL_SIZE(i)); 400 SR(OVL_ATTRIBUTES(i)); 401 SR(OVL_FIFO_THRESHOLD(i)); 402 SR(OVL_ROW_INC(i)); 403 SR(OVL_PIXEL_INC(i)); 404 if (dss_has_feature(FEAT_PRELOAD)) 405 SR(OVL_PRELOAD(i)); 406 if (i == OMAP_DSS_GFX) { 407 SR(OVL_WINDOW_SKIP(i)); 408 SR(OVL_TABLE_BA(i)); 409 continue; 410 } 411 SR(OVL_FIR(i)); 412 SR(OVL_PICTURE_SIZE(i)); 413 SR(OVL_ACCU0(i)); 414 SR(OVL_ACCU1(i)); 415 416 for (j = 0; j < 8; j++) 417 SR(OVL_FIR_COEF_H(i, j)); 418 419 for (j = 0; j < 8; j++) 420 SR(OVL_FIR_COEF_HV(i, j)); 421 422 for (j = 0; j < 5; j++) 423 SR(OVL_CONV_COEF(i, j)); 424 425 if (dss_has_feature(FEAT_FIR_COEF_V)) { 426 for (j = 0; j < 8; j++) 427 SR(OVL_FIR_COEF_V(i, j)); 428 } 429 430 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 431 SR(OVL_BA0_UV(i)); 432 SR(OVL_BA1_UV(i)); 433 SR(OVL_FIR2(i)); 434 SR(OVL_ACCU2_0(i)); 435 SR(OVL_ACCU2_1(i)); 436 437 for (j = 0; j < 8; j++) 438 SR(OVL_FIR_COEF_H2(i, j)); 439 440 for (j = 0; j < 8; j++) 441 SR(OVL_FIR_COEF_HV2(i, j)); 442 443 for (j = 0; j < 8; j++) 444 SR(OVL_FIR_COEF_V2(i, j)); 445 } 446 if (dss_has_feature(FEAT_ATTR2)) 447 SR(OVL_ATTRIBUTES2(i)); 448 } 449 450 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 451 SR(DIVISOR); 452 453 dispc.ctx_valid = true; 454 455 DSSDBG("context saved\n"); 456 } 457 458 static void dispc_restore_context(void) 459 { 460 int i, j; 461 462 DSSDBG("dispc_restore_context\n"); 463 464 if (!dispc.ctx_valid) 465 return; 466 467 /*RR(IRQENABLE);*/ 468 /*RR(CONTROL);*/ 469 RR(CONFIG); 470 RR(LINE_NUMBER); 471 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 472 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 473 RR(GLOBAL_ALPHA); 474 if (dss_has_feature(FEAT_MGR_LCD2)) 475 RR(CONFIG2); 476 if (dss_has_feature(FEAT_MGR_LCD3)) 477 RR(CONFIG3); 478 479 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 480 RR(DEFAULT_COLOR(i)); 481 RR(TRANS_COLOR(i)); 482 RR(SIZE_MGR(i)); 483 if (i == OMAP_DSS_CHANNEL_DIGIT) 484 continue; 485 RR(TIMING_H(i)); 486 RR(TIMING_V(i)); 487 RR(POL_FREQ(i)); 488 RR(DIVISORo(i)); 489 490 RR(DATA_CYCLE1(i)); 491 RR(DATA_CYCLE2(i)); 492 RR(DATA_CYCLE3(i)); 493 494 if (dss_has_feature(FEAT_CPR)) { 495 RR(CPR_COEF_R(i)); 496 RR(CPR_COEF_G(i)); 497 RR(CPR_COEF_B(i)); 498 } 499 } 500 501 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 502 RR(OVL_BA0(i)); 503 RR(OVL_BA1(i)); 504 RR(OVL_POSITION(i)); 505 RR(OVL_SIZE(i)); 506 RR(OVL_ATTRIBUTES(i)); 507 RR(OVL_FIFO_THRESHOLD(i)); 508 RR(OVL_ROW_INC(i)); 509 RR(OVL_PIXEL_INC(i)); 510 if (dss_has_feature(FEAT_PRELOAD)) 511 RR(OVL_PRELOAD(i)); 512 if (i == OMAP_DSS_GFX) { 513 RR(OVL_WINDOW_SKIP(i)); 514 RR(OVL_TABLE_BA(i)); 515 continue; 516 } 517 RR(OVL_FIR(i)); 518 RR(OVL_PICTURE_SIZE(i)); 519 RR(OVL_ACCU0(i)); 520 RR(OVL_ACCU1(i)); 521 522 for (j = 0; j < 8; j++) 523 RR(OVL_FIR_COEF_H(i, j)); 524 525 for (j = 0; j < 8; j++) 526 RR(OVL_FIR_COEF_HV(i, j)); 527 528 for (j = 0; j < 5; j++) 529 RR(OVL_CONV_COEF(i, j)); 530 531 if (dss_has_feature(FEAT_FIR_COEF_V)) { 532 for (j = 0; j < 8; j++) 533 RR(OVL_FIR_COEF_V(i, j)); 534 } 535 536 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 537 RR(OVL_BA0_UV(i)); 538 RR(OVL_BA1_UV(i)); 539 RR(OVL_FIR2(i)); 540 RR(OVL_ACCU2_0(i)); 541 RR(OVL_ACCU2_1(i)); 542 543 for (j = 0; j < 8; j++) 544 RR(OVL_FIR_COEF_H2(i, j)); 545 546 for (j = 0; j < 8; j++) 547 RR(OVL_FIR_COEF_HV2(i, j)); 548 549 for (j = 0; j < 8; j++) 550 RR(OVL_FIR_COEF_V2(i, j)); 551 } 552 if (dss_has_feature(FEAT_ATTR2)) 553 RR(OVL_ATTRIBUTES2(i)); 554 } 555 556 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 557 RR(DIVISOR); 558 559 /* enable last, because LCD & DIGIT enable are here */ 560 RR(CONTROL); 561 if (dss_has_feature(FEAT_MGR_LCD2)) 562 RR(CONTROL2); 563 if (dss_has_feature(FEAT_MGR_LCD3)) 564 RR(CONTROL3); 565 /* clear spurious SYNC_LOST_DIGIT interrupts */ 566 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); 567 568 /* 569 * enable last so IRQs won't trigger before 570 * the context is fully restored 571 */ 572 RR(IRQENABLE); 573 574 DSSDBG("context restored\n"); 575 } 576 577 #undef SR 578 #undef RR 579 580 int dispc_runtime_get(void) 581 { 582 int r; 583 584 DSSDBG("dispc_runtime_get\n"); 585 586 r = pm_runtime_get_sync(&dispc.pdev->dev); 587 WARN_ON(r < 0); 588 return r < 0 ? r : 0; 589 } 590 591 void dispc_runtime_put(void) 592 { 593 int r; 594 595 DSSDBG("dispc_runtime_put\n"); 596 597 r = pm_runtime_put_sync(&dispc.pdev->dev); 598 WARN_ON(r < 0 && r != -ENOSYS); 599 } 600 601 static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 602 { 603 return mgr_desc[channel].vsync_irq; 604 } 605 606 static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 607 { 608 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) 609 return 0; 610 611 return mgr_desc[channel].framedone_irq; 612 } 613 614 static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 615 { 616 return mgr_desc[channel].sync_lost_irq; 617 } 618 619 u32 dispc_wb_get_framedone_irq(void) 620 { 621 return DISPC_IRQ_FRAMEDONEWB; 622 } 623 624 static void dispc_mgr_enable(enum omap_channel channel, bool enable) 625 { 626 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); 627 /* flush posted write */ 628 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 629 } 630 631 static bool dispc_mgr_is_enabled(enum omap_channel channel) 632 { 633 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 634 } 635 636 static bool dispc_mgr_go_busy(enum omap_channel channel) 637 { 638 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 639 } 640 641 static void dispc_mgr_go(enum omap_channel channel) 642 { 643 WARN_ON(!dispc_mgr_is_enabled(channel)); 644 WARN_ON(dispc_mgr_go_busy(channel)); 645 646 DSSDBG("GO %s\n", mgr_desc[channel].name); 647 648 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 649 } 650 651 bool dispc_wb_go_busy(void) 652 { 653 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; 654 } 655 656 void dispc_wb_go(void) 657 { 658 enum omap_plane_id plane = OMAP_DSS_WB; 659 bool enable, go; 660 661 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 662 663 if (!enable) 664 return; 665 666 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; 667 if (go) { 668 DSSERR("GO bit not down for WB\n"); 669 return; 670 } 671 672 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); 673 } 674 675 static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg, 676 u32 value) 677 { 678 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 679 } 680 681 static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg, 682 u32 value) 683 { 684 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 685 } 686 687 static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg, 688 u32 value) 689 { 690 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 691 } 692 693 static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg, 694 u32 value) 695 { 696 BUG_ON(plane == OMAP_DSS_GFX); 697 698 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 699 } 700 701 static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg, 702 u32 value) 703 { 704 BUG_ON(plane == OMAP_DSS_GFX); 705 706 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 707 } 708 709 static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg, 710 u32 value) 711 { 712 BUG_ON(plane == OMAP_DSS_GFX); 713 714 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 715 } 716 717 static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc, 718 int fir_vinc, int five_taps, 719 enum omap_color_component color_comp) 720 { 721 const struct dispc_coef *h_coef, *v_coef; 722 int i; 723 724 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 725 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 726 727 for (i = 0; i < 8; i++) { 728 u32 h, hv; 729 730 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 731 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 732 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 733 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 734 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 735 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 736 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 737 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 738 739 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 740 dispc_ovl_write_firh_reg(plane, i, h); 741 dispc_ovl_write_firhv_reg(plane, i, hv); 742 } else { 743 dispc_ovl_write_firh2_reg(plane, i, h); 744 dispc_ovl_write_firhv2_reg(plane, i, hv); 745 } 746 747 } 748 749 if (five_taps) { 750 for (i = 0; i < 8; i++) { 751 u32 v; 752 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 753 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 754 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 755 dispc_ovl_write_firv_reg(plane, i, v); 756 else 757 dispc_ovl_write_firv2_reg(plane, i, v); 758 } 759 } 760 } 761 762 763 static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, 764 const struct color_conv_coef *ct) 765 { 766 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 767 768 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 769 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 770 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 771 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 772 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 773 774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 775 776 #undef CVAL 777 } 778 779 static void dispc_setup_color_conv_coef(void) 780 { 781 int i; 782 int num_ovl = dss_feat_get_num_ovls(); 783 const struct color_conv_coef ctbl_bt601_5_ovl = { 784 /* YUV -> RGB */ 785 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 786 }; 787 const struct color_conv_coef ctbl_bt601_5_wb = { 788 /* RGB -> YUV */ 789 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 790 }; 791 792 for (i = 1; i < num_ovl; i++) 793 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 794 795 if (dispc.feat->has_writeback) 796 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 797 } 798 799 static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr) 800 { 801 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 802 } 803 804 static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr) 805 { 806 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 807 } 808 809 static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr) 810 { 811 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 812 } 813 814 static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr) 815 { 816 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 817 } 818 819 static void dispc_ovl_set_pos(enum omap_plane_id plane, 820 enum omap_overlay_caps caps, int x, int y) 821 { 822 u32 val; 823 824 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 825 return; 826 827 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 828 829 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 830 } 831 832 static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width, 833 int height) 834 { 835 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 836 837 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 838 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 839 else 840 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 841 } 842 843 static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width, 844 int height) 845 { 846 u32 val; 847 848 BUG_ON(plane == OMAP_DSS_GFX); 849 850 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 851 852 if (plane == OMAP_DSS_WB) 853 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 854 else 855 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 856 } 857 858 static void dispc_ovl_set_zorder(enum omap_plane_id plane, 859 enum omap_overlay_caps caps, u8 zorder) 860 { 861 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 862 return; 863 864 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 865 } 866 867 static void dispc_ovl_enable_zorder_planes(void) 868 { 869 int i; 870 871 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 872 return; 873 874 for (i = 0; i < dss_feat_get_num_ovls(); i++) 875 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 876 } 877 878 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane, 879 enum omap_overlay_caps caps, bool enable) 880 { 881 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 882 return; 883 884 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 885 } 886 887 static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane, 888 enum omap_overlay_caps caps, u8 global_alpha) 889 { 890 static const unsigned shifts[] = { 0, 8, 16, 24, }; 891 int shift; 892 893 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 894 return; 895 896 shift = shifts[plane]; 897 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 898 } 899 900 static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc) 901 { 902 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 903 } 904 905 static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc) 906 { 907 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 908 } 909 910 static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc) 911 { 912 u32 m = 0; 913 if (plane != OMAP_DSS_GFX) { 914 switch (fourcc) { 915 case DRM_FORMAT_NV12: 916 m = 0x0; break; 917 case DRM_FORMAT_XRGB4444: 918 m = 0x1; break; 919 case DRM_FORMAT_RGBA4444: 920 m = 0x2; break; 921 case DRM_FORMAT_RGBX4444: 922 m = 0x4; break; 923 case DRM_FORMAT_ARGB4444: 924 m = 0x5; break; 925 case DRM_FORMAT_RGB565: 926 m = 0x6; break; 927 case DRM_FORMAT_ARGB1555: 928 m = 0x7; break; 929 case DRM_FORMAT_XRGB8888: 930 m = 0x8; break; 931 case DRM_FORMAT_RGB888: 932 m = 0x9; break; 933 case DRM_FORMAT_YUYV: 934 m = 0xa; break; 935 case DRM_FORMAT_UYVY: 936 m = 0xb; break; 937 case DRM_FORMAT_ARGB8888: 938 m = 0xc; break; 939 case DRM_FORMAT_RGBA8888: 940 m = 0xd; break; 941 case DRM_FORMAT_RGBX8888: 942 m = 0xe; break; 943 case DRM_FORMAT_XRGB1555: 944 m = 0xf; break; 945 default: 946 BUG(); return; 947 } 948 } else { 949 switch (fourcc) { 950 case DRM_FORMAT_RGBX4444: 951 m = 0x4; break; 952 case DRM_FORMAT_ARGB4444: 953 m = 0x5; break; 954 case DRM_FORMAT_RGB565: 955 m = 0x6; break; 956 case DRM_FORMAT_ARGB1555: 957 m = 0x7; break; 958 case DRM_FORMAT_XRGB8888: 959 m = 0x8; break; 960 case DRM_FORMAT_RGB888: 961 m = 0x9; break; 962 case DRM_FORMAT_XRGB4444: 963 m = 0xa; break; 964 case DRM_FORMAT_RGBA4444: 965 m = 0xb; break; 966 case DRM_FORMAT_ARGB8888: 967 m = 0xc; break; 968 case DRM_FORMAT_RGBA8888: 969 m = 0xd; break; 970 case DRM_FORMAT_RGBX8888: 971 m = 0xe; break; 972 case DRM_FORMAT_XRGB1555: 973 m = 0xf; break; 974 default: 975 BUG(); return; 976 } 977 } 978 979 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 980 } 981 982 static bool format_is_yuv(u32 fourcc) 983 { 984 switch (fourcc) { 985 case DRM_FORMAT_YUYV: 986 case DRM_FORMAT_UYVY: 987 case DRM_FORMAT_NV12: 988 return true; 989 default: 990 return false; 991 } 992 } 993 994 static void dispc_ovl_configure_burst_type(enum omap_plane_id plane, 995 enum omap_dss_rotation_type rotation_type) 996 { 997 if (dss_has_feature(FEAT_BURST_2D) == 0) 998 return; 999 1000 if (rotation_type == OMAP_DSS_ROT_TILER) 1001 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 1002 else 1003 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 1004 } 1005 1006 static void dispc_ovl_set_channel_out(enum omap_plane_id plane, 1007 enum omap_channel channel) 1008 { 1009 int shift; 1010 u32 val; 1011 int chan = 0, chan2 = 0; 1012 1013 switch (plane) { 1014 case OMAP_DSS_GFX: 1015 shift = 8; 1016 break; 1017 case OMAP_DSS_VIDEO1: 1018 case OMAP_DSS_VIDEO2: 1019 case OMAP_DSS_VIDEO3: 1020 shift = 16; 1021 break; 1022 default: 1023 BUG(); 1024 return; 1025 } 1026 1027 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1028 if (dss_has_feature(FEAT_MGR_LCD2)) { 1029 switch (channel) { 1030 case OMAP_DSS_CHANNEL_LCD: 1031 chan = 0; 1032 chan2 = 0; 1033 break; 1034 case OMAP_DSS_CHANNEL_DIGIT: 1035 chan = 1; 1036 chan2 = 0; 1037 break; 1038 case OMAP_DSS_CHANNEL_LCD2: 1039 chan = 0; 1040 chan2 = 1; 1041 break; 1042 case OMAP_DSS_CHANNEL_LCD3: 1043 if (dss_has_feature(FEAT_MGR_LCD3)) { 1044 chan = 0; 1045 chan2 = 2; 1046 } else { 1047 BUG(); 1048 return; 1049 } 1050 break; 1051 case OMAP_DSS_CHANNEL_WB: 1052 chan = 0; 1053 chan2 = 3; 1054 break; 1055 default: 1056 BUG(); 1057 return; 1058 } 1059 1060 val = FLD_MOD(val, chan, shift, shift); 1061 val = FLD_MOD(val, chan2, 31, 30); 1062 } else { 1063 val = FLD_MOD(val, channel, shift, shift); 1064 } 1065 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1066 } 1067 1068 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane) 1069 { 1070 int shift; 1071 u32 val; 1072 1073 switch (plane) { 1074 case OMAP_DSS_GFX: 1075 shift = 8; 1076 break; 1077 case OMAP_DSS_VIDEO1: 1078 case OMAP_DSS_VIDEO2: 1079 case OMAP_DSS_VIDEO3: 1080 shift = 16; 1081 break; 1082 default: 1083 BUG(); 1084 return 0; 1085 } 1086 1087 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1088 1089 if (FLD_GET(val, shift, shift) == 1) 1090 return OMAP_DSS_CHANNEL_DIGIT; 1091 1092 if (!dss_has_feature(FEAT_MGR_LCD2)) 1093 return OMAP_DSS_CHANNEL_LCD; 1094 1095 switch (FLD_GET(val, 31, 30)) { 1096 case 0: 1097 default: 1098 return OMAP_DSS_CHANNEL_LCD; 1099 case 1: 1100 return OMAP_DSS_CHANNEL_LCD2; 1101 case 2: 1102 return OMAP_DSS_CHANNEL_LCD3; 1103 case 3: 1104 return OMAP_DSS_CHANNEL_WB; 1105 } 1106 } 1107 1108 void dispc_wb_set_channel_in(enum dss_writeback_channel channel) 1109 { 1110 enum omap_plane_id plane = OMAP_DSS_WB; 1111 1112 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); 1113 } 1114 1115 static void dispc_ovl_set_burst_size(enum omap_plane_id plane, 1116 enum omap_burst_size burst_size) 1117 { 1118 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1119 int shift; 1120 1121 shift = shifts[plane]; 1122 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1123 } 1124 1125 static void dispc_configure_burst_sizes(void) 1126 { 1127 int i; 1128 const int burst_size = BURST_SIZE_X8; 1129 1130 /* Configure burst size always to maximum size */ 1131 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1132 dispc_ovl_set_burst_size(i, burst_size); 1133 if (dispc.feat->has_writeback) 1134 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1135 } 1136 1137 static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) 1138 { 1139 unsigned unit = dss_feat_get_burst_size_unit(); 1140 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1141 return unit * 8; 1142 } 1143 1144 static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) 1145 { 1146 return dss_feat_get_supported_color_modes(plane); 1147 } 1148 1149 static int dispc_get_num_ovls(void) 1150 { 1151 return dss_feat_get_num_ovls(); 1152 } 1153 1154 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 1155 { 1156 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1157 return; 1158 1159 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); 1160 } 1161 1162 static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 1163 const struct omap_dss_cpr_coefs *coefs) 1164 { 1165 u32 coef_r, coef_g, coef_b; 1166 1167 if (!dss_mgr_is_lcd(channel)) 1168 return; 1169 1170 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1171 FLD_VAL(coefs->rb, 9, 0); 1172 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1173 FLD_VAL(coefs->gb, 9, 0); 1174 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1175 FLD_VAL(coefs->bb, 9, 0); 1176 1177 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); 1178 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); 1179 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1180 } 1181 1182 static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane, 1183 bool enable) 1184 { 1185 u32 val; 1186 1187 BUG_ON(plane == OMAP_DSS_GFX); 1188 1189 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1190 val = FLD_MOD(val, enable, 9, 9); 1191 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1192 } 1193 1194 static void dispc_ovl_enable_replication(enum omap_plane_id plane, 1195 enum omap_overlay_caps caps, bool enable) 1196 { 1197 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1198 int shift; 1199 1200 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1201 return; 1202 1203 shift = shifts[plane]; 1204 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1205 } 1206 1207 static void dispc_mgr_set_size(enum omap_channel channel, u16 width, 1208 u16 height) 1209 { 1210 u32 val; 1211 1212 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | 1213 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); 1214 1215 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1216 } 1217 1218 static void dispc_init_fifos(void) 1219 { 1220 u32 size; 1221 int fifo; 1222 u8 start, end; 1223 u32 unit; 1224 int i; 1225 1226 unit = dss_feat_get_buffer_size_unit(); 1227 1228 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1229 1230 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1231 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); 1232 size *= unit; 1233 dispc.fifo_size[fifo] = size; 1234 1235 /* 1236 * By default fifos are mapped directly to overlays, fifo 0 to 1237 * ovl 0, fifo 1 to ovl 1, etc. 1238 */ 1239 dispc.fifo_assignment[fifo] = fifo; 1240 } 1241 1242 /* 1243 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1244 * causes problems with certain use cases, like using the tiler in 2D 1245 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1246 * giving GFX plane a larger fifo. WB but should work fine with a 1247 * smaller fifo. 1248 */ 1249 if (dispc.feat->gfx_fifo_workaround) { 1250 u32 v; 1251 1252 v = dispc_read_reg(DISPC_GLOBAL_BUFFER); 1253 1254 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1255 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1256 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1257 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1258 1259 dispc_write_reg(DISPC_GLOBAL_BUFFER, v); 1260 1261 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1262 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1263 } 1264 1265 /* 1266 * Setup default fifo thresholds. 1267 */ 1268 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1269 u32 low, high; 1270 const bool use_fifomerge = false; 1271 const bool manual_update = false; 1272 1273 dispc_ovl_compute_fifo_thresholds(i, &low, &high, 1274 use_fifomerge, manual_update); 1275 1276 dispc_ovl_set_fifo_threshold(i, low, high); 1277 } 1278 1279 if (dispc.feat->has_writeback) { 1280 u32 low, high; 1281 const bool use_fifomerge = false; 1282 const bool manual_update = false; 1283 1284 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, 1285 use_fifomerge, manual_update); 1286 1287 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); 1288 } 1289 } 1290 1291 static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane) 1292 { 1293 int fifo; 1294 u32 size = 0; 1295 1296 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1297 if (dispc.fifo_assignment[fifo] == plane) 1298 size += dispc.fifo_size[fifo]; 1299 } 1300 1301 return size; 1302 } 1303 1304 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 1305 u32 high) 1306 { 1307 u8 hi_start, hi_end, lo_start, lo_end; 1308 u32 unit; 1309 1310 unit = dss_feat_get_buffer_size_unit(); 1311 1312 WARN_ON(low % unit != 0); 1313 WARN_ON(high % unit != 0); 1314 1315 low /= unit; 1316 high /= unit; 1317 1318 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1319 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1320 1321 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1322 plane, 1323 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1324 lo_start, lo_end) * unit, 1325 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1326 hi_start, hi_end) * unit, 1327 low * unit, high * unit); 1328 1329 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1330 FLD_VAL(high, hi_start, hi_end) | 1331 FLD_VAL(low, lo_start, lo_end)); 1332 1333 /* 1334 * configure the preload to the pipeline's high threhold, if HT it's too 1335 * large for the preload field, set the threshold to the maximum value 1336 * that can be held by the preload register 1337 */ 1338 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && 1339 plane != OMAP_DSS_WB) 1340 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); 1341 } 1342 1343 void dispc_enable_fifomerge(bool enable) 1344 { 1345 if (!dss_has_feature(FEAT_FIFO_MERGE)) { 1346 WARN_ON(enable); 1347 return; 1348 } 1349 1350 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1351 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1352 } 1353 1354 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 1355 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1356 bool manual_update) 1357 { 1358 /* 1359 * All sizes are in bytes. Both the buffer and burst are made of 1360 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1361 */ 1362 1363 unsigned buf_unit = dss_feat_get_buffer_size_unit(); 1364 unsigned ovl_fifo_size, total_fifo_size, burst_size; 1365 int i; 1366 1367 burst_size = dispc_ovl_get_burst_size(plane); 1368 ovl_fifo_size = dispc_ovl_get_fifo_size(plane); 1369 1370 if (use_fifomerge) { 1371 total_fifo_size = 0; 1372 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1373 total_fifo_size += dispc_ovl_get_fifo_size(i); 1374 } else { 1375 total_fifo_size = ovl_fifo_size; 1376 } 1377 1378 /* 1379 * We use the same low threshold for both fifomerge and non-fifomerge 1380 * cases, but for fifomerge we calculate the high threshold using the 1381 * combined fifo size 1382 */ 1383 1384 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { 1385 *fifo_low = ovl_fifo_size - burst_size * 2; 1386 *fifo_high = total_fifo_size - burst_size; 1387 } else if (plane == OMAP_DSS_WB) { 1388 /* 1389 * Most optimal configuration for writeback is to push out data 1390 * to the interconnect the moment writeback pushes enough pixels 1391 * in the FIFO to form a burst 1392 */ 1393 *fifo_low = 0; 1394 *fifo_high = burst_size; 1395 } else { 1396 *fifo_low = ovl_fifo_size - burst_size; 1397 *fifo_high = total_fifo_size - buf_unit; 1398 } 1399 } 1400 1401 static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable) 1402 { 1403 int bit; 1404 1405 if (plane == OMAP_DSS_GFX) 1406 bit = 14; 1407 else 1408 bit = 23; 1409 1410 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1411 } 1412 1413 static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane, 1414 int low, int high) 1415 { 1416 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1417 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1418 } 1419 1420 static void dispc_init_mflag(void) 1421 { 1422 int i; 1423 1424 /* 1425 * HACK: NV12 color format and MFLAG seem to have problems working 1426 * together: using two displays, and having an NV12 overlay on one of 1427 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1428 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1429 * remove the errors, but there doesn't seem to be a clear logic on 1430 * which values work and which not. 1431 * 1432 * As a work-around, set force MFLAG to always on. 1433 */ 1434 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1435 (1 << 0) | /* MFLAG_CTRL = force always on */ 1436 (0 << 2)); /* MFLAG_START = disable */ 1437 1438 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1439 u32 size = dispc_ovl_get_fifo_size(i); 1440 u32 unit = dss_feat_get_buffer_size_unit(); 1441 u32 low, high; 1442 1443 dispc_ovl_set_mflag(i, true); 1444 1445 /* 1446 * Simulation team suggests below thesholds: 1447 * HT = fifosize * 5 / 8; 1448 * LT = fifosize * 4 / 8; 1449 */ 1450 1451 low = size * 4 / 8 / unit; 1452 high = size * 5 / 8 / unit; 1453 1454 dispc_ovl_set_mflag_threshold(i, low, high); 1455 } 1456 1457 if (dispc.feat->has_writeback) { 1458 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); 1459 u32 unit = dss_feat_get_buffer_size_unit(); 1460 u32 low, high; 1461 1462 dispc_ovl_set_mflag(OMAP_DSS_WB, true); 1463 1464 /* 1465 * Simulation team suggests below thesholds: 1466 * HT = fifosize * 5 / 8; 1467 * LT = fifosize * 4 / 8; 1468 */ 1469 1470 low = size * 4 / 8 / unit; 1471 high = size * 5 / 8 / unit; 1472 1473 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); 1474 } 1475 } 1476 1477 static void dispc_ovl_set_fir(enum omap_plane_id plane, 1478 int hinc, int vinc, 1479 enum omap_color_component color_comp) 1480 { 1481 u32 val; 1482 1483 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1484 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1485 1486 dss_feat_get_reg_field(FEAT_REG_FIRHINC, 1487 &hinc_start, &hinc_end); 1488 dss_feat_get_reg_field(FEAT_REG_FIRVINC, 1489 &vinc_start, &vinc_end); 1490 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1491 FLD_VAL(hinc, hinc_start, hinc_end); 1492 1493 dispc_write_reg(DISPC_OVL_FIR(plane), val); 1494 } else { 1495 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1496 dispc_write_reg(DISPC_OVL_FIR2(plane), val); 1497 } 1498 } 1499 1500 static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, 1501 int vaccu) 1502 { 1503 u32 val; 1504 u8 hor_start, hor_end, vert_start, vert_end; 1505 1506 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1507 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1508 1509 val = FLD_VAL(vaccu, vert_start, vert_end) | 1510 FLD_VAL(haccu, hor_start, hor_end); 1511 1512 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1513 } 1514 1515 static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, 1516 int vaccu) 1517 { 1518 u32 val; 1519 u8 hor_start, hor_end, vert_start, vert_end; 1520 1521 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1522 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1523 1524 val = FLD_VAL(vaccu, vert_start, vert_end) | 1525 FLD_VAL(haccu, hor_start, hor_end); 1526 1527 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1528 } 1529 1530 static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu, 1531 int vaccu) 1532 { 1533 u32 val; 1534 1535 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1536 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1537 } 1538 1539 static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu, 1540 int vaccu) 1541 { 1542 u32 val; 1543 1544 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1545 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1546 } 1547 1548 static void dispc_ovl_set_scale_param(enum omap_plane_id plane, 1549 u16 orig_width, u16 orig_height, 1550 u16 out_width, u16 out_height, 1551 bool five_taps, u8 rotation, 1552 enum omap_color_component color_comp) 1553 { 1554 int fir_hinc, fir_vinc; 1555 1556 fir_hinc = 1024 * orig_width / out_width; 1557 fir_vinc = 1024 * orig_height / out_height; 1558 1559 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, 1560 color_comp); 1561 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1562 } 1563 1564 static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, 1565 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1566 bool ilace, u32 fourcc, u8 rotation) 1567 { 1568 int h_accu2_0, h_accu2_1; 1569 int v_accu2_0, v_accu2_1; 1570 int chroma_hinc, chroma_vinc; 1571 int idx; 1572 1573 struct accu { 1574 s8 h0_m, h0_n; 1575 s8 h1_m, h1_n; 1576 s8 v0_m, v0_n; 1577 s8 v1_m, v1_n; 1578 }; 1579 1580 const struct accu *accu_table; 1581 const struct accu *accu_val; 1582 1583 static const struct accu accu_nv12[4] = { 1584 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1585 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1586 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1587 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1588 }; 1589 1590 static const struct accu accu_nv12_ilace[4] = { 1591 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1592 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1593 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1594 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1595 }; 1596 1597 static const struct accu accu_yuv[4] = { 1598 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1599 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1600 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1601 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1602 }; 1603 1604 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1605 switch (rotation & DRM_MODE_ROTATE_MASK) { 1606 default: 1607 case DRM_MODE_ROTATE_0: 1608 idx = 0; 1609 break; 1610 case DRM_MODE_ROTATE_90: 1611 idx = 3; 1612 break; 1613 case DRM_MODE_ROTATE_180: 1614 idx = 2; 1615 break; 1616 case DRM_MODE_ROTATE_270: 1617 idx = 1; 1618 break; 1619 } 1620 1621 switch (fourcc) { 1622 case DRM_FORMAT_NV12: 1623 if (ilace) 1624 accu_table = accu_nv12_ilace; 1625 else 1626 accu_table = accu_nv12; 1627 break; 1628 case DRM_FORMAT_YUYV: 1629 case DRM_FORMAT_UYVY: 1630 accu_table = accu_yuv; 1631 break; 1632 default: 1633 BUG(); 1634 return; 1635 } 1636 1637 accu_val = &accu_table[idx]; 1638 1639 chroma_hinc = 1024 * orig_width / out_width; 1640 chroma_vinc = 1024 * orig_height / out_height; 1641 1642 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1643 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1644 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1645 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1646 1647 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); 1648 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1649 } 1650 1651 static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, 1652 u16 orig_width, u16 orig_height, 1653 u16 out_width, u16 out_height, 1654 bool ilace, bool five_taps, 1655 bool fieldmode, u32 fourcc, 1656 u8 rotation) 1657 { 1658 int accu0 = 0; 1659 int accu1 = 0; 1660 u32 l; 1661 1662 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1663 out_width, out_height, five_taps, 1664 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1665 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1666 1667 /* RESIZEENABLE and VERTICALTAPS */ 1668 l &= ~((0x3 << 5) | (0x1 << 21)); 1669 l |= (orig_width != out_width) ? (1 << 5) : 0; 1670 l |= (orig_height != out_height) ? (1 << 6) : 0; 1671 l |= five_taps ? (1 << 21) : 0; 1672 1673 /* VRESIZECONF and HRESIZECONF */ 1674 if (dss_has_feature(FEAT_RESIZECONF)) { 1675 l &= ~(0x3 << 7); 1676 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1677 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1678 } 1679 1680 /* LINEBUFFERSPLIT */ 1681 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { 1682 l &= ~(0x1 << 22); 1683 l |= five_taps ? (1 << 22) : 0; 1684 } 1685 1686 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 1687 1688 /* 1689 * field 0 = even field = bottom field 1690 * field 1 = odd field = top field 1691 */ 1692 if (ilace && !fieldmode) { 1693 accu1 = 0; 1694 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1695 if (accu0 >= 1024/2) { 1696 accu1 = 1024/2; 1697 accu0 -= accu1; 1698 } 1699 } 1700 1701 dispc_ovl_set_vid_accu0(plane, 0, accu0); 1702 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1703 } 1704 1705 static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, 1706 u16 orig_width, u16 orig_height, 1707 u16 out_width, u16 out_height, 1708 bool ilace, bool five_taps, 1709 bool fieldmode, u32 fourcc, 1710 u8 rotation) 1711 { 1712 int scale_x = out_width != orig_width; 1713 int scale_y = out_height != orig_height; 1714 bool chroma_upscale = plane != OMAP_DSS_WB; 1715 1716 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1717 return; 1718 1719 if (!format_is_yuv(fourcc)) { 1720 /* reset chroma resampling for RGB formats */ 1721 if (plane != OMAP_DSS_WB) 1722 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); 1723 return; 1724 } 1725 1726 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, 1727 out_height, ilace, fourcc, rotation); 1728 1729 switch (fourcc) { 1730 case DRM_FORMAT_NV12: 1731 if (chroma_upscale) { 1732 /* UV is subsampled by 2 horizontally and vertically */ 1733 orig_height >>= 1; 1734 orig_width >>= 1; 1735 } else { 1736 /* UV is downsampled by 2 horizontally and vertically */ 1737 orig_height <<= 1; 1738 orig_width <<= 1; 1739 } 1740 1741 break; 1742 case DRM_FORMAT_YUYV: 1743 case DRM_FORMAT_UYVY: 1744 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1745 if (!drm_rotation_90_or_270(rotation)) { 1746 if (chroma_upscale) 1747 /* UV is subsampled by 2 horizontally */ 1748 orig_width >>= 1; 1749 else 1750 /* UV is downsampled by 2 horizontally */ 1751 orig_width <<= 1; 1752 } 1753 1754 /* must use FIR for YUV422 if rotated */ 1755 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0) 1756 scale_x = scale_y = true; 1757 1758 break; 1759 default: 1760 BUG(); 1761 return; 1762 } 1763 1764 if (out_width != orig_width) 1765 scale_x = true; 1766 if (out_height != orig_height) 1767 scale_y = true; 1768 1769 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1770 out_width, out_height, five_taps, 1771 rotation, DISPC_COLOR_COMPONENT_UV); 1772 1773 if (plane != OMAP_DSS_WB) 1774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 1775 (scale_x || scale_y) ? 1 : 0, 8, 8); 1776 1777 /* set H scaling */ 1778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1779 /* set V scaling */ 1780 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1781 } 1782 1783 static void dispc_ovl_set_scaling(enum omap_plane_id plane, 1784 u16 orig_width, u16 orig_height, 1785 u16 out_width, u16 out_height, 1786 bool ilace, bool five_taps, 1787 bool fieldmode, u32 fourcc, 1788 u8 rotation) 1789 { 1790 BUG_ON(plane == OMAP_DSS_GFX); 1791 1792 dispc_ovl_set_scaling_common(plane, 1793 orig_width, orig_height, 1794 out_width, out_height, 1795 ilace, five_taps, 1796 fieldmode, fourcc, 1797 rotation); 1798 1799 dispc_ovl_set_scaling_uv(plane, 1800 orig_width, orig_height, 1801 out_width, out_height, 1802 ilace, five_taps, 1803 fieldmode, fourcc, 1804 rotation); 1805 } 1806 1807 static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, 1808 enum omap_dss_rotation_type rotation_type, u32 fourcc) 1809 { 1810 bool row_repeat = false; 1811 int vidrot = 0; 1812 1813 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ 1814 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) { 1815 1816 if (rotation & DRM_MODE_REFLECT_X) { 1817 switch (rotation & DRM_MODE_ROTATE_MASK) { 1818 case DRM_MODE_ROTATE_0: 1819 vidrot = 2; 1820 break; 1821 case DRM_MODE_ROTATE_90: 1822 vidrot = 1; 1823 break; 1824 case DRM_MODE_ROTATE_180: 1825 vidrot = 0; 1826 break; 1827 case DRM_MODE_ROTATE_270: 1828 vidrot = 3; 1829 break; 1830 } 1831 } else { 1832 switch (rotation & DRM_MODE_ROTATE_MASK) { 1833 case DRM_MODE_ROTATE_0: 1834 vidrot = 0; 1835 break; 1836 case DRM_MODE_ROTATE_90: 1837 vidrot = 3; 1838 break; 1839 case DRM_MODE_ROTATE_180: 1840 vidrot = 2; 1841 break; 1842 case DRM_MODE_ROTATE_270: 1843 vidrot = 1; 1844 break; 1845 } 1846 } 1847 1848 if (drm_rotation_90_or_270(rotation)) 1849 row_repeat = true; 1850 else 1851 row_repeat = false; 1852 } 1853 1854 /* 1855 * OMAP4/5 Errata i631: 1856 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 1857 * rows beyond the framebuffer, which may cause OCP error. 1858 */ 1859 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) 1860 vidrot = 1; 1861 1862 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 1863 if (dss_has_feature(FEAT_ROWREPEATENABLE)) 1864 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1865 row_repeat ? 1 : 0, 18, 18); 1866 1867 if (dss_feat_color_mode_supported(plane, DRM_FORMAT_NV12)) { 1868 bool doublestride = 1869 fourcc == DRM_FORMAT_NV12 && 1870 rotation_type == OMAP_DSS_ROT_TILER && 1871 !drm_rotation_90_or_270(rotation); 1872 1873 /* DOUBLESTRIDE */ 1874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); 1875 } 1876 } 1877 1878 static int color_mode_to_bpp(u32 fourcc) 1879 { 1880 switch (fourcc) { 1881 case DRM_FORMAT_NV12: 1882 return 8; 1883 case DRM_FORMAT_RGBX4444: 1884 case DRM_FORMAT_RGB565: 1885 case DRM_FORMAT_ARGB4444: 1886 case DRM_FORMAT_YUYV: 1887 case DRM_FORMAT_UYVY: 1888 case DRM_FORMAT_RGBA4444: 1889 case DRM_FORMAT_XRGB4444: 1890 case DRM_FORMAT_ARGB1555: 1891 case DRM_FORMAT_XRGB1555: 1892 return 16; 1893 case DRM_FORMAT_RGB888: 1894 return 24; 1895 case DRM_FORMAT_XRGB8888: 1896 case DRM_FORMAT_ARGB8888: 1897 case DRM_FORMAT_RGBA8888: 1898 case DRM_FORMAT_RGBX8888: 1899 return 32; 1900 default: 1901 BUG(); 1902 return 0; 1903 } 1904 } 1905 1906 static s32 pixinc(int pixels, u8 ps) 1907 { 1908 if (pixels == 1) 1909 return 1; 1910 else if (pixels > 1) 1911 return 1 + (pixels - 1) * ps; 1912 else if (pixels < 0) 1913 return 1 - (-pixels + 1) * ps; 1914 else 1915 BUG(); 1916 return 0; 1917 } 1918 1919 static void calc_offset(u16 screen_width, u16 width, 1920 u32 fourcc, bool fieldmode, 1921 unsigned int field_offset, unsigned *offset0, unsigned *offset1, 1922 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, 1923 enum omap_dss_rotation_type rotation_type, u8 rotation) 1924 { 1925 u8 ps; 1926 1927 ps = color_mode_to_bpp(fourcc) / 8; 1928 1929 DSSDBG("scrw %d, width %d\n", screen_width, width); 1930 1931 if (rotation_type == OMAP_DSS_ROT_TILER && 1932 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && 1933 drm_rotation_90_or_270(rotation)) { 1934 /* 1935 * HACK: ROW_INC needs to be calculated with TILER units. 1936 * We get such 'screen_width' that multiplying it with the 1937 * YUV422 pixel size gives the correct TILER container width. 1938 * However, 'width' is in pixels and multiplying it with YUV422 1939 * pixel size gives incorrect result. We thus multiply it here 1940 * with 2 to match the 32 bit TILER unit size. 1941 */ 1942 width *= 2; 1943 } 1944 1945 /* 1946 * field 0 = even field = bottom field 1947 * field 1 = odd field = top field 1948 */ 1949 *offset0 = field_offset * screen_width * ps; 1950 *offset1 = 0; 1951 1952 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 1953 (fieldmode ? screen_width : 0), ps); 1954 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) 1955 *pix_inc = pixinc(x_predecim, 2 * ps); 1956 else 1957 *pix_inc = pixinc(x_predecim, ps); 1958 } 1959 1960 /* 1961 * This function is used to avoid synclosts in OMAP3, because of some 1962 * undocumented horizontal position and timing related limitations. 1963 */ 1964 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 1965 const struct videomode *vm, u16 pos_x, 1966 u16 width, u16 height, u16 out_width, u16 out_height, 1967 bool five_taps) 1968 { 1969 const int ds = DIV_ROUND_UP(height, out_height); 1970 unsigned long nonactive; 1971 static const u8 limits[3] = { 8, 10, 20 }; 1972 u64 val, blank; 1973 int i; 1974 1975 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + 1976 vm->hback_porch - out_width; 1977 1978 i = 0; 1979 if (out_height < height) 1980 i++; 1981 if (out_width < width) 1982 i++; 1983 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * 1984 lclk, pclk); 1985 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 1986 if (blank <= limits[i]) 1987 return -EINVAL; 1988 1989 /* FIXME add checks for 3-tap filter once the limitations are known */ 1990 if (!five_taps) 1991 return 0; 1992 1993 /* 1994 * Pixel data should be prepared before visible display point starts. 1995 * So, atleast DS-2 lines must have already been fetched by DISPC 1996 * during nonactive - pos_x period. 1997 */ 1998 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 1999 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2000 val, max(0, ds - 2) * width); 2001 if (val < max(0, ds - 2) * width) 2002 return -EINVAL; 2003 2004 /* 2005 * All lines need to be refilled during the nonactive period of which 2006 * only one line can be loaded during the active period. So, atleast 2007 * DS - 1 lines should be loaded during nonactive period. 2008 */ 2009 val = div_u64((u64)nonactive * lclk, pclk); 2010 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2011 val, max(0, ds - 1) * width); 2012 if (val < max(0, ds - 1) * width) 2013 return -EINVAL; 2014 2015 return 0; 2016 } 2017 2018 static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2019 const struct videomode *vm, u16 width, 2020 u16 height, u16 out_width, u16 out_height, 2021 u32 fourcc) 2022 { 2023 u32 core_clk = 0; 2024 u64 tmp; 2025 2026 if (height <= out_height && width <= out_width) 2027 return (unsigned long) pclk; 2028 2029 if (height > out_height) { 2030 unsigned int ppl = vm->hactive; 2031 2032 tmp = (u64)pclk * height * out_width; 2033 do_div(tmp, 2 * out_height * ppl); 2034 core_clk = tmp; 2035 2036 if (height > 2 * out_height) { 2037 if (ppl == out_width) 2038 return 0; 2039 2040 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2041 do_div(tmp, 2 * out_height * (ppl - out_width)); 2042 core_clk = max_t(u32, core_clk, tmp); 2043 } 2044 } 2045 2046 if (width > out_width) { 2047 tmp = (u64)pclk * width; 2048 do_div(tmp, out_width); 2049 core_clk = max_t(u32, core_clk, tmp); 2050 2051 if (fourcc == DRM_FORMAT_XRGB8888) 2052 core_clk <<= 1; 2053 } 2054 2055 return core_clk; 2056 } 2057 2058 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2059 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2060 { 2061 if (height > out_height && width > out_width) 2062 return pclk * 4; 2063 else 2064 return pclk * 2; 2065 } 2066 2067 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2068 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2069 { 2070 unsigned int hf, vf; 2071 2072 /* 2073 * FIXME how to determine the 'A' factor 2074 * for the no downscaling case ? 2075 */ 2076 2077 if (width > 3 * out_width) 2078 hf = 4; 2079 else if (width > 2 * out_width) 2080 hf = 3; 2081 else if (width > out_width) 2082 hf = 2; 2083 else 2084 hf = 1; 2085 if (height > out_height) 2086 vf = 2; 2087 else 2088 vf = 1; 2089 2090 return pclk * vf * hf; 2091 } 2092 2093 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2094 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2095 { 2096 /* 2097 * If the overlay/writeback is in mem to mem mode, there are no 2098 * downscaling limitations with respect to pixel clock, return 1 as 2099 * required core clock to represent that we have sufficient enough 2100 * core clock to do maximum downscaling 2101 */ 2102 if (mem_to_mem) 2103 return 1; 2104 2105 if (width > out_width) 2106 return DIV_ROUND_UP(pclk, out_width) * width; 2107 else 2108 return pclk; 2109 } 2110 2111 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2112 const struct videomode *vm, 2113 u16 width, u16 height, u16 out_width, u16 out_height, 2114 u32 fourcc, bool *five_taps, 2115 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2116 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2117 { 2118 int error; 2119 u16 in_width, in_height; 2120 int min_factor = min(*decim_x, *decim_y); 2121 const int maxsinglelinewidth = 2122 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2123 2124 *five_taps = false; 2125 2126 do { 2127 in_height = height / *decim_y; 2128 in_width = width / *decim_x; 2129 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2130 in_height, out_width, out_height, mem_to_mem); 2131 error = (in_width > maxsinglelinewidth || !*core_clk || 2132 *core_clk > dispc_core_clk_rate()); 2133 if (error) { 2134 if (*decim_x == *decim_y) { 2135 *decim_x = min_factor; 2136 ++*decim_y; 2137 } else { 2138 swap(*decim_x, *decim_y); 2139 if (*decim_x < *decim_y) 2140 ++*decim_x; 2141 } 2142 } 2143 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2144 2145 if (error) { 2146 DSSERR("failed to find scaling settings\n"); 2147 return -EINVAL; 2148 } 2149 2150 if (in_width > maxsinglelinewidth) { 2151 DSSERR("Cannot scale max input width exceeded"); 2152 return -EINVAL; 2153 } 2154 return 0; 2155 } 2156 2157 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2158 const struct videomode *vm, 2159 u16 width, u16 height, u16 out_width, u16 out_height, 2160 u32 fourcc, bool *five_taps, 2161 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2162 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2163 { 2164 int error; 2165 u16 in_width, in_height; 2166 const int maxsinglelinewidth = 2167 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2168 2169 do { 2170 in_height = height / *decim_y; 2171 in_width = width / *decim_x; 2172 *five_taps = in_height > out_height; 2173 2174 if (in_width > maxsinglelinewidth) 2175 if (in_height > out_height && 2176 in_height < out_height * 2) 2177 *five_taps = false; 2178 again: 2179 if (*five_taps) 2180 *core_clk = calc_core_clk_five_taps(pclk, vm, 2181 in_width, in_height, out_width, 2182 out_height, fourcc); 2183 else 2184 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2185 in_height, out_width, out_height, 2186 mem_to_mem); 2187 2188 error = check_horiz_timing_omap3(pclk, lclk, vm, 2189 pos_x, in_width, in_height, out_width, 2190 out_height, *five_taps); 2191 if (error && *five_taps) { 2192 *five_taps = false; 2193 goto again; 2194 } 2195 2196 error = (error || in_width > maxsinglelinewidth * 2 || 2197 (in_width > maxsinglelinewidth && *five_taps) || 2198 !*core_clk || *core_clk > dispc_core_clk_rate()); 2199 2200 if (!error) { 2201 /* verify that we're inside the limits of scaler */ 2202 if (in_width / 4 > out_width) 2203 error = 1; 2204 2205 if (*five_taps) { 2206 if (in_height / 4 > out_height) 2207 error = 1; 2208 } else { 2209 if (in_height / 2 > out_height) 2210 error = 1; 2211 } 2212 } 2213 2214 if (error) 2215 ++*decim_y; 2216 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2217 2218 if (error) { 2219 DSSERR("failed to find scaling settings\n"); 2220 return -EINVAL; 2221 } 2222 2223 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width, 2224 in_height, out_width, out_height, *five_taps)) { 2225 DSSERR("horizontal timing too tight\n"); 2226 return -EINVAL; 2227 } 2228 2229 if (in_width > (maxsinglelinewidth * 2)) { 2230 DSSERR("Cannot setup scaling"); 2231 DSSERR("width exceeds maximum width possible"); 2232 return -EINVAL; 2233 } 2234 2235 if (in_width > maxsinglelinewidth && *five_taps) { 2236 DSSERR("cannot setup scaling with five taps"); 2237 return -EINVAL; 2238 } 2239 return 0; 2240 } 2241 2242 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2243 const struct videomode *vm, 2244 u16 width, u16 height, u16 out_width, u16 out_height, 2245 u32 fourcc, bool *five_taps, 2246 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2247 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2248 { 2249 u16 in_width, in_width_max; 2250 int decim_x_min = *decim_x; 2251 u16 in_height = height / *decim_y; 2252 const int maxsinglelinewidth = 2253 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2254 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2255 2256 if (mem_to_mem) { 2257 in_width_max = out_width * maxdownscale; 2258 } else { 2259 in_width_max = dispc_core_clk_rate() / 2260 DIV_ROUND_UP(pclk, out_width); 2261 } 2262 2263 *decim_x = DIV_ROUND_UP(width, in_width_max); 2264 2265 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; 2266 if (*decim_x > *x_predecim) 2267 return -EINVAL; 2268 2269 do { 2270 in_width = width / *decim_x; 2271 } while (*decim_x <= *x_predecim && 2272 in_width > maxsinglelinewidth && ++*decim_x); 2273 2274 if (in_width > maxsinglelinewidth) { 2275 DSSERR("Cannot scale width exceeds max line width"); 2276 return -EINVAL; 2277 } 2278 2279 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) { 2280 /* 2281 * Let's disable all scaling that requires horizontal 2282 * decimation with higher factor than 4, until we have 2283 * better estimates of what we can and can not 2284 * do. However, NV12 color format appears to work Ok 2285 * with all decimation factors. 2286 * 2287 * When decimating horizontally by more that 4 the dss 2288 * is not able to fetch the data in burst mode. When 2289 * this happens it is hard to tell if there enough 2290 * bandwidth. Despite what theory says this appears to 2291 * be true also for 16-bit color formats. 2292 */ 2293 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x); 2294 2295 return -EINVAL; 2296 } 2297 2298 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, 2299 out_width, out_height, mem_to_mem); 2300 return 0; 2301 } 2302 2303 #define DIV_FRAC(dividend, divisor) \ 2304 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2305 2306 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2307 enum omap_overlay_caps caps, 2308 const struct videomode *vm, 2309 u16 width, u16 height, u16 out_width, u16 out_height, 2310 u32 fourcc, bool *five_taps, 2311 int *x_predecim, int *y_predecim, u16 pos_x, 2312 enum omap_dss_rotation_type rotation_type, bool mem_to_mem) 2313 { 2314 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2315 const int max_decim_limit = 16; 2316 unsigned long core_clk = 0; 2317 int decim_x, decim_y, ret; 2318 2319 if (width == out_width && height == out_height) 2320 return 0; 2321 2322 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { 2323 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2324 return -EINVAL; 2325 } 2326 2327 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2328 return -EINVAL; 2329 2330 if (mem_to_mem) { 2331 *x_predecim = *y_predecim = 1; 2332 } else { 2333 *x_predecim = max_decim_limit; 2334 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2335 dss_has_feature(FEAT_BURST_2D)) ? 2336 2 : max_decim_limit; 2337 } 2338 2339 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); 2340 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); 2341 2342 if (decim_x > *x_predecim || out_width > width * 8) 2343 return -EINVAL; 2344 2345 if (decim_y > *y_predecim || out_height > height * 8) 2346 return -EINVAL; 2347 2348 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height, 2349 out_width, out_height, fourcc, five_taps, 2350 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2351 mem_to_mem); 2352 if (ret) 2353 return ret; 2354 2355 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2356 width, height, 2357 out_width, out_height, 2358 out_width / width, DIV_FRAC(out_width, width), 2359 out_height / height, DIV_FRAC(out_height, height), 2360 2361 decim_x, decim_y, 2362 width / decim_x, height / decim_y, 2363 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2364 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2365 2366 *five_taps ? 5 : 3, 2367 core_clk, dispc_core_clk_rate()); 2368 2369 if (!core_clk || core_clk > dispc_core_clk_rate()) { 2370 DSSERR("failed to set up scaling, " 2371 "required core clk rate = %lu Hz, " 2372 "current core clk rate = %lu Hz\n", 2373 core_clk, dispc_core_clk_rate()); 2374 return -EINVAL; 2375 } 2376 2377 *x_predecim = decim_x; 2378 *y_predecim = decim_y; 2379 return 0; 2380 } 2381 2382 static int dispc_ovl_setup_common(enum omap_plane_id plane, 2383 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2384 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2385 u16 out_width, u16 out_height, u32 fourcc, 2386 u8 rotation, u8 zorder, u8 pre_mult_alpha, 2387 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2388 bool replication, const struct videomode *vm, 2389 bool mem_to_mem) 2390 { 2391 bool five_taps = true; 2392 bool fieldmode = false; 2393 int r, cconv = 0; 2394 unsigned offset0, offset1; 2395 s32 row_inc; 2396 s32 pix_inc; 2397 u16 frame_width, frame_height; 2398 unsigned int field_offset = 0; 2399 u16 in_height = height; 2400 u16 in_width = width; 2401 int x_predecim = 1, y_predecim = 1; 2402 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); 2403 unsigned long pclk = dispc_plane_pclk_rate(plane); 2404 unsigned long lclk = dispc_plane_lclk_rate(plane); 2405 2406 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2407 return -EINVAL; 2408 2409 if (format_is_yuv(fourcc) && (in_width & 1)) { 2410 DSSERR("input width %d is not even for YUV format\n", in_width); 2411 return -EINVAL; 2412 } 2413 2414 out_width = out_width == 0 ? width : out_width; 2415 out_height = out_height == 0 ? height : out_height; 2416 2417 if (ilace && height == out_height) 2418 fieldmode = true; 2419 2420 if (ilace) { 2421 if (fieldmode) 2422 in_height /= 2; 2423 pos_y /= 2; 2424 out_height /= 2; 2425 2426 DSSDBG("adjusting for ilace: height %d, pos_y %d, " 2427 "out_height %d\n", in_height, pos_y, 2428 out_height); 2429 } 2430 2431 if (!dss_feat_color_mode_supported(plane, fourcc)) 2432 return -EINVAL; 2433 2434 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width, 2435 in_height, out_width, out_height, fourcc, 2436 &five_taps, &x_predecim, &y_predecim, pos_x, 2437 rotation_type, mem_to_mem); 2438 if (r) 2439 return r; 2440 2441 in_width = in_width / x_predecim; 2442 in_height = in_height / y_predecim; 2443 2444 if (x_predecim > 1 || y_predecim > 1) 2445 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2446 x_predecim, y_predecim, in_width, in_height); 2447 2448 if (format_is_yuv(fourcc) && (in_width & 1)) { 2449 DSSDBG("predecimated input width is not even for YUV format\n"); 2450 DSSDBG("adjusting input width %d -> %d\n", 2451 in_width, in_width & ~1); 2452 2453 in_width &= ~1; 2454 } 2455 2456 if (format_is_yuv(fourcc)) 2457 cconv = 1; 2458 2459 if (ilace && !fieldmode) { 2460 /* 2461 * when downscaling the bottom field may have to start several 2462 * source lines below the top field. Unfortunately ACCUI 2463 * registers will only hold the fractional part of the offset 2464 * so the integer part must be added to the base address of the 2465 * bottom field. 2466 */ 2467 if (!in_height || in_height == out_height) 2468 field_offset = 0; 2469 else 2470 field_offset = in_height / out_height / 2; 2471 } 2472 2473 /* Fields are independent but interleaved in memory. */ 2474 if (fieldmode) 2475 field_offset = 1; 2476 2477 offset0 = 0; 2478 offset1 = 0; 2479 row_inc = 0; 2480 pix_inc = 0; 2481 2482 if (plane == OMAP_DSS_WB) { 2483 frame_width = out_width; 2484 frame_height = out_height; 2485 } else { 2486 frame_width = in_width; 2487 frame_height = height; 2488 } 2489 2490 calc_offset(screen_width, frame_width, 2491 fourcc, fieldmode, field_offset, 2492 &offset0, &offset1, &row_inc, &pix_inc, 2493 x_predecim, y_predecim, 2494 rotation_type, rotation); 2495 2496 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2497 offset0, offset1, row_inc, pix_inc); 2498 2499 dispc_ovl_set_color_mode(plane, fourcc); 2500 2501 dispc_ovl_configure_burst_type(plane, rotation_type); 2502 2503 if (dispc.feat->reverse_ilace_field_order) 2504 swap(offset0, offset1); 2505 2506 dispc_ovl_set_ba0(plane, paddr + offset0); 2507 dispc_ovl_set_ba1(plane, paddr + offset1); 2508 2509 if (fourcc == DRM_FORMAT_NV12) { 2510 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); 2511 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); 2512 } 2513 2514 if (dispc.feat->last_pixel_inc_missing) 2515 row_inc += pix_inc - 1; 2516 2517 dispc_ovl_set_row_inc(plane, row_inc); 2518 dispc_ovl_set_pix_inc(plane, pix_inc); 2519 2520 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2521 in_height, out_width, out_height); 2522 2523 dispc_ovl_set_pos(plane, caps, pos_x, pos_y); 2524 2525 dispc_ovl_set_input_size(plane, in_width, in_height); 2526 2527 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2528 dispc_ovl_set_scaling(plane, in_width, in_height, out_width, 2529 out_height, ilace, five_taps, fieldmode, 2530 fourcc, rotation); 2531 dispc_ovl_set_output_size(plane, out_width, out_height); 2532 dispc_ovl_set_vid_color_conv(plane, cconv); 2533 } 2534 2535 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc); 2536 2537 dispc_ovl_set_zorder(plane, caps, zorder); 2538 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); 2539 dispc_ovl_setup_global_alpha(plane, caps, global_alpha); 2540 2541 dispc_ovl_enable_replication(plane, caps, replication); 2542 2543 return 0; 2544 } 2545 2546 static int dispc_ovl_setup(enum omap_plane_id plane, 2547 const struct omap_overlay_info *oi, 2548 const struct videomode *vm, bool mem_to_mem, 2549 enum omap_channel channel) 2550 { 2551 int r; 2552 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); 2553 const bool replication = true; 2554 2555 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2556 " %dx%d, cmode %x, rot %d, chan %d repl %d\n", 2557 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2558 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2559 oi->fourcc, oi->rotation, channel, replication); 2560 2561 dispc_ovl_set_channel_out(plane, channel); 2562 2563 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, 2564 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2565 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, 2566 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2567 oi->rotation_type, replication, vm, mem_to_mem); 2568 2569 return r; 2570 } 2571 2572 int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2573 bool mem_to_mem, const struct videomode *vm) 2574 { 2575 int r; 2576 u32 l; 2577 enum omap_plane_id plane = OMAP_DSS_WB; 2578 const int pos_x = 0, pos_y = 0; 2579 const u8 zorder = 0, global_alpha = 0; 2580 const bool replication = true; 2581 bool truncation; 2582 int in_width = vm->hactive; 2583 int in_height = vm->vactive; 2584 enum omap_overlay_caps caps = 2585 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2586 2587 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " 2588 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, 2589 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); 2590 2591 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, 2592 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2593 wi->height, wi->fourcc, wi->rotation, zorder, 2594 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2595 replication, vm, mem_to_mem); 2596 2597 switch (wi->fourcc) { 2598 case DRM_FORMAT_RGB565: 2599 case DRM_FORMAT_RGB888: 2600 case DRM_FORMAT_ARGB4444: 2601 case DRM_FORMAT_RGBA4444: 2602 case DRM_FORMAT_RGBX4444: 2603 case DRM_FORMAT_ARGB1555: 2604 case DRM_FORMAT_XRGB1555: 2605 case DRM_FORMAT_XRGB4444: 2606 truncation = true; 2607 break; 2608 default: 2609 truncation = false; 2610 break; 2611 } 2612 2613 /* setup extra DISPC_WB_ATTRIBUTES */ 2614 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 2615 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ 2616 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ 2617 if (mem_to_mem) 2618 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ 2619 else 2620 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ 2621 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 2622 2623 if (mem_to_mem) { 2624 /* WBDELAYCOUNT */ 2625 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); 2626 } else { 2627 int wbdelay; 2628 2629 wbdelay = min(vm->vfront_porch + 2630 vm->vsync_len + vm->vback_porch, (u32)255); 2631 2632 /* WBDELAYCOUNT */ 2633 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2634 } 2635 2636 return r; 2637 } 2638 2639 static int dispc_ovl_enable(enum omap_plane_id plane, bool enable) 2640 { 2641 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2642 2643 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2644 2645 return 0; 2646 } 2647 2648 static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) 2649 { 2650 return dss_feat_get_supported_outputs(channel); 2651 } 2652 2653 static void dispc_lcd_enable_signal_polarity(bool act_high) 2654 { 2655 if (!dss_has_feature(FEAT_LCDENABLEPOL)) 2656 return; 2657 2658 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2659 } 2660 2661 void dispc_lcd_enable_signal(bool enable) 2662 { 2663 if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) 2664 return; 2665 2666 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2667 } 2668 2669 void dispc_pck_free_enable(bool enable) 2670 { 2671 if (!dss_has_feature(FEAT_PCKFREEENABLE)) 2672 return; 2673 2674 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2675 } 2676 2677 static int dispc_get_num_mgrs(void) 2678 { 2679 return dss_feat_get_num_mgrs(); 2680 } 2681 2682 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2683 { 2684 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2685 } 2686 2687 2688 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2689 { 2690 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2691 } 2692 2693 static void dispc_set_loadmode(enum omap_dss_load_mode mode) 2694 { 2695 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2696 } 2697 2698 2699 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) 2700 { 2701 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2702 } 2703 2704 static void dispc_mgr_set_trans_key(enum omap_channel ch, 2705 enum omap_dss_trans_key_type type, 2706 u32 trans_key) 2707 { 2708 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); 2709 2710 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2711 } 2712 2713 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2714 { 2715 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); 2716 } 2717 2718 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2719 bool enable) 2720 { 2721 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) 2722 return; 2723 2724 if (ch == OMAP_DSS_CHANNEL_LCD) 2725 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2726 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2727 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2728 } 2729 2730 static void dispc_mgr_setup(enum omap_channel channel, 2731 const struct omap_overlay_manager_info *info) 2732 { 2733 dispc_mgr_set_default_color(channel, info->default_color); 2734 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); 2735 dispc_mgr_enable_trans_key(channel, info->trans_enabled); 2736 dispc_mgr_enable_alpha_fixed_zorder(channel, 2737 info->partial_alpha_enabled); 2738 if (dss_has_feature(FEAT_CPR)) { 2739 dispc_mgr_enable_cpr(channel, info->cpr_enable); 2740 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 2741 } 2742 } 2743 2744 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2745 { 2746 int code; 2747 2748 switch (data_lines) { 2749 case 12: 2750 code = 0; 2751 break; 2752 case 16: 2753 code = 1; 2754 break; 2755 case 18: 2756 code = 2; 2757 break; 2758 case 24: 2759 code = 3; 2760 break; 2761 default: 2762 BUG(); 2763 return; 2764 } 2765 2766 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 2767 } 2768 2769 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2770 { 2771 u32 l; 2772 int gpout0, gpout1; 2773 2774 switch (mode) { 2775 case DSS_IO_PAD_MODE_RESET: 2776 gpout0 = 0; 2777 gpout1 = 0; 2778 break; 2779 case DSS_IO_PAD_MODE_RFBI: 2780 gpout0 = 1; 2781 gpout1 = 0; 2782 break; 2783 case DSS_IO_PAD_MODE_BYPASS: 2784 gpout0 = 1; 2785 gpout1 = 1; 2786 break; 2787 default: 2788 BUG(); 2789 return; 2790 } 2791 2792 l = dispc_read_reg(DISPC_CONTROL); 2793 l = FLD_MOD(l, gpout0, 15, 15); 2794 l = FLD_MOD(l, gpout1, 16, 16); 2795 dispc_write_reg(DISPC_CONTROL, l); 2796 } 2797 2798 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2799 { 2800 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 2801 } 2802 2803 static void dispc_mgr_set_lcd_config(enum omap_channel channel, 2804 const struct dss_lcd_mgr_config *config) 2805 { 2806 dispc_mgr_set_io_pad_mode(config->io_pad_mode); 2807 2808 dispc_mgr_enable_stallmode(channel, config->stallmode); 2809 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); 2810 2811 dispc_mgr_set_clock_div(channel, &config->clock_info); 2812 2813 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); 2814 2815 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); 2816 2817 dispc_mgr_set_lcd_type_tft(channel); 2818 } 2819 2820 static bool _dispc_mgr_size_ok(u16 width, u16 height) 2821 { 2822 return width <= dispc.feat->mgr_width_max && 2823 height <= dispc.feat->mgr_height_max; 2824 } 2825 2826 static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp, 2827 int vsw, int vfp, int vbp) 2828 { 2829 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max || 2830 hfp < 1 || hfp > dispc.feat->hp_max || 2831 hbp < 1 || hbp > dispc.feat->hp_max || 2832 vsw < 1 || vsw > dispc.feat->sw_max || 2833 vfp < 0 || vfp > dispc.feat->vp_max || 2834 vbp < 0 || vbp > dispc.feat->vp_max) 2835 return false; 2836 return true; 2837 } 2838 2839 static bool _dispc_mgr_pclk_ok(enum omap_channel channel, 2840 unsigned long pclk) 2841 { 2842 if (dss_mgr_is_lcd(channel)) 2843 return pclk <= dispc.feat->max_lcd_pclk; 2844 else 2845 return pclk <= dispc.feat->max_tv_pclk; 2846 } 2847 2848 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm) 2849 { 2850 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive)) 2851 return false; 2852 2853 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock)) 2854 return false; 2855 2856 if (dss_mgr_is_lcd(channel)) { 2857 /* TODO: OMAP4+ supports interlace for LCD outputs */ 2858 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 2859 return false; 2860 2861 if (!_dispc_lcd_timings_ok(vm->hsync_len, 2862 vm->hfront_porch, vm->hback_porch, 2863 vm->vsync_len, vm->vfront_porch, 2864 vm->vback_porch)) 2865 return false; 2866 } 2867 2868 return true; 2869 } 2870 2871 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, 2872 const struct videomode *vm) 2873 { 2874 u32 timing_h, timing_v, l; 2875 bool onoff, rf, ipc, vs, hs, de; 2876 2877 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) | 2878 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) | 2879 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20); 2880 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) | 2881 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) | 2882 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20); 2883 2884 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 2885 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 2886 2887 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH) 2888 vs = false; 2889 else 2890 vs = true; 2891 2892 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH) 2893 hs = false; 2894 else 2895 hs = true; 2896 2897 if (vm->flags & DISPLAY_FLAGS_DE_HIGH) 2898 de = false; 2899 else 2900 de = true; 2901 2902 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 2903 ipc = false; 2904 else 2905 ipc = true; 2906 2907 /* always use the 'rf' setting */ 2908 onoff = true; 2909 2910 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE) 2911 rf = true; 2912 else 2913 rf = false; 2914 2915 l = FLD_VAL(onoff, 17, 17) | 2916 FLD_VAL(rf, 16, 16) | 2917 FLD_VAL(de, 15, 15) | 2918 FLD_VAL(ipc, 14, 14) | 2919 FLD_VAL(hs, 13, 13) | 2920 FLD_VAL(vs, 12, 12); 2921 2922 /* always set ALIGN bit when available */ 2923 if (dispc.feat->supports_sync_align) 2924 l |= (1 << 18); 2925 2926 dispc_write_reg(DISPC_POL_FREQ(channel), l); 2927 2928 if (dispc.syscon_pol) { 2929 const int shifts[] = { 2930 [OMAP_DSS_CHANNEL_LCD] = 0, 2931 [OMAP_DSS_CHANNEL_LCD2] = 1, 2932 [OMAP_DSS_CHANNEL_LCD3] = 2, 2933 }; 2934 2935 u32 mask, val; 2936 2937 mask = (1 << 0) | (1 << 3) | (1 << 6); 2938 val = (rf << 0) | (ipc << 3) | (onoff << 6); 2939 2940 mask <<= 16 + shifts[channel]; 2941 val <<= 16 + shifts[channel]; 2942 2943 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, 2944 mask, val); 2945 } 2946 } 2947 2948 static int vm_flag_to_int(enum display_flags flags, enum display_flags high, 2949 enum display_flags low) 2950 { 2951 if (flags & high) 2952 return 1; 2953 if (flags & low) 2954 return -1; 2955 return 0; 2956 } 2957 2958 /* change name to mode? */ 2959 static void dispc_mgr_set_timings(enum omap_channel channel, 2960 const struct videomode *vm) 2961 { 2962 unsigned xtot, ytot; 2963 unsigned long ht, vt; 2964 struct videomode t = *vm; 2965 2966 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 2967 2968 if (!dispc_mgr_timings_ok(channel, &t)) { 2969 BUG(); 2970 return; 2971 } 2972 2973 if (dss_mgr_is_lcd(channel)) { 2974 _dispc_mgr_set_lcd_timings(channel, &t); 2975 2976 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 2977 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 2978 2979 ht = vm->pixelclock / xtot; 2980 vt = vm->pixelclock / xtot / ytot; 2981 2982 DSSDBG("pck %lu\n", vm->pixelclock); 2983 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 2984 t.hsync_len, t.hfront_porch, t.hback_porch, 2985 t.vsync_len, t.vfront_porch, t.vback_porch); 2986 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 2987 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW), 2988 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW), 2989 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE), 2990 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW), 2991 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE)); 2992 2993 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 2994 } else { 2995 if (t.flags & DISPLAY_FLAGS_INTERLACED) 2996 t.vactive /= 2; 2997 2998 if (dispc.feat->supports_double_pixel) 2999 REG_FLD_MOD(DISPC_CONTROL, 3000 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), 3001 19, 17); 3002 } 3003 3004 dispc_mgr_set_size(channel, t.hactive, t.vactive); 3005 } 3006 3007 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 3008 u16 pck_div) 3009 { 3010 BUG_ON(lck_div < 1); 3011 BUG_ON(pck_div < 1); 3012 3013 dispc_write_reg(DISPC_DIVISORo(channel), 3014 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3015 3016 if (!dss_has_feature(FEAT_CORE_CLK_DIV) && 3017 channel == OMAP_DSS_CHANNEL_LCD) 3018 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; 3019 } 3020 3021 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, 3022 int *pck_div) 3023 { 3024 u32 l; 3025 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3026 *lck_div = FLD_GET(l, 23, 16); 3027 *pck_div = FLD_GET(l, 7, 0); 3028 } 3029 3030 static unsigned long dispc_fclk_rate(void) 3031 { 3032 unsigned long r; 3033 enum dss_clk_source src; 3034 3035 src = dss_get_dispc_clk_source(); 3036 3037 if (src == DSS_CLK_SRC_FCK) { 3038 r = dss_get_dispc_clk_rate(); 3039 } else { 3040 struct dss_pll *pll; 3041 unsigned clkout_idx; 3042 3043 pll = dss_pll_find_by_src(src); 3044 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3045 3046 r = pll->cinfo.clkout[clkout_idx]; 3047 } 3048 3049 return r; 3050 } 3051 3052 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3053 { 3054 int lcd; 3055 unsigned long r; 3056 enum dss_clk_source src; 3057 3058 /* for TV, LCLK rate is the FCLK rate */ 3059 if (!dss_mgr_is_lcd(channel)) 3060 return dispc_fclk_rate(); 3061 3062 src = dss_get_lcd_clk_source(channel); 3063 3064 if (src == DSS_CLK_SRC_FCK) { 3065 r = dss_get_dispc_clk_rate(); 3066 } else { 3067 struct dss_pll *pll; 3068 unsigned clkout_idx; 3069 3070 pll = dss_pll_find_by_src(src); 3071 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3072 3073 r = pll->cinfo.clkout[clkout_idx]; 3074 } 3075 3076 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3077 3078 return r / lcd; 3079 } 3080 3081 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) 3082 { 3083 unsigned long r; 3084 3085 if (dss_mgr_is_lcd(channel)) { 3086 int pcd; 3087 u32 l; 3088 3089 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3090 3091 pcd = FLD_GET(l, 7, 0); 3092 3093 r = dispc_mgr_lclk_rate(channel); 3094 3095 return r / pcd; 3096 } else { 3097 return dispc.tv_pclk_rate; 3098 } 3099 } 3100 3101 void dispc_set_tv_pclk(unsigned long pclk) 3102 { 3103 dispc.tv_pclk_rate = pclk; 3104 } 3105 3106 static unsigned long dispc_core_clk_rate(void) 3107 { 3108 return dispc.core_clk_rate; 3109 } 3110 3111 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane) 3112 { 3113 enum omap_channel channel; 3114 3115 if (plane == OMAP_DSS_WB) 3116 return 0; 3117 3118 channel = dispc_ovl_get_channel_out(plane); 3119 3120 return dispc_mgr_pclk_rate(channel); 3121 } 3122 3123 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane) 3124 { 3125 enum omap_channel channel; 3126 3127 if (plane == OMAP_DSS_WB) 3128 return 0; 3129 3130 channel = dispc_ovl_get_channel_out(plane); 3131 3132 return dispc_mgr_lclk_rate(channel); 3133 } 3134 3135 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3136 { 3137 int lcd, pcd; 3138 enum dss_clk_source lcd_clk_src; 3139 3140 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3141 3142 lcd_clk_src = dss_get_lcd_clk_source(channel); 3143 3144 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3145 dss_get_clk_source_name(lcd_clk_src)); 3146 3147 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3148 3149 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3150 dispc_mgr_lclk_rate(channel), lcd); 3151 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3152 dispc_mgr_pclk_rate(channel), pcd); 3153 } 3154 3155 void dispc_dump_clocks(struct seq_file *s) 3156 { 3157 int lcd; 3158 u32 l; 3159 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3160 3161 if (dispc_runtime_get()) 3162 return; 3163 3164 seq_printf(s, "- DISPC -\n"); 3165 3166 seq_printf(s, "dispc fclk source = %s\n", 3167 dss_get_clk_source_name(dispc_clk_src)); 3168 3169 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3170 3171 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3172 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3173 l = dispc_read_reg(DISPC_DIVISOR); 3174 lcd = FLD_GET(l, 23, 16); 3175 3176 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3177 (dispc_fclk_rate()/lcd), lcd); 3178 } 3179 3180 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); 3181 3182 if (dss_has_feature(FEAT_MGR_LCD2)) 3183 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); 3184 if (dss_has_feature(FEAT_MGR_LCD3)) 3185 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); 3186 3187 dispc_runtime_put(); 3188 } 3189 3190 static void dispc_dump_regs(struct seq_file *s) 3191 { 3192 int i, j; 3193 const char *mgr_names[] = { 3194 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3195 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3196 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3197 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3198 }; 3199 const char *ovl_names[] = { 3200 [OMAP_DSS_GFX] = "GFX", 3201 [OMAP_DSS_VIDEO1] = "VID1", 3202 [OMAP_DSS_VIDEO2] = "VID2", 3203 [OMAP_DSS_VIDEO3] = "VID3", 3204 [OMAP_DSS_WB] = "WB", 3205 }; 3206 const char **p_names; 3207 3208 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) 3209 3210 if (dispc_runtime_get()) 3211 return; 3212 3213 /* DISPC common registers */ 3214 DUMPREG(DISPC_REVISION); 3215 DUMPREG(DISPC_SYSCONFIG); 3216 DUMPREG(DISPC_SYSSTATUS); 3217 DUMPREG(DISPC_IRQSTATUS); 3218 DUMPREG(DISPC_IRQENABLE); 3219 DUMPREG(DISPC_CONTROL); 3220 DUMPREG(DISPC_CONFIG); 3221 DUMPREG(DISPC_CAPABLE); 3222 DUMPREG(DISPC_LINE_STATUS); 3223 DUMPREG(DISPC_LINE_NUMBER); 3224 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 3225 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 3226 DUMPREG(DISPC_GLOBAL_ALPHA); 3227 if (dss_has_feature(FEAT_MGR_LCD2)) { 3228 DUMPREG(DISPC_CONTROL2); 3229 DUMPREG(DISPC_CONFIG2); 3230 } 3231 if (dss_has_feature(FEAT_MGR_LCD3)) { 3232 DUMPREG(DISPC_CONTROL3); 3233 DUMPREG(DISPC_CONFIG3); 3234 } 3235 if (dss_has_feature(FEAT_MFLAG)) 3236 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3237 3238 #undef DUMPREG 3239 3240 #define DISPC_REG(i, name) name(i) 3241 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3242 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3243 dispc_read_reg(DISPC_REG(i, r))) 3244 3245 p_names = mgr_names; 3246 3247 /* DISPC channel specific registers */ 3248 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 3249 DUMPREG(i, DISPC_DEFAULT_COLOR); 3250 DUMPREG(i, DISPC_TRANS_COLOR); 3251 DUMPREG(i, DISPC_SIZE_MGR); 3252 3253 if (i == OMAP_DSS_CHANNEL_DIGIT) 3254 continue; 3255 3256 DUMPREG(i, DISPC_TIMING_H); 3257 DUMPREG(i, DISPC_TIMING_V); 3258 DUMPREG(i, DISPC_POL_FREQ); 3259 DUMPREG(i, DISPC_DIVISORo); 3260 3261 DUMPREG(i, DISPC_DATA_CYCLE1); 3262 DUMPREG(i, DISPC_DATA_CYCLE2); 3263 DUMPREG(i, DISPC_DATA_CYCLE3); 3264 3265 if (dss_has_feature(FEAT_CPR)) { 3266 DUMPREG(i, DISPC_CPR_COEF_R); 3267 DUMPREG(i, DISPC_CPR_COEF_G); 3268 DUMPREG(i, DISPC_CPR_COEF_B); 3269 } 3270 } 3271 3272 p_names = ovl_names; 3273 3274 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 3275 DUMPREG(i, DISPC_OVL_BA0); 3276 DUMPREG(i, DISPC_OVL_BA1); 3277 DUMPREG(i, DISPC_OVL_POSITION); 3278 DUMPREG(i, DISPC_OVL_SIZE); 3279 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3280 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3281 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3282 DUMPREG(i, DISPC_OVL_ROW_INC); 3283 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3284 3285 if (dss_has_feature(FEAT_PRELOAD)) 3286 DUMPREG(i, DISPC_OVL_PRELOAD); 3287 if (dss_has_feature(FEAT_MFLAG)) 3288 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3289 3290 if (i == OMAP_DSS_GFX) { 3291 DUMPREG(i, DISPC_OVL_WINDOW_SKIP); 3292 DUMPREG(i, DISPC_OVL_TABLE_BA); 3293 continue; 3294 } 3295 3296 DUMPREG(i, DISPC_OVL_FIR); 3297 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3298 DUMPREG(i, DISPC_OVL_ACCU0); 3299 DUMPREG(i, DISPC_OVL_ACCU1); 3300 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3301 DUMPREG(i, DISPC_OVL_BA0_UV); 3302 DUMPREG(i, DISPC_OVL_BA1_UV); 3303 DUMPREG(i, DISPC_OVL_FIR2); 3304 DUMPREG(i, DISPC_OVL_ACCU2_0); 3305 DUMPREG(i, DISPC_OVL_ACCU2_1); 3306 } 3307 if (dss_has_feature(FEAT_ATTR2)) 3308 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3309 } 3310 3311 if (dispc.feat->has_writeback) { 3312 i = OMAP_DSS_WB; 3313 DUMPREG(i, DISPC_OVL_BA0); 3314 DUMPREG(i, DISPC_OVL_BA1); 3315 DUMPREG(i, DISPC_OVL_SIZE); 3316 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3317 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3318 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3319 DUMPREG(i, DISPC_OVL_ROW_INC); 3320 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3321 3322 if (dss_has_feature(FEAT_MFLAG)) 3323 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3324 3325 DUMPREG(i, DISPC_OVL_FIR); 3326 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3327 DUMPREG(i, DISPC_OVL_ACCU0); 3328 DUMPREG(i, DISPC_OVL_ACCU1); 3329 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3330 DUMPREG(i, DISPC_OVL_BA0_UV); 3331 DUMPREG(i, DISPC_OVL_BA1_UV); 3332 DUMPREG(i, DISPC_OVL_FIR2); 3333 DUMPREG(i, DISPC_OVL_ACCU2_0); 3334 DUMPREG(i, DISPC_OVL_ACCU2_1); 3335 } 3336 if (dss_has_feature(FEAT_ATTR2)) 3337 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3338 } 3339 3340 #undef DISPC_REG 3341 #undef DUMPREG 3342 3343 #define DISPC_REG(plane, name, i) name(plane, i) 3344 #define DUMPREG(plane, name, i) \ 3345 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3346 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3347 dispc_read_reg(DISPC_REG(plane, name, i))) 3348 3349 /* Video pipeline coefficient registers */ 3350 3351 /* start from OMAP_DSS_VIDEO1 */ 3352 for (i = 1; i < dss_feat_get_num_ovls(); i++) { 3353 for (j = 0; j < 8; j++) 3354 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); 3355 3356 for (j = 0; j < 8; j++) 3357 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); 3358 3359 for (j = 0; j < 5; j++) 3360 DUMPREG(i, DISPC_OVL_CONV_COEF, j); 3361 3362 if (dss_has_feature(FEAT_FIR_COEF_V)) { 3363 for (j = 0; j < 8; j++) 3364 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); 3365 } 3366 3367 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3368 for (j = 0; j < 8; j++) 3369 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); 3370 3371 for (j = 0; j < 8; j++) 3372 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); 3373 3374 for (j = 0; j < 8; j++) 3375 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); 3376 } 3377 } 3378 3379 dispc_runtime_put(); 3380 3381 #undef DISPC_REG 3382 #undef DUMPREG 3383 } 3384 3385 /* calculate clock rates using dividers in cinfo */ 3386 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3387 struct dispc_clock_info *cinfo) 3388 { 3389 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3390 return -EINVAL; 3391 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3392 return -EINVAL; 3393 3394 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3395 cinfo->pck = cinfo->lck / cinfo->pck_div; 3396 3397 return 0; 3398 } 3399 3400 bool dispc_div_calc(unsigned long dispc, 3401 unsigned long pck_min, unsigned long pck_max, 3402 dispc_div_calc_func func, void *data) 3403 { 3404 int lckd, lckd_start, lckd_stop; 3405 int pckd, pckd_start, pckd_stop; 3406 unsigned long pck, lck; 3407 unsigned long lck_max; 3408 unsigned long pckd_hw_min, pckd_hw_max; 3409 unsigned min_fck_per_pck; 3410 unsigned long fck; 3411 3412 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK 3413 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; 3414 #else 3415 min_fck_per_pck = 0; 3416 #endif 3417 3418 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); 3419 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); 3420 3421 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 3422 3423 pck_min = pck_min ? pck_min : 1; 3424 pck_max = pck_max ? pck_max : ULONG_MAX; 3425 3426 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); 3427 lckd_stop = min(dispc / pck_min, 255ul); 3428 3429 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3430 lck = dispc / lckd; 3431 3432 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3433 pckd_stop = min(lck / pck_min, pckd_hw_max); 3434 3435 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3436 pck = lck / pckd; 3437 3438 /* 3439 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3440 * clock, which means we're configuring DISPC fclk here 3441 * also. Thus we need to use the calculated lck. For 3442 * OMAP4+ the DISPC fclk is a separate clock. 3443 */ 3444 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 3445 fck = dispc_core_clk_rate(); 3446 else 3447 fck = lck; 3448 3449 if (fck < pck * min_fck_per_pck) 3450 continue; 3451 3452 if (func(lckd, pckd, lck, pck, data)) 3453 return true; 3454 } 3455 } 3456 3457 return false; 3458 } 3459 3460 void dispc_mgr_set_clock_div(enum omap_channel channel, 3461 const struct dispc_clock_info *cinfo) 3462 { 3463 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3464 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3465 3466 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); 3467 } 3468 3469 int dispc_mgr_get_clock_div(enum omap_channel channel, 3470 struct dispc_clock_info *cinfo) 3471 { 3472 unsigned long fck; 3473 3474 fck = dispc_fclk_rate(); 3475 3476 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3477 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); 3478 3479 cinfo->lck = fck / cinfo->lck_div; 3480 cinfo->pck = cinfo->lck / cinfo->pck_div; 3481 3482 return 0; 3483 } 3484 3485 static u32 dispc_read_irqstatus(void) 3486 { 3487 return dispc_read_reg(DISPC_IRQSTATUS); 3488 } 3489 3490 static void dispc_clear_irqstatus(u32 mask) 3491 { 3492 dispc_write_reg(DISPC_IRQSTATUS, mask); 3493 } 3494 3495 static void dispc_write_irqenable(u32 mask) 3496 { 3497 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3498 3499 /* clear the irqstatus for newly enabled irqs */ 3500 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3501 3502 dispc_write_reg(DISPC_IRQENABLE, mask); 3503 3504 /* flush posted write */ 3505 dispc_read_reg(DISPC_IRQENABLE); 3506 } 3507 3508 void dispc_enable_sidle(void) 3509 { 3510 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ 3511 } 3512 3513 void dispc_disable_sidle(void) 3514 { 3515 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3516 } 3517 3518 static u32 dispc_mgr_gamma_size(enum omap_channel channel) 3519 { 3520 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3521 3522 if (!dispc.feat->has_gamma_table) 3523 return 0; 3524 3525 return gdesc->len; 3526 } 3527 3528 static void dispc_mgr_write_gamma_table(enum omap_channel channel) 3529 { 3530 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3531 u32 *table = dispc.gamma_table[channel]; 3532 unsigned int i; 3533 3534 DSSDBG("%s: channel %d\n", __func__, channel); 3535 3536 for (i = 0; i < gdesc->len; ++i) { 3537 u32 v = table[i]; 3538 3539 if (gdesc->has_index) 3540 v |= i << 24; 3541 else if (i == 0) 3542 v |= 1 << 31; 3543 3544 dispc_write_reg(gdesc->reg, v); 3545 } 3546 } 3547 3548 static void dispc_restore_gamma_tables(void) 3549 { 3550 DSSDBG("%s()\n", __func__); 3551 3552 if (!dispc.feat->has_gamma_table) 3553 return; 3554 3555 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD); 3556 3557 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT); 3558 3559 if (dss_has_feature(FEAT_MGR_LCD2)) 3560 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2); 3561 3562 if (dss_has_feature(FEAT_MGR_LCD3)) 3563 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3); 3564 } 3565 3566 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 3567 { .red = 0, .green = 0, .blue = 0, }, 3568 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 3569 }; 3570 3571 static void dispc_mgr_set_gamma(enum omap_channel channel, 3572 const struct drm_color_lut *lut, 3573 unsigned int length) 3574 { 3575 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3576 u32 *table = dispc.gamma_table[channel]; 3577 uint i; 3578 3579 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__, 3580 channel, length, gdesc->len); 3581 3582 if (!dispc.feat->has_gamma_table) 3583 return; 3584 3585 if (lut == NULL || length < 2) { 3586 lut = dispc_mgr_gamma_default_lut; 3587 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut); 3588 } 3589 3590 for (i = 0; i < length - 1; ++i) { 3591 uint first = i * (gdesc->len - 1) / (length - 1); 3592 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); 3593 uint w = last - first; 3594 u16 r, g, b; 3595 uint j; 3596 3597 if (w == 0) 3598 continue; 3599 3600 for (j = 0; j <= w; j++) { 3601 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; 3602 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; 3603 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; 3604 3605 r >>= 16 - gdesc->bits; 3606 g >>= 16 - gdesc->bits; 3607 b >>= 16 - gdesc->bits; 3608 3609 table[first + j] = (r << (gdesc->bits * 2)) | 3610 (g << gdesc->bits) | b; 3611 } 3612 } 3613 3614 if (dispc.is_enabled) 3615 dispc_mgr_write_gamma_table(channel); 3616 } 3617 3618 static int dispc_init_gamma_tables(void) 3619 { 3620 int channel; 3621 3622 if (!dispc.feat->has_gamma_table) 3623 return 0; 3624 3625 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) { 3626 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3627 u32 *gt; 3628 3629 if (channel == OMAP_DSS_CHANNEL_LCD2 && 3630 !dss_has_feature(FEAT_MGR_LCD2)) 3631 continue; 3632 3633 if (channel == OMAP_DSS_CHANNEL_LCD3 && 3634 !dss_has_feature(FEAT_MGR_LCD3)) 3635 continue; 3636 3637 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len, 3638 sizeof(u32), GFP_KERNEL); 3639 if (!gt) 3640 return -ENOMEM; 3641 3642 dispc.gamma_table[channel] = gt; 3643 3644 dispc_mgr_set_gamma(channel, NULL, 0); 3645 } 3646 return 0; 3647 } 3648 3649 static void _omap_dispc_initial_config(void) 3650 { 3651 u32 l; 3652 3653 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3654 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3655 l = dispc_read_reg(DISPC_DIVISOR); 3656 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3657 l = FLD_MOD(l, 1, 0, 0); 3658 l = FLD_MOD(l, 1, 23, 16); 3659 dispc_write_reg(DISPC_DIVISOR, l); 3660 3661 dispc.core_clk_rate = dispc_fclk_rate(); 3662 } 3663 3664 /* Use gamma table mode, instead of palette mode */ 3665 if (dispc.feat->has_gamma_table) 3666 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3); 3667 3668 /* For older DSS versions (FEAT_FUNCGATED) this enables 3669 * func-clock auto-gating. For newer versions 3670 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables. 3671 */ 3672 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) 3673 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3674 3675 dispc_setup_color_conv_coef(); 3676 3677 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3678 3679 dispc_init_fifos(); 3680 3681 dispc_configure_burst_sizes(); 3682 3683 dispc_ovl_enable_zorder_planes(); 3684 3685 if (dispc.feat->mstandby_workaround) 3686 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3687 3688 if (dss_has_feature(FEAT_MFLAG)) 3689 dispc_init_mflag(); 3690 } 3691 3692 static const struct dispc_features omap24xx_dispc_feats = { 3693 .sw_start = 5, 3694 .fp_start = 15, 3695 .bp_start = 27, 3696 .sw_max = 64, 3697 .vp_max = 255, 3698 .hp_max = 256, 3699 .mgr_width_start = 10, 3700 .mgr_height_start = 26, 3701 .mgr_width_max = 2048, 3702 .mgr_height_max = 2048, 3703 .max_lcd_pclk = 66500000, 3704 .calc_scaling = dispc_ovl_calc_scaling_24xx, 3705 .calc_core_clk = calc_core_clk_24xx, 3706 .num_fifos = 3, 3707 .no_framedone_tv = true, 3708 .set_max_preload = false, 3709 .last_pixel_inc_missing = true, 3710 }; 3711 3712 static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 3713 .sw_start = 5, 3714 .fp_start = 15, 3715 .bp_start = 27, 3716 .sw_max = 64, 3717 .vp_max = 255, 3718 .hp_max = 256, 3719 .mgr_width_start = 10, 3720 .mgr_height_start = 26, 3721 .mgr_width_max = 2048, 3722 .mgr_height_max = 2048, 3723 .max_lcd_pclk = 173000000, 3724 .max_tv_pclk = 59000000, 3725 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3726 .calc_core_clk = calc_core_clk_34xx, 3727 .num_fifos = 3, 3728 .no_framedone_tv = true, 3729 .set_max_preload = false, 3730 .last_pixel_inc_missing = true, 3731 }; 3732 3733 static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 3734 .sw_start = 7, 3735 .fp_start = 19, 3736 .bp_start = 31, 3737 .sw_max = 256, 3738 .vp_max = 4095, 3739 .hp_max = 4096, 3740 .mgr_width_start = 10, 3741 .mgr_height_start = 26, 3742 .mgr_width_max = 2048, 3743 .mgr_height_max = 2048, 3744 .max_lcd_pclk = 173000000, 3745 .max_tv_pclk = 59000000, 3746 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3747 .calc_core_clk = calc_core_clk_34xx, 3748 .num_fifos = 3, 3749 .no_framedone_tv = true, 3750 .set_max_preload = false, 3751 .last_pixel_inc_missing = true, 3752 }; 3753 3754 static const struct dispc_features omap44xx_dispc_feats = { 3755 .sw_start = 7, 3756 .fp_start = 19, 3757 .bp_start = 31, 3758 .sw_max = 256, 3759 .vp_max = 4095, 3760 .hp_max = 4096, 3761 .mgr_width_start = 10, 3762 .mgr_height_start = 26, 3763 .mgr_width_max = 2048, 3764 .mgr_height_max = 2048, 3765 .max_lcd_pclk = 170000000, 3766 .max_tv_pclk = 185625000, 3767 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3768 .calc_core_clk = calc_core_clk_44xx, 3769 .num_fifos = 5, 3770 .gfx_fifo_workaround = true, 3771 .set_max_preload = true, 3772 .supports_sync_align = true, 3773 .has_writeback = true, 3774 .supports_double_pixel = true, 3775 .reverse_ilace_field_order = true, 3776 .has_gamma_table = true, 3777 .has_gamma_i734_bug = true, 3778 }; 3779 3780 static const struct dispc_features omap54xx_dispc_feats = { 3781 .sw_start = 7, 3782 .fp_start = 19, 3783 .bp_start = 31, 3784 .sw_max = 256, 3785 .vp_max = 4095, 3786 .hp_max = 4096, 3787 .mgr_width_start = 11, 3788 .mgr_height_start = 27, 3789 .mgr_width_max = 4096, 3790 .mgr_height_max = 4096, 3791 .max_lcd_pclk = 170000000, 3792 .max_tv_pclk = 186000000, 3793 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3794 .calc_core_clk = calc_core_clk_44xx, 3795 .num_fifos = 5, 3796 .gfx_fifo_workaround = true, 3797 .mstandby_workaround = true, 3798 .set_max_preload = true, 3799 .supports_sync_align = true, 3800 .has_writeback = true, 3801 .supports_double_pixel = true, 3802 .reverse_ilace_field_order = true, 3803 .has_gamma_table = true, 3804 .has_gamma_i734_bug = true, 3805 }; 3806 3807 static int dispc_init_features(struct platform_device *pdev) 3808 { 3809 const struct dispc_features *src; 3810 struct dispc_features *dst; 3811 3812 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); 3813 if (!dst) { 3814 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n"); 3815 return -ENOMEM; 3816 } 3817 3818 switch (omapdss_get_version()) { 3819 case OMAPDSS_VER_OMAP24xx: 3820 src = &omap24xx_dispc_feats; 3821 break; 3822 3823 case OMAPDSS_VER_OMAP34xx_ES1: 3824 src = &omap34xx_rev1_0_dispc_feats; 3825 break; 3826 3827 case OMAPDSS_VER_OMAP34xx_ES3: 3828 case OMAPDSS_VER_OMAP3630: 3829 case OMAPDSS_VER_AM35xx: 3830 case OMAPDSS_VER_AM43xx: 3831 src = &omap34xx_rev3_0_dispc_feats; 3832 break; 3833 3834 case OMAPDSS_VER_OMAP4430_ES1: 3835 case OMAPDSS_VER_OMAP4430_ES2: 3836 case OMAPDSS_VER_OMAP4: 3837 src = &omap44xx_dispc_feats; 3838 break; 3839 3840 case OMAPDSS_VER_OMAP5: 3841 case OMAPDSS_VER_DRA7xx: 3842 src = &omap54xx_dispc_feats; 3843 break; 3844 3845 default: 3846 return -ENODEV; 3847 } 3848 3849 memcpy(dst, src, sizeof(*dst)); 3850 dispc.feat = dst; 3851 3852 return 0; 3853 } 3854 3855 static irqreturn_t dispc_irq_handler(int irq, void *arg) 3856 { 3857 if (!dispc.is_enabled) 3858 return IRQ_NONE; 3859 3860 return dispc.user_handler(irq, dispc.user_data); 3861 } 3862 3863 static int dispc_request_irq(irq_handler_t handler, void *dev_id) 3864 { 3865 int r; 3866 3867 if (dispc.user_handler != NULL) 3868 return -EBUSY; 3869 3870 dispc.user_handler = handler; 3871 dispc.user_data = dev_id; 3872 3873 /* ensure the dispc_irq_handler sees the values above */ 3874 smp_wmb(); 3875 3876 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, 3877 IRQF_SHARED, "OMAP DISPC", &dispc); 3878 if (r) { 3879 dispc.user_handler = NULL; 3880 dispc.user_data = NULL; 3881 } 3882 3883 return r; 3884 } 3885 3886 static void dispc_free_irq(void *dev_id) 3887 { 3888 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); 3889 3890 dispc.user_handler = NULL; 3891 dispc.user_data = NULL; 3892 } 3893 3894 /* 3895 * Workaround for errata i734 in DSS dispc 3896 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled 3897 * 3898 * For gamma tables to work on LCD1 the GFX plane has to be used at 3899 * least once after DSS HW has come out of reset. The workaround 3900 * sets up a minimal LCD setup with GFX plane and waits for one 3901 * vertical sync irq before disabling the setup and continuing with 3902 * the context restore. The physical outputs are gated during the 3903 * operation. This workaround requires that gamma table's LOADMODE 3904 * is set to 0x2 in DISPC_CONTROL1 register. 3905 * 3906 * For details see: 3907 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata 3908 * Literature Number: SWPZ037E 3909 * Or some other relevant errata document for the DSS IP version. 3910 */ 3911 3912 static const struct dispc_errata_i734_data { 3913 struct videomode vm; 3914 struct omap_overlay_info ovli; 3915 struct omap_overlay_manager_info mgri; 3916 struct dss_lcd_mgr_config lcd_conf; 3917 } i734 = { 3918 .vm = { 3919 .hactive = 8, .vactive = 1, 3920 .pixelclock = 16000000, 3921 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 3922 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, 3923 3924 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3925 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE | 3926 DISPLAY_FLAGS_PIXDATA_POSEDGE, 3927 }, 3928 .ovli = { 3929 .screen_width = 1, 3930 .width = 1, .height = 1, 3931 .fourcc = DRM_FORMAT_XRGB8888, 3932 .rotation = DRM_MODE_ROTATE_0, 3933 .rotation_type = OMAP_DSS_ROT_NONE, 3934 .pos_x = 0, .pos_y = 0, 3935 .out_width = 0, .out_height = 0, 3936 .global_alpha = 0xff, 3937 .pre_mult_alpha = 0, 3938 .zorder = 0, 3939 }, 3940 .mgri = { 3941 .default_color = 0, 3942 .trans_enabled = false, 3943 .partial_alpha_enabled = false, 3944 .cpr_enable = false, 3945 }, 3946 .lcd_conf = { 3947 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS, 3948 .stallmode = false, 3949 .fifohandcheck = false, 3950 .clock_info = { 3951 .lck_div = 1, 3952 .pck_div = 2, 3953 }, 3954 .video_port_width = 24, 3955 .lcden_sig_polarity = 0, 3956 }, 3957 }; 3958 3959 static struct i734_buf { 3960 size_t size; 3961 dma_addr_t paddr; 3962 void *vaddr; 3963 } i734_buf; 3964 3965 static int dispc_errata_i734_wa_init(void) 3966 { 3967 if (!dispc.feat->has_gamma_i734_bug) 3968 return 0; 3969 3970 i734_buf.size = i734.ovli.width * i734.ovli.height * 3971 color_mode_to_bpp(i734.ovli.fourcc) / 8; 3972 3973 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size, 3974 &i734_buf.paddr, GFP_KERNEL); 3975 if (!i734_buf.vaddr) { 3976 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed", 3977 __func__); 3978 return -ENOMEM; 3979 } 3980 3981 return 0; 3982 } 3983 3984 static void dispc_errata_i734_wa_fini(void) 3985 { 3986 if (!dispc.feat->has_gamma_i734_bug) 3987 return; 3988 3989 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr, 3990 i734_buf.paddr); 3991 } 3992 3993 static void dispc_errata_i734_wa(void) 3994 { 3995 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD); 3996 struct omap_overlay_info ovli; 3997 struct dss_lcd_mgr_config lcd_conf; 3998 u32 gatestate; 3999 unsigned int count; 4000 4001 if (!dispc.feat->has_gamma_i734_bug) 4002 return; 4003 4004 gatestate = REG_GET(DISPC_CONFIG, 8, 4); 4005 4006 ovli = i734.ovli; 4007 ovli.paddr = i734_buf.paddr; 4008 lcd_conf = i734.lcd_conf; 4009 4010 /* Gate all LCD1 outputs */ 4011 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4); 4012 4013 /* Setup and enable GFX plane */ 4014 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false, 4015 OMAP_DSS_CHANNEL_LCD); 4016 dispc_ovl_enable(OMAP_DSS_GFX, true); 4017 4018 /* Set up and enable display manager for LCD1 */ 4019 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri); 4020 dispc_calc_clock_rates(dss_get_dispc_clk_rate(), 4021 &lcd_conf.clock_info); 4022 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4023 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm); 4024 4025 dispc_clear_irqstatus(framedone_irq); 4026 4027 /* Enable and shut the channel to produce just one frame */ 4028 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true); 4029 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false); 4030 4031 /* Busy wait for framedone. We can't fiddle with irq handlers 4032 * in PM resume. Typically the loop runs less than 5 times and 4033 * waits less than a micro second. 4034 */ 4035 count = 0; 4036 while (!(dispc_read_irqstatus() & framedone_irq)) { 4037 if (count++ > 10000) { 4038 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n", 4039 __func__); 4040 break; 4041 } 4042 } 4043 dispc_ovl_enable(OMAP_DSS_GFX, false); 4044 4045 /* Clear all irq bits before continuing */ 4046 dispc_clear_irqstatus(0xffffffff); 4047 4048 /* Restore the original state to LCD1 output gates */ 4049 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4); 4050 } 4051 4052 static const struct dispc_ops dispc_ops = { 4053 .read_irqstatus = dispc_read_irqstatus, 4054 .clear_irqstatus = dispc_clear_irqstatus, 4055 .write_irqenable = dispc_write_irqenable, 4056 4057 .request_irq = dispc_request_irq, 4058 .free_irq = dispc_free_irq, 4059 4060 .runtime_get = dispc_runtime_get, 4061 .runtime_put = dispc_runtime_put, 4062 4063 .get_num_ovls = dispc_get_num_ovls, 4064 .get_num_mgrs = dispc_get_num_mgrs, 4065 4066 .mgr_enable = dispc_mgr_enable, 4067 .mgr_is_enabled = dispc_mgr_is_enabled, 4068 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, 4069 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq, 4070 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq, 4071 .mgr_go_busy = dispc_mgr_go_busy, 4072 .mgr_go = dispc_mgr_go, 4073 .mgr_set_lcd_config = dispc_mgr_set_lcd_config, 4074 .mgr_set_timings = dispc_mgr_set_timings, 4075 .mgr_setup = dispc_mgr_setup, 4076 .mgr_get_supported_outputs = dispc_mgr_get_supported_outputs, 4077 .mgr_gamma_size = dispc_mgr_gamma_size, 4078 .mgr_set_gamma = dispc_mgr_set_gamma, 4079 4080 .ovl_enable = dispc_ovl_enable, 4081 .ovl_setup = dispc_ovl_setup, 4082 .ovl_get_color_modes = dispc_ovl_get_color_modes, 4083 }; 4084 4085 /* DISPC HW IP initialisation */ 4086 static int dispc_bind(struct device *dev, struct device *master, void *data) 4087 { 4088 struct platform_device *pdev = to_platform_device(dev); 4089 u32 rev; 4090 int r = 0; 4091 struct resource *dispc_mem; 4092 struct device_node *np = pdev->dev.of_node; 4093 4094 dispc.pdev = pdev; 4095 4096 spin_lock_init(&dispc.control_lock); 4097 4098 r = dispc_init_features(dispc.pdev); 4099 if (r) 4100 return r; 4101 4102 r = dispc_errata_i734_wa_init(); 4103 if (r) 4104 return r; 4105 4106 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); 4107 dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem); 4108 if (IS_ERR(dispc.base)) 4109 return PTR_ERR(dispc.base); 4110 4111 dispc.irq = platform_get_irq(dispc.pdev, 0); 4112 if (dispc.irq < 0) { 4113 DSSERR("platform_get_irq failed\n"); 4114 return -ENODEV; 4115 } 4116 4117 if (np && of_property_read_bool(np, "syscon-pol")) { 4118 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 4119 if (IS_ERR(dispc.syscon_pol)) { 4120 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 4121 return PTR_ERR(dispc.syscon_pol); 4122 } 4123 4124 if (of_property_read_u32_index(np, "syscon-pol", 1, 4125 &dispc.syscon_pol_offset)) { 4126 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 4127 return -EINVAL; 4128 } 4129 } 4130 4131 r = dispc_init_gamma_tables(); 4132 if (r) 4133 return r; 4134 4135 pm_runtime_enable(&pdev->dev); 4136 4137 r = dispc_runtime_get(); 4138 if (r) 4139 goto err_runtime_get; 4140 4141 _omap_dispc_initial_config(); 4142 4143 rev = dispc_read_reg(DISPC_REVISION); 4144 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 4145 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4146 4147 dispc_runtime_put(); 4148 4149 dispc_set_ops(&dispc_ops); 4150 4151 dss_debugfs_create_file("dispc", dispc_dump_regs); 4152 4153 return 0; 4154 4155 err_runtime_get: 4156 pm_runtime_disable(&pdev->dev); 4157 return r; 4158 } 4159 4160 static void dispc_unbind(struct device *dev, struct device *master, 4161 void *data) 4162 { 4163 dispc_set_ops(NULL); 4164 4165 pm_runtime_disable(dev); 4166 4167 dispc_errata_i734_wa_fini(); 4168 } 4169 4170 static const struct component_ops dispc_component_ops = { 4171 .bind = dispc_bind, 4172 .unbind = dispc_unbind, 4173 }; 4174 4175 static int dispc_probe(struct platform_device *pdev) 4176 { 4177 return component_add(&pdev->dev, &dispc_component_ops); 4178 } 4179 4180 static int dispc_remove(struct platform_device *pdev) 4181 { 4182 component_del(&pdev->dev, &dispc_component_ops); 4183 return 0; 4184 } 4185 4186 static int dispc_runtime_suspend(struct device *dev) 4187 { 4188 dispc.is_enabled = false; 4189 /* ensure the dispc_irq_handler sees the is_enabled value */ 4190 smp_wmb(); 4191 /* wait for current handler to finish before turning the DISPC off */ 4192 synchronize_irq(dispc.irq); 4193 4194 dispc_save_context(); 4195 4196 return 0; 4197 } 4198 4199 static int dispc_runtime_resume(struct device *dev) 4200 { 4201 /* 4202 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4203 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4204 * _omap_dispc_initial_config(). We can thus use it to detect if 4205 * we have lost register context. 4206 */ 4207 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4208 _omap_dispc_initial_config(); 4209 4210 dispc_errata_i734_wa(); 4211 4212 dispc_restore_context(); 4213 4214 dispc_restore_gamma_tables(); 4215 } 4216 4217 dispc.is_enabled = true; 4218 /* ensure the dispc_irq_handler sees the is_enabled value */ 4219 smp_wmb(); 4220 4221 return 0; 4222 } 4223 4224 static const struct dev_pm_ops dispc_pm_ops = { 4225 .runtime_suspend = dispc_runtime_suspend, 4226 .runtime_resume = dispc_runtime_resume, 4227 }; 4228 4229 static const struct of_device_id dispc_of_match[] = { 4230 { .compatible = "ti,omap2-dispc", }, 4231 { .compatible = "ti,omap3-dispc", }, 4232 { .compatible = "ti,omap4-dispc", }, 4233 { .compatible = "ti,omap5-dispc", }, 4234 { .compatible = "ti,dra7-dispc", }, 4235 {}, 4236 }; 4237 4238 static struct platform_driver omap_dispchw_driver = { 4239 .probe = dispc_probe, 4240 .remove = dispc_remove, 4241 .driver = { 4242 .name = "omapdss_dispc", 4243 .pm = &dispc_pm_ops, 4244 .of_match_table = dispc_of_match, 4245 .suppress_bind_attrs = true, 4246 }, 4247 }; 4248 4249 int __init dispc_init_platform_driver(void) 4250 { 4251 return platform_driver_register(&omap_dispchw_driver); 4252 } 4253 4254 void dispc_uninit_platform_driver(void) 4255 { 4256 platform_driver_unregister(&omap_dispchw_driver); 4257 } 4258