1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #define gk20a_volt(p) container_of((p), struct gk20a_volt, base) 23 #include "priv.h" 24 25 #ifdef __KERNEL__ 26 #include <nouveau_platform.h> 27 #endif 28 29 struct cvb_coef { 30 int c0; 31 int c1; 32 int c2; 33 int c3; 34 int c4; 35 int c5; 36 }; 37 38 struct gk20a_volt { 39 struct nvkm_volt base; 40 struct regulator *vdd; 41 }; 42 43 const struct cvb_coef gk20a_cvb_coef[] = { 44 /* MHz, c0, c1, c2, c3, c4, c5 */ 45 /* 72 */ { 1209886, -36468, 515, 417, -13123, 203}, 46 /* 108 */ { 1130804, -27659, 296, 298, -10834, 221}, 47 /* 180 */ { 1162871, -27110, 247, 238, -10681, 268}, 48 /* 252 */ { 1220458, -28654, 247, 179, -10376, 298}, 49 /* 324 */ { 1280953, -30204, 247, 119, -9766, 304}, 50 /* 396 */ { 1344547, -31777, 247, 119, -8545, 292}, 51 /* 468 */ { 1420168, -34227, 269, 60, -7172, 256}, 52 /* 540 */ { 1490757, -35955, 274, 60, -5188, 197}, 53 /* 612 */ { 1599112, -42583, 398, 0, -1831, 119}, 54 /* 648 */ { 1366986, -16459, -274, 0, -3204, 72}, 55 /* 684 */ { 1391884, -17078, -274, -60, -1526, 30}, 56 /* 708 */ { 1415522, -17497, -274, -60, -458, 0}, 57 /* 756 */ { 1464061, -18331, -274, -119, 1831, -72}, 58 /* 804 */ { 1524225, -20064, -254, -119, 4272, -155}, 59 /* 852 */ { 1608418, -21643, -269, 0, 763, -48}, 60 }; 61 62 /** 63 * cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) 64 */ 65 static inline int 66 gk20a_volt_get_cvb_voltage(int speedo, int s_scale, const struct cvb_coef *coef) 67 { 68 int mv; 69 70 mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale); 71 mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0; 72 return mv; 73 } 74 75 /** 76 * cvb_t_mv = 77 * ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) + 78 * ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale) 79 */ 80 static inline int 81 gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale, 82 const struct cvb_coef *coef) 83 { 84 int cvb_mv, mv; 85 86 cvb_mv = gk20a_volt_get_cvb_voltage(speedo, s_scale, coef); 87 88 mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 + 89 DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale); 90 mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv; 91 return mv; 92 } 93 94 static int 95 gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo) 96 { 97 int mv; 98 99 mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef); 100 mv = DIV_ROUND_UP(mv, 1000); 101 102 return mv * 1000; 103 } 104 105 static int 106 gk20a_volt_vid_get(struct nvkm_volt *base) 107 { 108 struct gk20a_volt *volt = gk20a_volt(base); 109 int i, uv; 110 111 uv = regulator_get_voltage(volt->vdd); 112 113 for (i = 0; i < volt->base.vid_nr; i++) 114 if (volt->base.vid[i].uv >= uv) 115 return i; 116 117 return -EINVAL; 118 } 119 120 static int 121 gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid) 122 { 123 struct gk20a_volt *volt = gk20a_volt(base); 124 struct nvkm_subdev *subdev = &volt->base.subdev; 125 126 nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv); 127 return regulator_set_voltage(volt->vdd, volt->base.vid[vid].uv, 1200000); 128 } 129 130 static int 131 gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition) 132 { 133 struct gk20a_volt *volt = gk20a_volt(base); 134 struct nvkm_subdev *subdev = &volt->base.subdev; 135 int prev_uv = regulator_get_voltage(volt->vdd); 136 int target_uv = volt->base.vid[id].uv; 137 int ret; 138 139 nvkm_debug(subdev, "prev=%d, target=%d, condition=%d\n", 140 prev_uv, target_uv, condition); 141 if (!condition || 142 (condition < 0 && target_uv < prev_uv) || 143 (condition > 0 && target_uv > prev_uv)) { 144 ret = gk20a_volt_vid_set(&volt->base, volt->base.vid[id].vid); 145 } else { 146 ret = 0; 147 } 148 149 return ret; 150 } 151 152 static const struct nvkm_volt_func 153 gk20a_volt = { 154 .vid_get = gk20a_volt_vid_get, 155 .vid_set = gk20a_volt_vid_set, 156 .set_id = gk20a_volt_set_id, 157 }; 158 159 int 160 gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) 161 { 162 struct gk20a_volt *volt; 163 int i, uv; 164 165 if (!(volt = kzalloc(sizeof(*volt), GFP_KERNEL))) 166 return -ENOMEM; 167 168 nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); 169 *pvolt = &volt->base; 170 171 uv = regulator_get_voltage(device->gpu->vdd); 172 nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv); 173 174 volt->vdd = device->gpu->vdd; 175 176 volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef); 177 nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__, 178 volt->base.vid_nr); 179 for (i = 0; i < volt->base.vid_nr; i++) { 180 volt->base.vid[i].vid = i; 181 volt->base.vid[i].uv = 182 gk20a_volt_calc_voltage(&gk20a_cvb_coef[i], 183 device->gpu->gpu_speedo); 184 nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i, 185 volt->base.vid[i].vid, volt->base.vid[i].uv); 186 } 187 188 return 0; 189 } 190