1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Martin Peres 24 */ 25 #include "priv.h" 26 27 #include <subdev/fuse.h> 28 29 int 30 g84_temp_get(struct nvkm_therm *therm) 31 { 32 struct nvkm_fuse *fuse = nvkm_fuse(therm); 33 34 if (nv_ro32(fuse, 0x1a8) == 1) 35 return nv_rd32(therm, 0x20400); 36 else 37 return -ENODEV; 38 } 39 40 void 41 g84_sensor_setup(struct nvkm_therm *therm) 42 { 43 struct nvkm_fuse *fuse = nvkm_fuse(therm); 44 45 /* enable temperature reading for cards with insane defaults */ 46 if (nv_ro32(fuse, 0x1a8) == 1) { 47 nv_mask(therm, 0x20008, 0x80008000, 0x80000000); 48 nv_mask(therm, 0x2000c, 0x80000003, 0x00000000); 49 mdelay(20); /* wait for the temperature to stabilize */ 50 } 51 } 52 53 static void 54 g84_therm_program_alarms(struct nvkm_therm *obj) 55 { 56 struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base); 57 struct nvbios_therm_sensor *sensor = &therm->bios_sensor; 58 unsigned long flags; 59 60 spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags); 61 62 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ 63 nv_wr32(therm, 0x20000, 0x000003ff); 64 65 /* shutdown: The computer should be shutdown when reached */ 66 nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis); 67 nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp); 68 69 /* THRS_1 : fan boost*/ 70 nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp); 71 72 /* THRS_2 : critical */ 73 nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp); 74 75 /* THRS_4 : down clock */ 76 nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp); 77 spin_unlock_irqrestore(&therm->sensor.alarm_program_lock, flags); 78 79 nv_debug(therm, 80 "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n", 81 sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis, 82 sensor->thrs_down_clock.temp, 83 sensor->thrs_down_clock.hysteresis, 84 sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis, 85 sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis); 86 87 } 88 89 /* must be called with alarm_program_lock taken ! */ 90 static void 91 g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm, 92 uint32_t thrs_reg, u8 status_bit, 93 const struct nvbios_therm_threshold *thrs, 94 enum nvkm_therm_thrs thrs_name) 95 { 96 enum nvkm_therm_thrs_direction direction; 97 enum nvkm_therm_thrs_state prev_state, new_state; 98 int temp, cur; 99 100 prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name); 101 temp = nv_rd32(therm, thrs_reg); 102 103 /* program the next threshold */ 104 if (temp == thrs->temp) { 105 nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis); 106 new_state = NVKM_THERM_THRS_HIGHER; 107 } else { 108 nv_wr32(therm, thrs_reg, thrs->temp); 109 new_state = NVKM_THERM_THRS_LOWER; 110 } 111 112 /* fix the state (in case someone reprogrammed the alarms) */ 113 cur = therm->temp_get(therm); 114 if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp) 115 new_state = NVKM_THERM_THRS_HIGHER; 116 else if (new_state == NVKM_THERM_THRS_HIGHER && 117 cur < thrs->temp - thrs->hysteresis) 118 new_state = NVKM_THERM_THRS_LOWER; 119 nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state); 120 121 /* find the direction */ 122 if (prev_state < new_state) 123 direction = NVKM_THERM_THRS_RISING; 124 else if (prev_state > new_state) 125 direction = NVKM_THERM_THRS_FALLING; 126 else 127 return; 128 129 /* advertise a change in direction */ 130 nvkm_therm_sensor_event(therm, thrs_name, direction); 131 } 132 133 static void 134 g84_therm_intr(struct nvkm_subdev *subdev) 135 { 136 struct nvkm_therm_priv *therm = (void *)subdev; 137 struct nvbios_therm_sensor *sensor = &therm->bios_sensor; 138 unsigned long flags; 139 uint32_t intr; 140 141 spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags); 142 143 intr = nv_rd32(therm, 0x20100) & 0x3ff; 144 145 /* THRS_4: downclock */ 146 if (intr & 0x002) { 147 g84_therm_threshold_hyst_emulation(&therm->base, 0x20414, 24, 148 &sensor->thrs_down_clock, 149 NVKM_THERM_THRS_DOWNCLOCK); 150 intr &= ~0x002; 151 } 152 153 /* shutdown */ 154 if (intr & 0x004) { 155 g84_therm_threshold_hyst_emulation(&therm->base, 0x20480, 20, 156 &sensor->thrs_shutdown, 157 NVKM_THERM_THRS_SHUTDOWN); 158 intr &= ~0x004; 159 } 160 161 /* THRS_1 : fan boost */ 162 if (intr & 0x008) { 163 g84_therm_threshold_hyst_emulation(&therm->base, 0x204c4, 21, 164 &sensor->thrs_fan_boost, 165 NVKM_THERM_THRS_FANBOOST); 166 intr &= ~0x008; 167 } 168 169 /* THRS_2 : critical */ 170 if (intr & 0x010) { 171 g84_therm_threshold_hyst_emulation(&therm->base, 0x204c0, 22, 172 &sensor->thrs_critical, 173 NVKM_THERM_THRS_CRITICAL); 174 intr &= ~0x010; 175 } 176 177 if (intr) 178 nv_error(therm, "unhandled intr 0x%08x\n", intr); 179 180 /* ACK everything */ 181 nv_wr32(therm, 0x20100, 0xffffffff); 182 nv_wr32(therm, 0x1100, 0x10000); /* PBUS */ 183 184 spin_unlock_irqrestore(&therm->sensor.alarm_program_lock, flags); 185 } 186 187 static int 188 g84_therm_init(struct nvkm_object *object) 189 { 190 struct nvkm_therm_priv *therm = (void *)object; 191 int ret; 192 193 ret = nvkm_therm_init(&therm->base); 194 if (ret) 195 return ret; 196 197 g84_sensor_setup(&therm->base); 198 return 0; 199 } 200 201 static int 202 g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 203 struct nvkm_oclass *oclass, void *data, u32 size, 204 struct nvkm_object **pobject) 205 { 206 struct nvkm_therm_priv *therm; 207 int ret; 208 209 ret = nvkm_therm_create(parent, engine, oclass, &therm); 210 *pobject = nv_object(therm); 211 if (ret) 212 return ret; 213 214 therm->base.pwm_ctrl = nv50_fan_pwm_ctrl; 215 therm->base.pwm_get = nv50_fan_pwm_get; 216 therm->base.pwm_set = nv50_fan_pwm_set; 217 therm->base.pwm_clock = nv50_fan_pwm_clock; 218 therm->base.temp_get = g84_temp_get; 219 therm->sensor.program_alarms = g84_therm_program_alarms; 220 nv_subdev(therm)->intr = g84_therm_intr; 221 222 /* init the thresholds */ 223 nvkm_therm_sensor_set_threshold_state(&therm->base, 224 NVKM_THERM_THRS_SHUTDOWN, 225 NVKM_THERM_THRS_LOWER); 226 nvkm_therm_sensor_set_threshold_state(&therm->base, 227 NVKM_THERM_THRS_FANBOOST, 228 NVKM_THERM_THRS_LOWER); 229 nvkm_therm_sensor_set_threshold_state(&therm->base, 230 NVKM_THERM_THRS_CRITICAL, 231 NVKM_THERM_THRS_LOWER); 232 nvkm_therm_sensor_set_threshold_state(&therm->base, 233 NVKM_THERM_THRS_DOWNCLOCK, 234 NVKM_THERM_THRS_LOWER); 235 236 return nvkm_therm_preinit(&therm->base); 237 } 238 239 int 240 g84_therm_fini(struct nvkm_object *object, bool suspend) 241 { 242 /* Disable PTherm IRQs */ 243 nv_wr32(object, 0x20000, 0x00000000); 244 245 /* ACK all PTherm IRQs */ 246 nv_wr32(object, 0x20100, 0xffffffff); 247 nv_wr32(object, 0x1100, 0x10000); /* PBUS */ 248 249 return _nvkm_therm_fini(object, suspend); 250 } 251 252 struct nvkm_oclass 253 g84_therm_oclass = { 254 .handle = NV_SUBDEV(THERM, 0x84), 255 .ofuncs = &(struct nvkm_ofuncs) { 256 .ctor = g84_therm_ctor, 257 .dtor = _nvkm_therm_dtor, 258 .init = g84_therm_init, 259 .fini = g84_therm_fini, 260 }, 261 }; 262