1 #ifndef __NVKM_PMU_MEMX_H__
2 #define __NVKM_PMU_MEMX_H__
3 #include "priv.h"
4 
5 struct nvkm_memx {
6 	struct nvkm_pmu *pmu;
7 	u32 base;
8 	u32 size;
9 	struct {
10 		u32 mthd;
11 		u32 size;
12 		u32 data[64];
13 	} c;
14 };
15 
16 static void
17 memx_out(struct nvkm_memx *memx)
18 {
19 	struct nvkm_pmu *pmu = memx->pmu;
20 	int i;
21 
22 	if (memx->c.mthd) {
23 		nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
24 		for (i = 0; i < memx->c.size; i++)
25 			nv_wr32(pmu, 0x10a1c4, memx->c.data[i]);
26 		memx->c.mthd = 0;
27 		memx->c.size = 0;
28 	}
29 }
30 
31 static void
32 memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
33 {
34 	if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
35 	    (memx->c.mthd && memx->c.mthd != mthd))
36 		memx_out(memx);
37 	memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
38 	memx->c.size += size;
39 	memx->c.mthd  = mthd;
40 }
41 
42 int
43 nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
44 {
45 	struct nvkm_memx *memx;
46 	u32 reply[2];
47 	int ret;
48 
49 	ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
50 			   MEMX_INFO_DATA, 0);
51 	if (ret)
52 		return ret;
53 
54 	memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
55 	if (!memx)
56 		return -ENOMEM;
57 	memx->pmu = pmu;
58 	memx->base = reply[0];
59 	memx->size = reply[1];
60 
61 	/* acquire data segment access */
62 	do {
63 		nv_wr32(pmu, 0x10a580, 0x00000003);
64 	} while (nv_rd32(pmu, 0x10a580) != 0x00000003);
65 	nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
66 	return 0;
67 }
68 
69 int
70 nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
71 {
72 	struct nvkm_memx *memx = *pmemx;
73 	struct nvkm_pmu *pmu = memx->pmu;
74 	u32 finish, reply[2];
75 
76 	/* flush the cache... */
77 	memx_out(memx);
78 
79 	/* release data segment access */
80 	finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff;
81 	nv_wr32(pmu, 0x10a580, 0x00000000);
82 
83 	/* call MEMX process to execute the script, and wait for reply */
84 	if (exec) {
85 		pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
86 			     memx->base, finish);
87 	}
88 
89 	nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n",
90 		 reply[0], reply[1]);
91 	kfree(memx);
92 	return 0;
93 }
94 
95 void
96 nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data)
97 {
98 	nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data);
99 	memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
100 }
101 
102 void
103 nvkm_memx_wait(struct nvkm_memx *memx,
104 		  u32 addr, u32 mask, u32 data, u32 nsec)
105 {
106 	nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
107 				addr, mask, data, nsec);
108 	memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
109 	memx_out(memx); /* fuc can't handle multiple */
110 }
111 
112 void
113 nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
114 {
115 	nv_debug(memx->pmu, "    DELAY = %d ns\n", nsec);
116 	memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
117 	memx_out(memx); /* fuc can't handle multiple */
118 }
119 
120 void
121 nvkm_memx_wait_vblank(struct nvkm_memx *memx)
122 {
123 	struct nvkm_pmu *pmu = memx->pmu;
124 	u32 heads, x, y, px = 0;
125 	int i, head_sync;
126 
127 	if (nv_device(pmu)->chipset < 0xd0) {
128 		heads = nv_rd32(pmu, 0x610050);
129 		for (i = 0; i < 2; i++) {
130 			/* Heuristic: sync to head with biggest resolution */
131 			if (heads & (2 << (i << 3))) {
132 				x = nv_rd32(pmu, 0x610b40 + (0x540 * i));
133 				y = (x & 0xffff0000) >> 16;
134 				x &= 0x0000ffff;
135 				if ((x * y) > px) {
136 					px = (x * y);
137 					head_sync = i;
138 				}
139 			}
140 		}
141 	}
142 
143 	if (px == 0) {
144 		nv_debug(memx->pmu, "WAIT VBLANK !NO ACTIVE HEAD\n");
145 		return;
146 	}
147 
148 	nv_debug(memx->pmu, "WAIT VBLANK HEAD%d\n", head_sync);
149 	memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
150 	memx_out(memx); /* fuc can't handle multiple */
151 }
152 
153 void
154 nvkm_memx_train(struct nvkm_memx *memx)
155 {
156 	nv_debug(memx->pmu, "   MEM TRAIN\n");
157 	memx_cmd(memx, MEMX_TRAIN, 0, NULL);
158 }
159 
160 int
161 nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
162 {
163 	u32 reply[2], base, size, i;
164 	int ret;
165 
166 	ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
167 			   MEMX_INFO_TRAIN, 0);
168 	if (ret)
169 		return ret;
170 
171 	base = reply[0];
172 	size = reply[1] >> 2;
173 	if (size > rsize)
174 		return -ENOMEM;
175 
176 	/* read the packet */
177 	nv_wr32(pmu, 0x10a1c0, 0x02000000 | base);
178 
179 	for (i = 0; i < size; i++)
180 		res[i] = nv_rd32(pmu, 0x10a1c4);
181 
182 	return 0;
183 }
184 
185 void
186 nvkm_memx_block(struct nvkm_memx *memx)
187 {
188 	nv_debug(memx->pmu, "   HOST BLOCKED\n");
189 	memx_cmd(memx, MEMX_ENTER, 0, NULL);
190 }
191 
192 void
193 nvkm_memx_unblock(struct nvkm_memx *memx)
194 {
195 	nv_debug(memx->pmu, "   HOST UNBLOCKED\n");
196 	memx_cmd(memx, MEMX_LEAVE, 0, NULL);
197 }
198 #endif
199