1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 24 #include <subdev/clk.h> 25 #include <subdev/timer.h> 26 #include <subdev/volt.h> 27 28 #define BUSY_SLOT 0 29 #define CLK_SLOT 7 30 31 struct gk20a_pmu_dvfs_data { 32 int p_load_target; 33 int p_load_max; 34 int p_smooth; 35 unsigned int avg_load; 36 }; 37 38 struct gk20a_pmu { 39 struct nvkm_pmu base; 40 struct nvkm_alarm alarm; 41 struct gk20a_pmu_dvfs_data *data; 42 }; 43 44 struct gk20a_pmu_dvfs_dev_status { 45 unsigned long total; 46 unsigned long busy; 47 int cur_state; 48 }; 49 50 static int 51 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state) 52 { 53 struct nvkm_clk *clk = nvkm_clk(pmu); 54 55 return nvkm_clk_astate(clk, *state, 0, false); 56 } 57 58 static int 59 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) 60 { 61 struct nvkm_clk *clk = nvkm_clk(pmu); 62 63 *state = clk->pstate; 64 return 0; 65 } 66 67 static int 68 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, 69 int *state, int load) 70 { 71 struct gk20a_pmu_dvfs_data *data = pmu->data; 72 struct nvkm_clk *clk = nvkm_clk(pmu); 73 int cur_level, level; 74 75 /* For GK20A, the performance level is directly mapped to pstate */ 76 level = cur_level = clk->pstate; 77 78 if (load > data->p_load_max) { 79 level = min(clk->state_nr - 1, level + (clk->state_nr / 3)); 80 } else { 81 level += ((load - data->p_load_target) * 10 / 82 data->p_load_target) / 2; 83 level = max(0, level); 84 level = min(clk->state_nr - 1, level); 85 } 86 87 nv_trace(pmu, "cur level = %d, new level = %d\n", cur_level, level); 88 89 *state = level; 90 91 if (level == cur_level) 92 return 0; 93 else 94 return 1; 95 } 96 97 static int 98 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, 99 struct gk20a_pmu_dvfs_dev_status *status) 100 { 101 struct nvkm_device *device = pmu->base.subdev.device; 102 status->busy = nvkm_rd32(device, 0x10a508 + (BUSY_SLOT * 0x10)); 103 status->total= nvkm_rd32(device, 0x10a508 + (CLK_SLOT * 0x10)); 104 return 0; 105 } 106 107 static void 108 gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu *pmu) 109 { 110 struct nvkm_device *device = pmu->base.subdev.device; 111 nvkm_wr32(device, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000); 112 nvkm_wr32(device, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000); 113 } 114 115 static void 116 gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) 117 { 118 struct gk20a_pmu *pmu = 119 container_of(alarm, struct gk20a_pmu, alarm); 120 struct gk20a_pmu_dvfs_data *data = pmu->data; 121 struct gk20a_pmu_dvfs_dev_status status; 122 struct nvkm_clk *clk = nvkm_clk(pmu); 123 struct nvkm_volt *volt = nvkm_volt(pmu); 124 u32 utilization = 0; 125 int state, ret; 126 127 /* 128 * The PMU is initialized before CLK and VOLT, so we have to make sure the 129 * CLK and VOLT are ready here. 130 */ 131 if (!clk || !volt) 132 goto resched; 133 134 ret = gk20a_pmu_dvfs_get_dev_status(pmu, &status); 135 if (ret) { 136 nv_warn(pmu, "failed to get device status\n"); 137 goto resched; 138 } 139 140 if (status.total) 141 utilization = div_u64((u64)status.busy * 100, status.total); 142 143 data->avg_load = (data->p_smooth * data->avg_load) + utilization; 144 data->avg_load /= data->p_smooth + 1; 145 nv_trace(pmu, "utilization = %d %%, avg_load = %d %%\n", 146 utilization, data->avg_load); 147 148 ret = gk20a_pmu_dvfs_get_cur_state(pmu, &state); 149 if (ret) { 150 nv_warn(pmu, "failed to get current state\n"); 151 goto resched; 152 } 153 154 if (gk20a_pmu_dvfs_get_target_state(pmu, &state, data->avg_load)) { 155 nv_trace(pmu, "set new state to %d\n", state); 156 gk20a_pmu_dvfs_target(pmu, &state); 157 } 158 159 resched: 160 gk20a_pmu_dvfs_reset_dev_status(pmu); 161 nvkm_timer_alarm(pmu, 100000000, alarm); 162 } 163 164 static int 165 gk20a_pmu_fini(struct nvkm_object *object, bool suspend) 166 { 167 struct gk20a_pmu *pmu = (void *)object; 168 169 nvkm_timer_alarm_cancel(pmu, &pmu->alarm); 170 171 return nvkm_subdev_fini(&pmu->base.subdev, suspend); 172 } 173 174 static int 175 gk20a_pmu_init(struct nvkm_object *object) 176 { 177 struct gk20a_pmu *pmu = (void *)object; 178 struct nvkm_device *device = pmu->base.subdev.device; 179 int ret; 180 181 ret = nvkm_subdev_init(&pmu->base.subdev); 182 if (ret) 183 return ret; 184 185 pmu->base.pgob = nvkm_pmu_pgob; 186 187 /* init pwr perf counter */ 188 nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); 189 nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); 190 nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); 191 192 nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm); 193 return ret; 194 } 195 196 static struct gk20a_pmu_dvfs_data 197 gk20a_dvfs_data= { 198 .p_load_target = 70, 199 .p_load_max = 90, 200 .p_smooth = 1, 201 }; 202 203 static int 204 gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 205 struct nvkm_oclass *oclass, void *data, u32 size, 206 struct nvkm_object **pobject) 207 { 208 struct gk20a_pmu *pmu; 209 int ret; 210 211 ret = nvkm_pmu_create(parent, engine, oclass, &pmu); 212 *pobject = nv_object(pmu); 213 if (ret) 214 return ret; 215 216 pmu->data = &gk20a_dvfs_data; 217 218 nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work); 219 return 0; 220 } 221 222 struct nvkm_oclass * 223 gk20a_pmu_oclass = &(struct nvkm_pmu_impl) { 224 .base.handle = NV_SUBDEV(PMU, 0xea), 225 .base.ofuncs = &(struct nvkm_ofuncs) { 226 .ctor = gk20a_pmu_ctor, 227 .dtor = _nvkm_pmu_dtor, 228 .init = gk20a_pmu_init, 229 .fini = gk20a_pmu_fini, 230 }, 231 }.base; 232