1 /* 2 * Copyright 2015 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define gf110_pmu_code gk110_pmu_code 25 #define gf110_pmu_data gk110_pmu_data 26 #include "priv.h" 27 #include "fuc/gf110.fuc4.h" 28 29 #include <subdev/timer.h> 30 31 void 32 gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable) 33 { 34 static const struct { 35 u32 addr; 36 u32 data; 37 } magic[] = { 38 { 0x020520, 0xfffffffc }, 39 { 0x020524, 0xfffffffe }, 40 { 0x020524, 0xfffffffc }, 41 { 0x020524, 0xfffffff8 }, 42 { 0x020524, 0xffffffe0 }, 43 { 0x020530, 0xfffffffe }, 44 { 0x02052c, 0xfffffffa }, 45 { 0x02052c, 0xfffffff0 }, 46 { 0x02052c, 0xffffffc0 }, 47 { 0x02052c, 0xffffff00 }, 48 { 0x02052c, 0xfffffc00 }, 49 { 0x02052c, 0xfffcfc00 }, 50 { 0x02052c, 0xfff0fc00 }, 51 { 0x02052c, 0xff80fc00 }, 52 { 0x020528, 0xfffffffe }, 53 { 0x020528, 0xfffffffc }, 54 }; 55 int i; 56 57 nv_mask(pmu, 0x000200, 0x00001000, 0x00000000); 58 nv_rd32(pmu, 0x000200); 59 nv_mask(pmu, 0x000200, 0x08000000, 0x08000000); 60 msleep(50); 61 62 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002); 63 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); 64 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); 65 66 nv_mask(pmu, 0x0206b4, 0x00000000, 0x00000000); 67 for (i = 0; i < ARRAY_SIZE(magic); i++) { 68 nv_wr32(pmu, magic[i].addr, magic[i].data); 69 nv_wait(pmu, magic[i].addr, 0x80000000, 0x00000000); 70 } 71 72 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000); 73 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); 74 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); 75 76 nv_mask(pmu, 0x000200, 0x08000000, 0x00000000); 77 nv_mask(pmu, 0x000200, 0x00001000, 0x00001000); 78 nv_rd32(pmu, 0x000200); 79 } 80 81 struct nvkm_oclass * 82 gk110_pmu_oclass = &(struct nvkm_pmu_impl) { 83 .base.handle = NV_SUBDEV(PMU, 0xf0), 84 .base.ofuncs = &(struct nvkm_ofuncs) { 85 .ctor = _nvkm_pmu_ctor, 86 .dtor = _nvkm_pmu_dtor, 87 .init = _nvkm_pmu_init, 88 .fini = _nvkm_pmu_fini, 89 }, 90 .code.data = gk110_pmu_code, 91 .code.size = sizeof(gk110_pmu_code), 92 .data.data = gk110_pmu_data, 93 .data.size = sizeof(gk110_pmu_data), 94 .pgob = gk110_pmu_pgob, 95 }.base; 96