1 /* 2 * Copyright 2015 Nouveau Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "agp.h" 23 #ifdef __NVKM_PCI_AGP_H__ 24 #include <core/option.h> 25 26 struct nvkm_device_agp_quirk { 27 u16 hostbridge_vendor; 28 u16 hostbridge_device; 29 u16 chip_vendor; 30 u16 chip_device; 31 int mode; 32 }; 33 34 static const struct nvkm_device_agp_quirk 35 nvkm_device_agp_quirks[] = { 36 /* VIA Apollo PRO133x / GeForce FX 5600 Ultra - fdo#20341 */ 37 { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 }, 38 {}, 39 }; 40 41 void 42 nvkm_agp_fini(struct nvkm_pci *pci) 43 { 44 if (pci->agp.acquired) { 45 agp_backend_release(pci->agp.bridge); 46 pci->agp.acquired = false; 47 } 48 } 49 50 /* Ensure AGP controller is in a consistent state in case we need to 51 * execute the VBIOS DEVINIT scripts. 52 */ 53 void 54 nvkm_agp_preinit(struct nvkm_pci *pci) 55 { 56 struct nvkm_device *device = pci->subdev.device; 57 u32 mode = nvkm_pci_rd32(pci, 0x004c); 58 u32 save[2]; 59 60 /* First of all, disable fast writes, otherwise if it's already 61 * enabled in the AGP bridge and we disable the card's AGP 62 * controller we might be locking ourselves out of it. 63 */ 64 if ((mode | pci->agp.mode) & PCI_AGP_COMMAND_FW) { 65 mode = pci->agp.mode & ~PCI_AGP_COMMAND_FW; 66 agp_enable(pci->agp.bridge, mode); 67 } 68 69 /* clear busmaster bit, and disable AGP */ 70 save[0] = nvkm_pci_rd32(pci, 0x0004); 71 nvkm_pci_wr32(pci, 0x0004, save[0] & ~0x00000004); 72 nvkm_pci_wr32(pci, 0x004c, 0x00000000); 73 74 /* reset PGRAPH, PFIFO and PTIMER */ 75 save[1] = nvkm_mask(device, 0x000200, 0x00011100, 0x00000000); 76 nvkm_mask(device, 0x000200, 0x00011100, save[1]); 77 78 /* and restore busmaster bit (gives effect of resetting AGP) */ 79 nvkm_pci_wr32(pci, 0x0004, save[0]); 80 } 81 82 int 83 nvkm_agp_init(struct nvkm_pci *pci) 84 { 85 if (!agp_backend_acquire(pci->pdev)) { 86 nvkm_error(&pci->subdev, "failed to acquire agp\n"); 87 return -ENODEV; 88 } 89 90 agp_enable(pci->agp.bridge, pci->agp.mode); 91 pci->agp.acquired = true; 92 return 0; 93 } 94 95 void 96 nvkm_agp_dtor(struct nvkm_pci *pci) 97 { 98 arch_phys_wc_del(pci->agp.mtrr); 99 } 100 101 void 102 nvkm_agp_ctor(struct nvkm_pci *pci) 103 { 104 const struct nvkm_device_agp_quirk *quirk = nvkm_device_agp_quirks; 105 struct nvkm_subdev *subdev = &pci->subdev; 106 struct nvkm_device *device = subdev->device; 107 struct agp_kern_info info; 108 int mode = -1; 109 110 #ifdef __powerpc__ 111 /* Disable AGP by default on all PowerPC machines for now -- At 112 * least some UniNorth-2 AGP bridges are known to be broken: 113 * DMA from the host to the card works just fine, but writeback 114 * from the card to the host goes straight to memory 115 * untranslated bypassing that GATT somehow, making them quite 116 * painful to deal with... 117 */ 118 mode = 0; 119 #endif 120 mode = nvkm_longopt(device->cfgopt, "NvAGP", mode); 121 122 /* acquire bridge temporarily, so that we can copy its info */ 123 if (!(pci->agp.bridge = agp_backend_acquire(pci->pdev))) { 124 nvkm_warn(subdev, "failed to acquire agp\n"); 125 return; 126 } 127 agp_copy_info(pci->agp.bridge, &info); 128 agp_backend_release(pci->agp.bridge); 129 130 pci->agp.mode = info.mode; 131 pci->agp.base = info.aper_base; 132 pci->agp.size = info.aper_size * 1024 * 1024; 133 pci->agp.cma = info.cant_use_aperture; 134 pci->agp.mtrr = -1; 135 136 /* determine if bridge + chipset combination needs a workaround */ 137 while (quirk->hostbridge_vendor) { 138 if (info.device->vendor == quirk->hostbridge_vendor && 139 info.device->device == quirk->hostbridge_device && 140 pci->pdev->vendor == quirk->chip_vendor && 141 pci->pdev->device == quirk->chip_device) { 142 nvkm_info(subdev, "forcing default agp mode to %dX, " 143 "use NvAGP=<mode> to override\n", 144 quirk->mode); 145 mode = quirk->mode; 146 break; 147 } 148 quirk++; 149 } 150 151 /* apply quirk / user-specified mode */ 152 if (mode >= 1) { 153 if (pci->agp.mode & 0x00000008) 154 mode /= 4; /* AGPv3 */ 155 pci->agp.mode &= ~0x00000007; 156 pci->agp.mode |= (mode & 0x7); 157 } else 158 if (mode == 0) { 159 pci->agp.bridge = NULL; 160 return; 161 } 162 163 /* fast writes appear to be broken on nv18, they make the card 164 * lock up randomly. 165 */ 166 if (device->chipset == 0x18) 167 pci->agp.mode &= ~PCI_AGP_COMMAND_FW; 168 169 pci->agp.mtrr = arch_phys_wc_add(pci->agp.base, pci->agp.size); 170 } 171 #endif 172