1 /* 2 * Copyright 2010 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/mmu.h> 25 #include <subdev/bar.h> 26 #include <subdev/fb.h> 27 #include <subdev/timer.h> 28 29 #include <core/engine.h> 30 #include <core/gpuobj.h> 31 32 static void 33 nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2]) 34 { 35 u64 phys = 0xdeadcafe00000000ULL; 36 u32 coverage = 0; 37 38 if (pgt[0]) { 39 phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ 40 coverage = (pgt[0]->size >> 3) << 12; 41 } else 42 if (pgt[1]) { 43 phys = 0x00000001 | pgt[1]->addr; /* present */ 44 coverage = (pgt[1]->size >> 3) << 16; 45 } 46 47 if (phys & 1) { 48 if (coverage <= 32 * 1024 * 1024) 49 phys |= 0x60; 50 else if (coverage <= 64 * 1024 * 1024) 51 phys |= 0x40; 52 else if (coverage <= 128 * 1024 * 1024) 53 phys |= 0x20; 54 } 55 56 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); 57 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); 58 } 59 60 static inline u64 61 vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) 62 { 63 phys |= 1; /* present */ 64 phys |= (u64)memtype << 40; 65 phys |= target << 4; 66 if (vma->access & NV_MEM_ACCESS_SYS) 67 phys |= (1 << 6); 68 if (!(vma->access & NV_MEM_ACCESS_WO)) 69 phys |= (1 << 3); 70 return phys; 71 } 72 73 static void 74 nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 75 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 76 { 77 u32 comp = (mem->memtype & 0x180) >> 7; 78 u32 block, target; 79 int i; 80 81 /* IGPs don't have real VRAM, re-target to stolen system memory */ 82 target = 0; 83 if (nvkm_fb(vma->vm->mmu)->ram->stolen) { 84 phys += nvkm_fb(vma->vm->mmu)->ram->stolen; 85 target = 3; 86 } 87 88 phys = vm_addr(vma, phys, mem->memtype, target); 89 pte <<= 3; 90 cnt <<= 3; 91 92 while (cnt) { 93 u32 offset_h = upper_32_bits(phys); 94 u32 offset_l = lower_32_bits(phys); 95 96 for (i = 7; i >= 0; i--) { 97 block = 1 << (i + 3); 98 if (cnt >= block && !(pte & (block - 1))) 99 break; 100 } 101 offset_l |= (i << 7); 102 103 phys += block << (vma->node->type - 3); 104 cnt -= block; 105 if (comp) { 106 u32 tag = mem->tag->offset + ((delta >> 16) * comp); 107 offset_h |= (tag << 17); 108 delta += block << (vma->node->type - 3); 109 } 110 111 while (block) { 112 nv_wo32(pgt, pte + 0, offset_l); 113 nv_wo32(pgt, pte + 4, offset_h); 114 pte += 8; 115 block -= 8; 116 } 117 } 118 } 119 120 static void 121 nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 122 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 123 { 124 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; 125 pte <<= 3; 126 while (cnt--) { 127 u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); 128 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); 129 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); 130 pte += 8; 131 } 132 } 133 134 static void 135 nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) 136 { 137 pte <<= 3; 138 while (cnt--) { 139 nv_wo32(pgt, pte + 0, 0x00000000); 140 nv_wo32(pgt, pte + 4, 0x00000000); 141 pte += 8; 142 } 143 } 144 145 static void 146 nv50_vm_flush(struct nvkm_vm *vm) 147 { 148 struct nvkm_mmu *mmu = (void *)vm->mmu; 149 struct nvkm_device *device = mmu->subdev.device; 150 struct nvkm_bar *bar = device->bar; 151 struct nvkm_engine *engine; 152 int i, vme; 153 154 bar->flush(bar); 155 156 mutex_lock(&nv_subdev(mmu)->mutex); 157 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 158 if (!atomic_read(&vm->engref[i])) 159 continue; 160 161 /* unfortunate hw bug workaround... */ 162 engine = nvkm_engine(mmu, i); 163 if (engine && engine->tlb_flush) { 164 engine->tlb_flush(engine); 165 continue; 166 } 167 168 switch (i) { 169 case NVDEV_ENGINE_GR : vme = 0x00; break; 170 case NVDEV_ENGINE_VP : 171 case NVDEV_ENGINE_MSPDEC: vme = 0x01; break; 172 case NVDEV_SUBDEV_BAR : vme = 0x06; break; 173 case NVDEV_ENGINE_MSPPP : 174 case NVDEV_ENGINE_MPEG : vme = 0x08; break; 175 case NVDEV_ENGINE_BSP : 176 case NVDEV_ENGINE_MSVLD : vme = 0x09; break; 177 case NVDEV_ENGINE_CIPHER: 178 case NVDEV_ENGINE_SEC : vme = 0x0a; break; 179 case NVDEV_ENGINE_CE0 : vme = 0x0d; break; 180 default: 181 continue; 182 } 183 184 nvkm_wr32(device, 0x100c80, (vme << 16) | 1); 185 if (!nv_wait(mmu, 0x100c80, 0x00000001, 0x00000000)) 186 nv_error(mmu, "vm flush timeout: engine %d\n", vme); 187 } 188 mutex_unlock(&nv_subdev(mmu)->mutex); 189 } 190 191 static int 192 nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, 193 u64 mm_offset, struct nvkm_vm **pvm) 194 { 195 u32 block = (1 << (mmu->pgt_bits + 12)); 196 if (block > length) 197 block = length; 198 199 return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm); 200 } 201 202 static int 203 nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 204 struct nvkm_oclass *oclass, void *data, u32 size, 205 struct nvkm_object **pobject) 206 { 207 struct nvkm_mmu *mmu; 208 int ret; 209 210 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "mmu", &mmu); 211 *pobject = nv_object(mmu); 212 if (ret) 213 return ret; 214 215 mmu->limit = 1ULL << 40; 216 mmu->dma_bits = 40; 217 mmu->pgt_bits = 29 - 12; 218 mmu->spg_shift = 12; 219 mmu->lpg_shift = 16; 220 mmu->create = nv50_vm_create; 221 mmu->map_pgt = nv50_vm_map_pgt; 222 mmu->map = nv50_vm_map; 223 mmu->map_sg = nv50_vm_map_sg; 224 mmu->unmap = nv50_vm_unmap; 225 mmu->flush = nv50_vm_flush; 226 return 0; 227 } 228 229 struct nvkm_oclass 230 nv50_mmu_oclass = { 231 .handle = NV_SUBDEV(MMU, 0x50), 232 .ofuncs = &(struct nvkm_ofuncs) { 233 .ctor = nv50_mmu_ctor, 234 .dtor = _nvkm_mmu_dtor, 235 .init = _nvkm_mmu_init, 236 .fini = _nvkm_mmu_fini, 237 }, 238 }; 239