1 /* 2 * Copyright 2010 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/mmu.h> 25 #include <subdev/bar.h> 26 #include <subdev/fb.h> 27 #include <subdev/timer.h> 28 29 #include <core/engine.h> 30 #include <core/gpuobj.h> 31 32 static void 33 nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2]) 34 { 35 u64 phys = 0xdeadcafe00000000ULL; 36 u32 coverage = 0; 37 38 if (pgt[0]) { 39 phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ 40 coverage = (pgt[0]->size >> 3) << 12; 41 } else 42 if (pgt[1]) { 43 phys = 0x00000001 | pgt[1]->addr; /* present */ 44 coverage = (pgt[1]->size >> 3) << 16; 45 } 46 47 if (phys & 1) { 48 if (coverage <= 32 * 1024 * 1024) 49 phys |= 0x60; 50 else if (coverage <= 64 * 1024 * 1024) 51 phys |= 0x40; 52 else if (coverage <= 128 * 1024 * 1024) 53 phys |= 0x20; 54 } 55 56 nvkm_kmap(pgd); 57 nvkm_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); 58 nvkm_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); 59 nvkm_done(pgd); 60 } 61 62 static inline u64 63 vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) 64 { 65 phys |= 1; /* present */ 66 phys |= (u64)memtype << 40; 67 phys |= target << 4; 68 if (vma->access & NV_MEM_ACCESS_SYS) 69 phys |= (1 << 6); 70 if (!(vma->access & NV_MEM_ACCESS_WO)) 71 phys |= (1 << 3); 72 return phys; 73 } 74 75 static void 76 nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 77 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 78 { 79 u32 comp = (mem->memtype & 0x180) >> 7; 80 u32 block, target; 81 int i; 82 83 /* IGPs don't have real VRAM, re-target to stolen system memory */ 84 target = 0; 85 if (nvkm_fb(vma->vm->mmu)->ram->stolen) { 86 phys += nvkm_fb(vma->vm->mmu)->ram->stolen; 87 target = 3; 88 } 89 90 phys = vm_addr(vma, phys, mem->memtype, target); 91 pte <<= 3; 92 cnt <<= 3; 93 94 nvkm_kmap(pgt); 95 while (cnt) { 96 u32 offset_h = upper_32_bits(phys); 97 u32 offset_l = lower_32_bits(phys); 98 99 for (i = 7; i >= 0; i--) { 100 block = 1 << (i + 3); 101 if (cnt >= block && !(pte & (block - 1))) 102 break; 103 } 104 offset_l |= (i << 7); 105 106 phys += block << (vma->node->type - 3); 107 cnt -= block; 108 if (comp) { 109 u32 tag = mem->tag->offset + ((delta >> 16) * comp); 110 offset_h |= (tag << 17); 111 delta += block << (vma->node->type - 3); 112 } 113 114 while (block) { 115 nvkm_wo32(pgt, pte + 0, offset_l); 116 nvkm_wo32(pgt, pte + 4, offset_h); 117 pte += 8; 118 block -= 8; 119 } 120 } 121 nvkm_done(pgt); 122 } 123 124 static void 125 nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 126 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 127 { 128 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; 129 pte <<= 3; 130 nvkm_kmap(pgt); 131 while (cnt--) { 132 u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); 133 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys)); 134 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys)); 135 pte += 8; 136 } 137 nvkm_done(pgt); 138 } 139 140 static void 141 nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) 142 { 143 pte <<= 3; 144 nvkm_kmap(pgt); 145 while (cnt--) { 146 nvkm_wo32(pgt, pte + 0, 0x00000000); 147 nvkm_wo32(pgt, pte + 4, 0x00000000); 148 pte += 8; 149 } 150 nvkm_done(pgt); 151 } 152 153 static void 154 nv50_vm_flush(struct nvkm_vm *vm) 155 { 156 struct nvkm_mmu *mmu = (void *)vm->mmu; 157 struct nvkm_subdev *subdev = &mmu->subdev; 158 struct nvkm_device *device = subdev->device; 159 struct nvkm_bar *bar = device->bar; 160 struct nvkm_engine *engine; 161 int i, vme; 162 163 bar->flush(bar); 164 165 mutex_lock(&subdev->mutex); 166 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 167 if (!atomic_read(&vm->engref[i])) 168 continue; 169 170 /* unfortunate hw bug workaround... */ 171 engine = nvkm_engine(mmu, i); 172 if (engine && engine->tlb_flush) { 173 engine->tlb_flush(engine); 174 continue; 175 } 176 177 switch (i) { 178 case NVDEV_ENGINE_GR : vme = 0x00; break; 179 case NVDEV_ENGINE_VP : 180 case NVDEV_ENGINE_MSPDEC: vme = 0x01; break; 181 case NVDEV_SUBDEV_BAR : vme = 0x06; break; 182 case NVDEV_ENGINE_MSPPP : 183 case NVDEV_ENGINE_MPEG : vme = 0x08; break; 184 case NVDEV_ENGINE_BSP : 185 case NVDEV_ENGINE_MSVLD : vme = 0x09; break; 186 case NVDEV_ENGINE_CIPHER: 187 case NVDEV_ENGINE_SEC : vme = 0x0a; break; 188 case NVDEV_ENGINE_CE0 : vme = 0x0d; break; 189 default: 190 continue; 191 } 192 193 nvkm_wr32(device, 0x100c80, (vme << 16) | 1); 194 if (nvkm_msec(device, 2000, 195 if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) 196 break; 197 ) < 0) 198 nvkm_error(subdev, "vm flush timeout: engine %d\n", vme); 199 } 200 mutex_unlock(&subdev->mutex); 201 } 202 203 static int 204 nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, 205 u64 mm_offset, struct nvkm_vm **pvm) 206 { 207 u32 block = (1 << (mmu->pgt_bits + 12)); 208 if (block > length) 209 block = length; 210 211 return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm); 212 } 213 214 static int 215 nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 216 struct nvkm_oclass *oclass, void *data, u32 size, 217 struct nvkm_object **pobject) 218 { 219 struct nvkm_mmu *mmu; 220 int ret; 221 222 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "mmu", &mmu); 223 *pobject = nv_object(mmu); 224 if (ret) 225 return ret; 226 227 mmu->limit = 1ULL << 40; 228 mmu->dma_bits = 40; 229 mmu->pgt_bits = 29 - 12; 230 mmu->spg_shift = 12; 231 mmu->lpg_shift = 16; 232 mmu->create = nv50_vm_create; 233 mmu->map_pgt = nv50_vm_map_pgt; 234 mmu->map = nv50_vm_map; 235 mmu->map_sg = nv50_vm_map_sg; 236 mmu->unmap = nv50_vm_unmap; 237 mmu->flush = nv50_vm_flush; 238 return 0; 239 } 240 241 struct nvkm_oclass 242 nv50_mmu_oclass = { 243 .handle = NV_SUBDEV(MMU, 0x50), 244 .ofuncs = &(struct nvkm_ofuncs) { 245 .ctor = nv50_mmu_ctor, 246 .dtor = _nvkm_mmu_dtor, 247 .init = _nvkm_mmu_init, 248 .fini = _nvkm_mmu_fini, 249 }, 250 }; 251