1 /* 2 * Copyright 2010 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <subdev/fb.h> 27 #include <subdev/timer.h> 28 29 #include <core/engine.h> 30 #include <core/gpuobj.h> 31 32 static void 33 nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_memory *pgt[2]) 34 { 35 u64 phys = 0xdeadcafe00000000ULL; 36 u32 coverage = 0; 37 38 if (pgt[0]) { 39 /* present, 4KiB pages */ 40 phys = 0x00000003 | nvkm_memory_addr(pgt[0]); 41 coverage = (nvkm_memory_size(pgt[0]) >> 3) << 12; 42 } else 43 if (pgt[1]) { 44 /* present, 64KiB pages */ 45 phys = 0x00000001 | nvkm_memory_addr(pgt[1]); 46 coverage = (nvkm_memory_size(pgt[1]) >> 3) << 16; 47 } 48 49 if (phys & 1) { 50 if (coverage <= 32 * 1024 * 1024) 51 phys |= 0x60; 52 else if (coverage <= 64 * 1024 * 1024) 53 phys |= 0x40; 54 else if (coverage <= 128 * 1024 * 1024) 55 phys |= 0x20; 56 } 57 58 nvkm_kmap(pgd); 59 nvkm_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); 60 nvkm_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); 61 nvkm_done(pgd); 62 } 63 64 static inline u64 65 vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) 66 { 67 phys |= 1; /* present */ 68 phys |= (u64)memtype << 40; 69 phys |= target << 4; 70 if (vma->access & NV_MEM_ACCESS_SYS) 71 phys |= (1 << 6); 72 if (!(vma->access & NV_MEM_ACCESS_WO)) 73 phys |= (1 << 3); 74 return phys; 75 } 76 77 static void 78 nv50_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt, 79 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 80 { 81 struct nvkm_ram *ram = vma->vm->mmu->subdev.device->fb->ram; 82 u32 comp = (mem->memtype & 0x180) >> 7; 83 u32 block, target; 84 int i; 85 86 /* IGPs don't have real VRAM, re-target to stolen system memory */ 87 target = 0; 88 if (ram->stolen) { 89 phys += ram->stolen; 90 target = 3; 91 } 92 93 phys = vm_addr(vma, phys, mem->memtype, target); 94 pte <<= 3; 95 cnt <<= 3; 96 97 nvkm_kmap(pgt); 98 while (cnt) { 99 u32 offset_h = upper_32_bits(phys); 100 u32 offset_l = lower_32_bits(phys); 101 102 for (i = 7; i >= 0; i--) { 103 block = 1 << (i + 3); 104 if (cnt >= block && !(pte & (block - 1))) 105 break; 106 } 107 offset_l |= (i << 7); 108 109 phys += block << (vma->node->type - 3); 110 cnt -= block; 111 if (comp) { 112 u32 tag = mem->tag->offset + ((delta >> 16) * comp); 113 offset_h |= (tag << 17); 114 delta += block << (vma->node->type - 3); 115 } 116 117 while (block) { 118 nvkm_wo32(pgt, pte + 0, offset_l); 119 nvkm_wo32(pgt, pte + 4, offset_h); 120 pte += 8; 121 block -= 8; 122 } 123 } 124 nvkm_done(pgt); 125 } 126 127 static void 128 nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt, 129 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 130 { 131 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; 132 pte <<= 3; 133 nvkm_kmap(pgt); 134 while (cnt--) { 135 u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); 136 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys)); 137 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys)); 138 pte += 8; 139 } 140 nvkm_done(pgt); 141 } 142 143 static void 144 nv50_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt) 145 { 146 pte <<= 3; 147 nvkm_kmap(pgt); 148 while (cnt--) { 149 nvkm_wo32(pgt, pte + 0, 0x00000000); 150 nvkm_wo32(pgt, pte + 4, 0x00000000); 151 pte += 8; 152 } 153 nvkm_done(pgt); 154 } 155 156 static void 157 nv50_vm_flush(struct nvkm_vm *vm) 158 { 159 struct nvkm_mmu *mmu = vm->mmu; 160 struct nvkm_subdev *subdev = &mmu->subdev; 161 struct nvkm_device *device = subdev->device; 162 int i, vme; 163 164 mutex_lock(&subdev->mutex); 165 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 166 if (!atomic_read(&vm->engref[i])) 167 continue; 168 169 /* unfortunate hw bug workaround... */ 170 if (i == NVDEV_ENGINE_GR) { 171 struct nvkm_engine *engine = 172 nvkm_device_engine(device, i); 173 if (engine && engine->tlb_flush) { 174 engine->tlb_flush(engine); 175 continue; 176 } 177 } 178 179 switch (i) { 180 case NVDEV_ENGINE_GR : vme = 0x00; break; 181 case NVDEV_ENGINE_VP : 182 case NVDEV_ENGINE_MSPDEC: vme = 0x01; break; 183 case NVDEV_SUBDEV_BAR : vme = 0x06; break; 184 case NVDEV_ENGINE_MSPPP : 185 case NVDEV_ENGINE_MPEG : vme = 0x08; break; 186 case NVDEV_ENGINE_BSP : 187 case NVDEV_ENGINE_MSVLD : vme = 0x09; break; 188 case NVDEV_ENGINE_CIPHER: 189 case NVDEV_ENGINE_SEC : vme = 0x0a; break; 190 case NVDEV_ENGINE_CE0 : vme = 0x0d; break; 191 default: 192 continue; 193 } 194 195 nvkm_wr32(device, 0x100c80, (vme << 16) | 1); 196 if (nvkm_msec(device, 2000, 197 if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) 198 break; 199 ) < 0) 200 nvkm_error(subdev, "vm flush timeout: engine %d\n", vme); 201 } 202 mutex_unlock(&subdev->mutex); 203 } 204 205 static int 206 nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, 207 struct lock_class_key *key, struct nvkm_vm **pvm) 208 { 209 u32 block = (1 << (mmu->func->pgt_bits + 12)); 210 if (block > length) 211 block = length; 212 213 return nvkm_vm_create(mmu, offset, length, mm_offset, block, key, pvm); 214 } 215 216 static const struct nvkm_mmu_func 217 nv50_mmu = { 218 .limit = (1ULL << 40), 219 .dma_bits = 40, 220 .pgt_bits = 29 - 12, 221 .spg_shift = 12, 222 .lpg_shift = 16, 223 .create = nv50_vm_create, 224 .map_pgt = nv50_vm_map_pgt, 225 .map = nv50_vm_map, 226 .map_sg = nv50_vm_map_sg, 227 .unmap = nv50_vm_unmap, 228 .flush = nv50_vm_flush, 229 }; 230 231 int 232 nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) 233 { 234 return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu); 235 } 236