1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv04.h"
25 
26 #include <core/gpuobj.h>
27 #include <core/option.h>
28 #include <subdev/timer.h>
29 
30 #define NV41_GART_SIZE (512 * 1024 * 1024)
31 #define NV41_GART_PAGE (  4 * 1024)
32 
33 /*******************************************************************************
34  * VM map/unmap callbacks
35  ******************************************************************************/
36 
37 static void
38 nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
39 	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
40 {
41 	pte = pte * 4;
42 	while (cnt) {
43 		u32 page = PAGE_SIZE / NV41_GART_PAGE;
44 		u64 phys = (u64)*list++;
45 		while (cnt && page--) {
46 			nv_wo32(pgt, pte, (phys >> 7) | 1);
47 			phys += NV41_GART_PAGE;
48 			pte += 4;
49 			cnt -= 1;
50 		}
51 	}
52 }
53 
54 static void
55 nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
56 {
57 	pte = pte * 4;
58 	while (cnt--) {
59 		nv_wo32(pgt, pte, 0x00000000);
60 		pte += 4;
61 	}
62 }
63 
64 static void
65 nv41_vm_flush(struct nvkm_vm *vm)
66 {
67 	struct nv04_mmu *mmu = (void *)vm->mmu;
68 	struct nvkm_device *device = mmu->base.subdev.device;
69 
70 	mutex_lock(&nv_subdev(mmu)->mutex);
71 	nvkm_wr32(device, 0x100810, 0x00000022);
72 	if (!nv_wait(mmu, 0x100810, 0x00000020, 0x00000020)) {
73 		nv_warn(mmu, "flush timeout, 0x%08x\n",
74 			nvkm_rd32(device, 0x100810));
75 	}
76 	nvkm_wr32(device, 0x100810, 0x00000000);
77 	mutex_unlock(&nv_subdev(mmu)->mutex);
78 }
79 
80 /*******************************************************************************
81  * MMU subdev
82  ******************************************************************************/
83 
84 static int
85 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
86 	      struct nvkm_oclass *oclass, void *data, u32 size,
87 	      struct nvkm_object **pobject)
88 {
89 	struct nvkm_device *device = nv_device(parent);
90 	struct nv04_mmu *mmu;
91 	int ret;
92 
93 	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
94 	    !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
95 		return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
96 					data, size, pobject);
97 	}
98 
99 	ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
100 			      "mmu", &mmu);
101 	*pobject = nv_object(mmu);
102 	if (ret)
103 		return ret;
104 
105 	mmu->base.create = nv04_vm_create;
106 	mmu->base.limit = NV41_GART_SIZE;
107 	mmu->base.dma_bits = 39;
108 	mmu->base.pgt_bits = 32 - 12;
109 	mmu->base.spg_shift = 12;
110 	mmu->base.lpg_shift = 12;
111 	mmu->base.map_sg = nv41_vm_map_sg;
112 	mmu->base.unmap = nv41_vm_unmap;
113 	mmu->base.flush = nv41_vm_flush;
114 
115 	ret = nvkm_vm_create(&mmu->base, 0, NV41_GART_SIZE, 0, 4096,
116 			     &mmu->vm);
117 	if (ret)
118 		return ret;
119 
120 	ret = nvkm_gpuobj_new(nv_object(mmu), NULL,
121 			      (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
122 			      NVOBJ_FLAG_ZERO_ALLOC,
123 			      &mmu->vm->pgt[0].obj[0]);
124 	mmu->vm->pgt[0].refcount[0] = 1;
125 	if (ret)
126 		return ret;
127 
128 	return 0;
129 }
130 
131 static int
132 nv41_mmu_init(struct nvkm_object *object)
133 {
134 	struct nv04_mmu *mmu = (void *)object;
135 	struct nvkm_device *device = mmu->base.subdev.device;
136 	struct nvkm_gpuobj *dma = mmu->vm->pgt[0].obj[0];
137 	int ret;
138 
139 	ret = nvkm_mmu_init(&mmu->base);
140 	if (ret)
141 		return ret;
142 
143 	nvkm_wr32(device, 0x100800, dma->addr | 0x00000002);
144 	nvkm_mask(device, 0x10008c, 0x00000100, 0x00000100);
145 	nvkm_wr32(device, 0x100820, 0x00000000);
146 	return 0;
147 }
148 
149 struct nvkm_oclass
150 nv41_mmu_oclass = {
151 	.handle = NV_SUBDEV(MMU, 0x41),
152 	.ofuncs = &(struct nvkm_ofuncs) {
153 		.ctor = nv41_mmu_ctor,
154 		.dtor = nv04_mmu_dtor,
155 		.init = nv41_mmu_init,
156 		.fini = _nvkm_mmu_fini,
157 	},
158 };
159